[llvm] [RISCV] Use lookup tables to find CVTFOpc (PR #88742)
Michael Maitland via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 16 08:17:53 PDT 2024
https://github.com/michaelmaitland updated https://github.com/llvm/llvm-project/pull/88742
>From 222a3b6ab7d9b85f1c851de4f4ca318530527365 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Mon, 15 Apr 2024 07:42:07 -0700
Subject: [PATCH 1/5] [RISCV][NFC] Move RISCVMaskedPseudoTable to
RISCVInstrInfo
---
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 1 -
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h | 9 ---------
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 7 +++++++
llvm/lib/Target/RISCV/RISCVInstrInfo.h | 12 ++++++++++++
4 files changed, 19 insertions(+), 10 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index f99dc0b8576368..b0568297a470a7 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -43,7 +43,6 @@ namespace llvm::RISCV {
#define GET_RISCVVSETable_IMPL
#define GET_RISCVVLXTable_IMPL
#define GET_RISCVVSXTable_IMPL
-#define GET_RISCVMaskedPseudosTable_IMPL
#include "RISCVGenSearchableTables.inc"
} // namespace llvm::RISCV
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
index 92f818b0dc4891..7d4aec2dfdc984 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
@@ -261,13 +261,6 @@ struct VLX_VSXPseudo {
uint16_t Pseudo;
};
-struct RISCVMaskedPseudoInfo {
- uint16_t MaskedPseudo;
- uint16_t UnmaskedPseudo;
- uint8_t MaskOpIdx;
- uint8_t MaskAffectsResult : 1;
-};
-
#define GET_RISCVVSSEGTable_DECL
#define GET_RISCVVLSEGTable_DECL
#define GET_RISCVVLXSEGTable_DECL
@@ -276,8 +269,6 @@ struct RISCVMaskedPseudoInfo {
#define GET_RISCVVSETable_DECL
#define GET_RISCVVLXTable_DECL
#define GET_RISCVVSXTable_DECL
-#define GET_RISCVMaskedPseudosTable_DECL
-#include "RISCVGenSearchableTables.inc"
} // namespace RISCV
} // namespace llvm
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 508f607fab20fd..a2717ba495f216 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -66,6 +66,13 @@ using namespace RISCV;
} // namespace llvm::RISCVVPseudosTable
+namespace llvm::RISCV {
+
+#define GET_RISCVMaskedPseudosTable_IMPL
+#include "RISCVGenSearchableTables.inc"
+
+} // end namespace llvm::RISCV
+
RISCVInstrInfo::RISCVInstrInfo(RISCVSubtarget &STI)
: RISCVGenInstrInfo(RISCV::ADJCALLSTACKDOWN, RISCV::ADJCALLSTACKUP),
STI(STI) {}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index 70fe7da85be0e7..3b03d5efde6ef5 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -359,5 +359,17 @@ struct PseudoInfo {
} // end namespace RISCVVPseudosTable
+namespace RISCV {
+
+struct RISCVMaskedPseudoInfo {
+ uint16_t MaskedPseudo;
+ uint16_t UnmaskedPseudo;
+ uint8_t MaskOpIdx;
+ uint8_t MaskAffectsResult : 1;
+};
+#define GET_RISCVMaskedPseudosTable_DECL
+#include "RISCVGenSearchableTables.inc"
+} // end namespace RISCV
+
} // end namespace llvm
#endif
>From 8a256c901625b644958b69f75beeea3d4a3492ac Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Mon, 15 Apr 2024 07:42:59 -0700
Subject: [PATCH 2/5] [RISCV][NFC] Include RISCVVInversePseudosTable in
RISCVInstrInfo
---
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 9 +++++++++
llvm/lib/Target/RISCV/RISCVInstrInfo.h | 14 ++++++++++++++
2 files changed, 23 insertions(+)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index a2717ba495f216..c407958912ab2e 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -66,6 +66,15 @@ using namespace RISCV;
} // namespace llvm::RISCVVPseudosTable
+namespace llvm::RISCVVInversePseudosTable {
+
+using namespace RISCV;
+
+#define GET_RISCVVInversePseudosTable_IMPL
+#include "RISCVGenSearchableTables.inc"
+
+} // end namespace llvm::RISCVVInversePseudosTable
+
namespace llvm::RISCV {
#define GET_RISCVMaskedPseudosTable_IMPL
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index 3b03d5efde6ef5..788f2f568765f0 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -359,6 +359,20 @@ struct PseudoInfo {
} // end namespace RISCVVPseudosTable
+namespace RISCVVInversePseudosTable {
+
+struct PseudoInfo {
+ uint16_t Pseudo;
+ uint16_t BaseInstr;
+ uint8_t VLMul;
+ uint8_t SEW;
+};
+
+#define GET_RISCVVInversePseudosTable_DECL
+#include "RISCVGenSearchableTables.inc"
+
+} // end namespace RISCVVInversePseudosTable
+
namespace RISCV {
struct RISCVMaskedPseudoInfo {
>From 37e883c68e45a9f4326d054dc82e135563cde954 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Mon, 15 Apr 2024 07:45:38 -0700
Subject: [PATCH 3/5] [RISCV] Use lookup tables to find CVTFOpc
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 81 ++-----------------
.../Target/RISCV/RISCVInstrInfoVPseudos.td | 6 +-
2 files changed, 10 insertions(+), 77 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 27387595164a46..9d62af44097cdc 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -17677,80 +17677,13 @@ static MachineBasicBlock *emitVFROUND_NOEXCEPT_MASK(MachineInstr &MI,
unsigned Log2SEW = MI.getOperand(RISCVII::getSEWOpNum(MI.getDesc())).getImm();
// There is no E8 variant for VFCVT_F_X.
assert(Log2SEW >= 4);
- // Since MI (VFROUND) isn't SEW specific, we cannot use a macro to make
- // handling of different (LMUL, SEW) pairs easier because we need to pull the
- // SEW immediate from MI, and that information is not avaliable during macro
- // expansion.
- unsigned CVTFOpc;
- if (Log2SEW == 4) {
- switch (LMul) {
- case RISCVII::LMUL_1:
- CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M1_E16_MASK;
- break;
- case RISCVII::LMUL_2:
- CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M2_E16_MASK;
- break;
- case RISCVII::LMUL_4:
- CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M4_E16_MASK;
- break;
- case RISCVII::LMUL_8:
- CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M8_E16_MASK;
- break;
- case RISCVII::LMUL_F2:
- CVTFOpc = RISCV::PseudoVFCVT_F_X_V_MF2_E16_MASK;
- break;
- case RISCVII::LMUL_F4:
- CVTFOpc = RISCV::PseudoVFCVT_F_X_V_MF4_E16_MASK;
- break;
- case RISCVII::LMUL_F8:
- case RISCVII::LMUL_RESERVED:
- llvm_unreachable("Unexpected LMUL and SEW combination value for MI.");
- }
- } else if (Log2SEW == 5) {
- switch (LMul) {
- case RISCVII::LMUL_1:
- CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M1_E32_MASK;
- break;
- case RISCVII::LMUL_2:
- CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M2_E32_MASK;
- break;
- case RISCVII::LMUL_4:
- CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M4_E32_MASK;
- break;
- case RISCVII::LMUL_8:
- CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M8_E32_MASK;
- break;
- case RISCVII::LMUL_F2:
- CVTFOpc = RISCV::PseudoVFCVT_F_X_V_MF2_E32_MASK;
- break;
- case RISCVII::LMUL_F4:
- case RISCVII::LMUL_F8:
- case RISCVII::LMUL_RESERVED:
- llvm_unreachable("Unexpected LMUL and SEW combination value for MI.");
- }
- } else if (Log2SEW == 6) {
- switch (LMul) {
- case RISCVII::LMUL_1:
- CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M1_E64_MASK;
- break;
- case RISCVII::LMUL_2:
- CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M2_E64_MASK;
- break;
- case RISCVII::LMUL_4:
- CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M4_E64_MASK;
- break;
- case RISCVII::LMUL_8:
- CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M8_E64_MASK;
- break;
- case RISCVII::LMUL_F2:
- case RISCVII::LMUL_F4:
- case RISCVII::LMUL_F8:
- case RISCVII::LMUL_RESERVED:
- llvm_unreachable("Unexpected LMUL and SEW combination value for MI.");
- }
- } else {
- llvm_unreachable("Unexpected LMUL and SEW combination value for MI.");
- }
+ const RISCVVInversePseudosTable::PseudoInfo *Inverse =
+ RISCVVInversePseudosTable::getBaseInfo(RISCV::VFCVT_F_X_V, LMul,
+ 1 << Log2SEW);
+ assert(Inverse && "Unexpected LMUL and SEW pair for VFCVT_F_X_V instruction");
+ auto *Masked = RISCV::lookupMaskedIntrinsicByUnmasked(Inverse->Pseudo);
+ assert(Masked && "Could not find masked VFCVT_F_X_V instruction");
+ unsigned CVTFOpc = Masked->MaskedPseudo;
BuildMI(*BB, MI, DL, TII.get(CVTFOpc))
.add(MI.getOperand(0))
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index ad1821d57256bc..8b0352c76598af 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -3585,7 +3585,7 @@ multiclass VPseudoConversion<VReg RetClass,
int sew = 0,
int TargetConstraintType = 1> {
defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX);
- let VLMul = MInfo.value in {
+ let VLMul = MInfo.value, SEW=sew in {
def suffix : VPseudoUnaryNoMask<RetClass, Op1Class, Constraint, TargetConstraintType>;
def suffix # "_MASK" : VPseudoUnaryMask<RetClass, Op1Class,
Constraint, TargetConstraintType>,
@@ -3599,7 +3599,7 @@ multiclass VPseudoConversionRoundingMode<VReg RetClass,
string Constraint = "",
int sew = 0,
int TargetConstraintType = 1> {
- let VLMul = MInfo.value in {
+ let VLMul = MInfo.value, SEW=sew in {
defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX);
def suffix : VPseudoUnaryNoMaskRoundingMode<RetClass, Op1Class, Constraint, TargetConstraintType>;
def suffix # "_MASK" : VPseudoUnaryMaskRoundingMode<RetClass, Op1Class,
@@ -3616,7 +3616,7 @@ multiclass VPseudoConversionRM<VReg RetClass,
string Constraint = "",
int sew = 0,
int TargetConstraintType = 1> {
- let VLMul = MInfo.value in {
+ let VLMul = MInfo.value, SEW=sew in {
defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX);
def suffix : VPseudoUnaryNoMask_FRM<RetClass, Op1Class,
Constraint, TargetConstraintType>;
>From 65179e385ec5f70743d0f5438d46ab8075b75640 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Tue, 16 Apr 2024 08:16:19 -0700
Subject: [PATCH 4/5] [RISCV] Move RISCVInversePseudosTable to
RISCVMCTargetDesc.h
This is moved to a common header to remove duplicated code in MCA and
RISCVInstrInfo.
---
.../Target/RISCV/MCA/RISCVCustomBehaviour.cpp | 15 ---------------
.../RISCV/MCTargetDesc/RISCVMCTargetDesc.h | 16 +++++++++++++++-
llvm/lib/Target/RISCV/RISCVInstrInfo.h | 14 --------------
3 files changed, 15 insertions(+), 30 deletions(-)
diff --git a/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp b/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
index 8d97c5ffd20a05..5aeea2c18cb7e0 100644
--- a/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
+++ b/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
@@ -20,24 +20,9 @@
#define DEBUG_TYPE "llvm-mca-riscv-custombehaviour"
-// This brings in a table with primary key of
-// base instruction opcode and lmul and maps
-// to the opcode of the pseudo instruction.
namespace RISCVVInversePseudosTable {
-using namespace llvm;
-using namespace llvm::RISCV;
-
-struct PseudoInfo {
- uint16_t Pseudo;
- uint16_t BaseInstr;
- uint8_t VLMul;
- uint8_t SEW;
-};
-
#define GET_RISCVVInversePseudosTable_IMPL
-#define GET_RISCVVInversePseudosTable_DECL
#include "RISCVGenSearchableTables.inc"
-
} // end namespace RISCVVInversePseudosTable
namespace llvm {
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h
index 3cfddb530cdf63..d4aa0fe99078e1 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h
@@ -37,7 +37,21 @@ MCAsmBackend *createRISCVAsmBackend(const Target &T, const MCSubtargetInfo &STI,
std::unique_ptr<MCObjectTargetWriter> createRISCVELFObjectWriter(uint8_t OSABI,
bool Is64Bit);
-}
+
+namespace RISCVVInversePseudosTable {
+
+struct PseudoInfo {
+ uint16_t Pseudo;
+ uint16_t BaseInstr;
+ uint8_t VLMul;
+ uint8_t SEW;
+};
+
+#define GET_RISCVVInversePseudosTable_DECL
+#include "RISCVGenSearchableTables.inc"
+
+} // namespace RISCVVInversePseudosTable
+} // namespace llvm
// Defines symbolic names for RISC-V registers.
#define GET_REGINFO_ENUM
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index 788f2f568765f0..3b03d5efde6ef5 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -359,20 +359,6 @@ struct PseudoInfo {
} // end namespace RISCVVPseudosTable
-namespace RISCVVInversePseudosTable {
-
-struct PseudoInfo {
- uint16_t Pseudo;
- uint16_t BaseInstr;
- uint8_t VLMul;
- uint8_t SEW;
-};
-
-#define GET_RISCVVInversePseudosTable_DECL
-#include "RISCVGenSearchableTables.inc"
-
-} // end namespace RISCVVInversePseudosTable
-
namespace RISCV {
struct RISCVMaskedPseudoInfo {
>From 3d4350a20c8be5ca40a23d855e415fb9537d66f4 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Tue, 16 Apr 2024 08:16:47 -0700
Subject: [PATCH 5/5] [RISCV] Add and use helper lookupMaskedIntrinsic
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 10 +++-------
llvm/lib/Target/RISCV/RISCVInstrInfo.h | 12 ++++++++++++
2 files changed, 15 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 9d62af44097cdc..1b936d95fcfb2f 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -17677,13 +17677,9 @@ static MachineBasicBlock *emitVFROUND_NOEXCEPT_MASK(MachineInstr &MI,
unsigned Log2SEW = MI.getOperand(RISCVII::getSEWOpNum(MI.getDesc())).getImm();
// There is no E8 variant for VFCVT_F_X.
assert(Log2SEW >= 4);
- const RISCVVInversePseudosTable::PseudoInfo *Inverse =
- RISCVVInversePseudosTable::getBaseInfo(RISCV::VFCVT_F_X_V, LMul,
- 1 << Log2SEW);
- assert(Inverse && "Unexpected LMUL and SEW pair for VFCVT_F_X_V instruction");
- auto *Masked = RISCV::lookupMaskedIntrinsicByUnmasked(Inverse->Pseudo);
- assert(Masked && "Could not find masked VFCVT_F_X_V instruction");
- unsigned CVTFOpc = Masked->MaskedPseudo;
+ unsigned CVTFOpc =
+ RISCV::lookupMaskedIntrinsic(RISCV::VFCVT_F_X_V, LMul, 1 << Log2SEW)
+ ->MaskedPseudo;
BuildMI(*BB, MI, DL, TII.get(CVTFOpc))
.add(MI.getOperand(0))
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index 3b03d5efde6ef5..9275caadb6fd28 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -369,6 +369,18 @@ struct RISCVMaskedPseudoInfo {
};
#define GET_RISCVMaskedPseudosTable_DECL
#include "RISCVGenSearchableTables.inc"
+
+// Helper to find Masked Pseudo instruction from MC instruction, LMUL and SEW.
+static const RISCVMaskedPseudoInfo *
+lookupMaskedIntrinsic(uint16_t MCOpcode, RISCVII::VLMUL LMul, unsigned SEW) {
+ const RISCVVInversePseudosTable::PseudoInfo *Inverse =
+ RISCVVInversePseudosTable::getBaseInfo(MCOpcode, LMul, SEW);
+ assert(Inverse && "Unexpected LMUL and SEW pair for instruction");
+ const RISCVMaskedPseudoInfo *Masked =
+ RISCV::lookupMaskedIntrinsicByUnmasked(Inverse->Pseudo);
+ assert(Masked && "Could not find masked instruction for LMUL and SEW pair");
+ return Masked;
+}
} // end namespace RISCV
} // end namespace llvm
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