[llvm] [M68k] Add support for MOVEQ instruction (PR #88542)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 12 10:38:54 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-m68k
Author: Peter Lafreniere (n8pjl)
<details>
<summary>Changes</summary>
Add support for the moveq instruction, which is both faster and smaller
(1/2 to 1/3 the size) than a move with immediate to register.
This change introduces the instruction, along with a set of
pseudoinstructions to handle immediate moves to a register that is
lowered post-RA.
Pseudos are used as moveq can only write to the full register, which makes
matching i8 and i16 immediate loads difficult in tablegen. Furthermore,
selecting moveq before RA constrains that immediate to be moved into a data
register, which may not be optimal.
The bulk of this change are fixes to existing tests, which cover the new
functionality sufficiently.
---
Patch is 31.84 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/88542.diff
25 Files Affected:
- (modified) llvm/lib/Target/M68k/M68kExpandPseudo.cpp (+7)
- (modified) llvm/lib/Target/M68k/M68kInstrData.td (+38-3)
- (modified) llvm/lib/Target/M68k/M68kInstrInfo.cpp (+34)
- (modified) llvm/lib/Target/M68k/M68kInstrInfo.h (+3)
- (modified) llvm/test/CodeGen/M68k/Arith/add-with-overflow.ll (+1-1)
- (modified) llvm/test/CodeGen/M68k/Arith/add.ll (+2-2)
- (modified) llvm/test/CodeGen/M68k/Arith/bitwise.ll (+3-3)
- (modified) llvm/test/CodeGen/M68k/Arith/divide-by-constant.ll (+7-7)
- (modified) llvm/test/CodeGen/M68k/Arith/imul.ll (+8-8)
- (modified) llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll (+6-6)
- (modified) llvm/test/CodeGen/M68k/Arith/sub-with-overflow.ll (+5-5)
- (modified) llvm/test/CodeGen/M68k/Arith/sub.ll (+1-1)
- (modified) llvm/test/CodeGen/M68k/Arith/umul-with-overflow.ll (+3-3)
- (modified) llvm/test/CodeGen/M68k/CConv/c-call.ll (+3-3)
- (modified) llvm/test/CodeGen/M68k/CConv/fastcc-call.ll (+6-6)
- (modified) llvm/test/CodeGen/M68k/CodeModel/medium-pie-global-access.ll (+2-2)
- (modified) llvm/test/CodeGen/M68k/CodeModel/small-pie-global-access.ll (+2-2)
- (modified) llvm/test/CodeGen/M68k/Control/cmp.ll (+13-13)
- (modified) llvm/test/CodeGen/M68k/Control/long-setcc.ll (+2-2)
- (modified) llvm/test/CodeGen/M68k/Control/setcc.ll (+3-3)
- (modified) llvm/test/CodeGen/M68k/PR57660.ll (+1-1)
- (modified) llvm/test/CodeGen/M68k/gcc_except_table.ll (+1-1)
- (modified) llvm/test/CodeGen/M68k/link-unlnk.ll (+2-2)
- (modified) llvm/test/MC/Disassembler/M68k/data.txt (+6)
- (modified) llvm/test/MC/M68k/Data/Classes/MxMove_RI.s (+3)
``````````diff
diff --git a/llvm/lib/Target/M68k/M68kExpandPseudo.cpp b/llvm/lib/Target/M68k/M68kExpandPseudo.cpp
index 7fcc65beaa653b..c7fdd7d7c35023 100644
--- a/llvm/lib/Target/M68k/M68kExpandPseudo.cpp
+++ b/llvm/lib/Target/M68k/M68kExpandPseudo.cpp
@@ -80,6 +80,13 @@ bool M68kExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
default:
return false;
+ case M68k::MOVI8di:
+ return TII->ExpandMOVI(MIB, MVT::i8);
+ case M68k::MOVI16ri:
+ return TII->ExpandMOVI(MIB, MVT::i16);
+ case M68k::MOVI32ri:
+ return TII->ExpandMOVI(MIB, MVT::i32);
+
case M68k::MOVXd16d8:
return TII->ExpandMOVX_RR(MIB, MVT::i16, MVT::i8);
case M68k::MOVXd32d8:
diff --git a/llvm/lib/Target/M68k/M68kInstrData.td b/llvm/lib/Target/M68k/M68kInstrData.td
index fa7e7aa0ed4619..dc777a933e2786 100644
--- a/llvm/lib/Target/M68k/M68kInstrData.td
+++ b/llvm/lib/Target/M68k/M68kInstrData.td
@@ -19,7 +19,7 @@
///
/// Pseudo:
///
-/// MOVSX [x] MOVZX [x] MOVX [x]
+/// MOVI [x] MOVSX [x] MOVZX [x] MOVX [x]
///
/// Map:
///
@@ -165,11 +165,12 @@ foreach AM = MxMoveSupportedAMs in {
} // foreach AM
// R <- I
+// No pattern, as all immediate -> register moves are matched to the MOVI pseudo
class MxMove_RI<MxType TYPE, string DST_REG, MxMoveEncoding ENC,
MxImmOpBundle SRC = !cast<MxImmOpBundle>("MxOp"#TYPE.Size#"AddrMode_i"),
MxOpBundle DST = !cast<MxOpBundle>("MxOp"#TYPE.Size#"AddrMode_"#DST_REG)>
: MxMove<TYPE.Prefix, (outs DST.Op:$dst), (ins SRC.Op:$src),
- [(set TYPE.VT:$dst, SRC.ImmPat:$src)], ENC>;
+ [(null_frag)], ENC>;
foreach REG = ["r", "a", "d"] in {
foreach TYPE = !if(!eq(REG, "d"), [MxType8, MxType16, MxType32], [MxType16, MxType32]) in
@@ -242,6 +243,24 @@ def : Pat<(store MxType32.BPat :$src, MxType32.BPat :$dst),
def : Pat<(store MxType32.BPat :$src, MxType32.JPat :$dst),
(MOV32ji MxType32.JOp :$dst, MxType32.IOp :$src)>;
+//===----------------------------------------------------------------------===//
+// MOVEQ
+//===----------------------------------------------------------------------===//
+
+/// ------------+---------+---+-----------------------
+/// F E D C | B A 9 | 8 | 7 6 5 4 3 2 1 0
+/// ------------+---------+---+-----------------------
+/// 0 1 1 1 | REG | 0 | DATA
+/// ------------+---------+---+-----------------------
+
+// No pattern, as all immediate -> register moves are matched to the MOVI pseudo
+let Defs = [CCR] in
+def MOVQ : MxInst<(outs MxDRD32:$dst), (ins Mxi8imm:$imm),
+ "moveq\t$imm, $dst",
+ [(null_frag)]> {
+ let Inst = (descend 0b0111, (operand "$dst", 3), 0b0, (operand "$imm", 8));
+}
+
//===----------------------------------------------------------------------===//
// MOVEM
//
@@ -496,7 +515,23 @@ class MxPseudoMove_RR<MxType DST, MxType SRC, list<dag> PAT = []>
class MxPseudoMove_RM<MxType DST, MxOperand SRCOpd, list<dag> PAT = []>
: MxPseudo<(outs DST.ROp:$dst), (ins SRCOpd:$src), PAT>;
-}
+
+
+// These Pseudos handle loading immediates to registers.
+// They are expanded post-RA into either move or moveq instructions,
+// depending on size, destination register class, and immediate value.
+// This is done with pseudoinstructions in order to not constrain RA to
+// data registers if moveq matches.
+class MxPseudoMove_DI<MxType TYPE>
+ : MxPseudo<(outs TYPE.ROp:$dst), (ins TYPE.IOp:$src),
+ [(set TYPE.ROp:$dst, imm:$src)]>;
+
+// i8 imm -> reg can always be converted to moveq,
+// but we still emit a pseudo for consistency.
+def MOVI8di : MxPseudoMove_DI<MxType8d>;
+def MOVI16ri : MxPseudoMove_DI<MxType16r>;
+def MOVI32ri : MxPseudoMove_DI<MxType32r>;
+} // let Defs = [CCR]
/// This group of Pseudos is analogues to the real x86 extending moves, but
/// since M68k does not have those we need to emulate. These instructions
diff --git a/llvm/lib/Target/M68k/M68kInstrInfo.cpp b/llvm/lib/Target/M68k/M68kInstrInfo.cpp
index d56fef9e9029af..338db45782c961 100644
--- a/llvm/lib/Target/M68k/M68kInstrInfo.cpp
+++ b/llvm/lib/Target/M68k/M68kInstrInfo.cpp
@@ -346,6 +346,40 @@ void M68kInstrInfo::AddZExt(MachineBasicBlock &MBB,
BuildMI(MBB, I, DL, get(And), Reg).addReg(Reg).addImm(Mask);
}
+// Convert MOVI to MOVQ if the target is a data register and the immediate
+// fits in a sign-extended i8, otherwise emit a plain MOV.
+bool M68kInstrInfo::ExpandMOVI(MachineInstrBuilder &MIB, MVT MVTSize) const {
+ Register Reg = MIB->getOperand(0).getReg();
+ int64_t Imm = MIB->getOperand(1).getImm();
+ bool IsAddressReg = false;
+
+ const auto *DR32 = RI.getRegClass(M68k::DR32RegClassID);
+ const auto *AR32 = RI.getRegClass(M68k::AR32RegClassID);
+ const auto *AR16 = RI.getRegClass(M68k::AR16RegClassID);
+
+ if (AR16->contains(Reg) || AR32->contains(Reg))
+ IsAddressReg = true;
+
+ LLVM_DEBUG(dbgs() << "Expand " << *MIB.getInstr() << " to ");
+
+ if (MVTSize == MVT::i8 || (!IsAddressReg && Imm >= -128 && Imm <= 127)) {
+ LLVM_DEBUG(dbgs() << "MOVEQ\n");
+
+ // We need to assign to the full register to make IV happy
+ Register SReg =
+ MVTSize == MVT::i32 ? Reg : Register(RI.getMatchingMegaReg(Reg, DR32));
+ assert(SReg && "No viable MEGA register available");
+
+ MIB->setDesc(get(M68k::MOVQ));
+ MIB->getOperand(0).setReg(SReg);
+ } else {
+ LLVM_DEBUG(dbgs() << "MOVE\n");
+ MIB->setDesc(get(MVTSize == MVT::i16 ? M68k::MOV16ri : M68k::MOV32ri));
+ }
+
+ return true;
+}
+
bool M68kInstrInfo::ExpandMOVX_RR(MachineInstrBuilder &MIB, MVT MVTDst,
MVT MVTSrc) const {
unsigned Move = MVTDst == MVT::i16 ? M68k::MOV16rr : M68k::MOV32rr;
diff --git a/llvm/lib/Target/M68k/M68kInstrInfo.h b/llvm/lib/Target/M68k/M68kInstrInfo.h
index 577967f2fdfc97..d1e1e1cd99987b 100644
--- a/llvm/lib/Target/M68k/M68kInstrInfo.h
+++ b/llvm/lib/Target/M68k/M68kInstrInfo.h
@@ -302,6 +302,9 @@ class M68kInstrInfo : public M68kGenInstrInfo {
void AddZExt(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
DebugLoc DL, unsigned Reg, MVT From, MVT To) const;
+ /// Move immediate to register
+ bool ExpandMOVI(MachineInstrBuilder &MIB, MVT MVTSize) const;
+
/// Move across register classes without extension
bool ExpandMOVX_RR(MachineInstrBuilder &MIB, MVT MVTDst, MVT MVTSrc) const;
diff --git a/llvm/test/CodeGen/M68k/Arith/add-with-overflow.ll b/llvm/test/CodeGen/M68k/Arith/add-with-overflow.ll
index bd5e593edb33d8..70479b0b3ec65c 100644
--- a/llvm/test/CodeGen/M68k/Arith/add-with-overflow.ll
+++ b/llvm/test/CodeGen/M68k/Arith/add-with-overflow.ll
@@ -35,7 +35,7 @@ define fastcc i1 @test6(i32 %v1, i32 %v2, ptr %X) nounwind {
; CHECK-NEXT: ; %bb.1: ; %normal
; CHECK-NEXT: move.l #0, (%a0)
; CHECK-NEXT: .LBB1_2: ; %carry
-; CHECK-NEXT: move.b #0, %d0
+; CHECK-NEXT: moveq #0, %d0
; CHECK-NEXT: rts
entry:
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
diff --git a/llvm/test/CodeGen/M68k/Arith/add.ll b/llvm/test/CodeGen/M68k/Arith/add.ll
index 281751e3e183c7..a9eb0bb815b088 100644
--- a/llvm/test/CodeGen/M68k/Arith/add.ll
+++ b/llvm/test/CodeGen/M68k/Arith/add.ll
@@ -43,7 +43,7 @@ define fastcc void @test3(ptr inreg %a) nounwind {
; CHECK-NEXT: suba.l #4, %sp
; CHECK-NEXT: movem.l %d2, (0,%sp) ; 8-byte Folded Spill
; CHECK-NEXT: move.l (%a0), %d0
-; CHECK-NEXT: move.l #0, %d1
+; CHECK-NEXT: moveq #0, %d1
; CHECK-NEXT: move.l #-2147483648, %d2
; CHECK-NEXT: add.l (4,%a0), %d2
; CHECK-NEXT: addx.l %d0, %d1
@@ -64,7 +64,7 @@ define fastcc void @test4(ptr inreg %a) nounwind {
; CHECK-NEXT: suba.l #4, %sp
; CHECK-NEXT: movem.l %d2, (0,%sp) ; 8-byte Folded Spill
; CHECK-NEXT: move.l (%a0), %d0
-; CHECK-NEXT: move.l #0, %d1
+; CHECK-NEXT: moveq #0, %d1
; CHECK-NEXT: move.l #128, %d2
; CHECK-NEXT: add.l (4,%a0), %d2
; CHECK-NEXT: addx.l %d0, %d1
diff --git a/llvm/test/CodeGen/M68k/Arith/bitwise.ll b/llvm/test/CodeGen/M68k/Arith/bitwise.ll
index 70e4dd42bfb6de..74fc543a5fb856 100644
--- a/llvm/test/CodeGen/M68k/Arith/bitwise.ll
+++ b/llvm/test/CodeGen/M68k/Arith/bitwise.ll
@@ -242,7 +242,7 @@ define i64 @lshr64(i64 %a, i64 %b) nounwind {
; CHECK-NEXT: add.l #-32, %d1
; CHECK-NEXT: bmi .LBB18_1
; CHECK-NEXT: ; %bb.2:
-; CHECK-NEXT: move.l #0, %d0
+; CHECK-NEXT: moveq #0, %d0
; CHECK-NEXT: bra .LBB18_3
; CHECK-NEXT: .LBB18_1:
; CHECK-NEXT: move.l %d2, %d0
@@ -301,7 +301,7 @@ define i64 @ashr64(i64 %a, i64 %b) nounwind {
; CHECK-NEXT: add.l #-32, %d3
; CHECK-NEXT: bmi .LBB19_5
; CHECK-NEXT: ; %bb.4:
-; CHECK-NEXT: move.l #31, %d2
+; CHECK-NEXT: moveq #31, %d2
; CHECK-NEXT: .LBB19_5:
; CHECK-NEXT: asr.l %d2, %d0
; CHECK-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
@@ -322,7 +322,7 @@ define i64 @shl64(i64 %a, i64 %b) nounwind {
; CHECK-NEXT: add.l #-32, %d0
; CHECK-NEXT: bmi .LBB20_1
; CHECK-NEXT: ; %bb.2:
-; CHECK-NEXT: move.l #0, %d1
+; CHECK-NEXT: moveq #0, %d1
; CHECK-NEXT: bra .LBB20_3
; CHECK-NEXT: .LBB20_1:
; CHECK-NEXT: move.l %d2, %d1
diff --git a/llvm/test/CodeGen/M68k/Arith/divide-by-constant.ll b/llvm/test/CodeGen/M68k/Arith/divide-by-constant.ll
index 834dfe1c26f08f..fcc8dd3e7662e1 100644
--- a/llvm/test/CodeGen/M68k/Arith/divide-by-constant.ll
+++ b/llvm/test/CodeGen/M68k/Arith/divide-by-constant.ll
@@ -40,7 +40,7 @@ define zeroext i8 @test3(i8 zeroext %x, i8 zeroext %c) {
; CHECK-NEXT: move.b (11,%sp), %d0
; CHECK-NEXT: and.l #255, %d0
; CHECK-NEXT: muls #171, %d0
-; CHECK-NEXT: move.w #9, %d1
+; CHECK-NEXT: moveq #9, %d1
; CHECK-NEXT: lsr.w %d1, %d0
; CHECK-NEXT: and.l #65535, %d0
; CHECK-NEXT: rts
@@ -58,7 +58,7 @@ define signext i16 @test4(i16 signext %x) nounwind {
; CHECK-NEXT: muls #1986, %d0
; CHECK-NEXT: asr.l #8, %d0
; CHECK-NEXT: asr.l #8, %d0
-; CHECK-NEXT: move.w #15, %d1
+; CHECK-NEXT: moveq #15, %d1
; CHECK-NEXT: move.w %d0, %d2
; CHECK-NEXT: lsr.w %d1, %d2
; CHECK-NEXT: add.w %d2, %d0
@@ -94,7 +94,7 @@ define signext i16 @test6(i16 signext %x) nounwind {
; CHECK-NEXT: muls #26215, %d0
; CHECK-NEXT: asr.l #8, %d0
; CHECK-NEXT: asr.l #8, %d0
-; CHECK-NEXT: move.w #15, %d1
+; CHECK-NEXT: moveq #15, %d1
; CHECK-NEXT: move.w %d0, %d2
; CHECK-NEXT: lsr.w %d1, %d2
; CHECK-NEXT: asr.w #2, %d0
@@ -128,7 +128,7 @@ define i8 @test8(i8 %x) nounwind {
; CHECK-NEXT: lsr.b #1, %d0
; CHECK-NEXT: and.l #255, %d0
; CHECK-NEXT: muls #211, %d0
-; CHECK-NEXT: move.w #13, %d1
+; CHECK-NEXT: moveq #13, %d1
; CHECK-NEXT: lsr.w %d1, %d0
; CHECK-NEXT: ; kill: def $bd0 killed $bd0 killed $d0
; CHECK-NEXT: rts
@@ -143,7 +143,7 @@ define i8 @test9(i8 %x) nounwind {
; CHECK-NEXT: lsr.b #2, %d0
; CHECK-NEXT: and.l #255, %d0
; CHECK-NEXT: muls #71, %d0
-; CHECK-NEXT: move.w #11, %d1
+; CHECK-NEXT: moveq #11, %d1
; CHECK-NEXT: lsr.w %d1, %d0
; CHECK-NEXT: ; kill: def $bd0 killed $bd0 killed $d0
; CHECK-NEXT: rts
@@ -156,11 +156,11 @@ define i32 @testsize1(i32 %x) minsize nounwind {
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: suba.l #4, %sp
; CHECK-NEXT: movem.l %d2, (0,%sp) ; 8-byte Folded Spill
-; CHECK-NEXT: move.l #31, %d1
+; CHECK-NEXT: moveq #31, %d1
; CHECK-NEXT: move.l (8,%sp), %d0
; CHECK-NEXT: move.l %d0, %d2
; CHECK-NEXT: asr.l %d1, %d2
-; CHECK-NEXT: move.l #27, %d1
+; CHECK-NEXT: moveq #27, %d1
; CHECK-NEXT: lsr.l %d1, %d2
; CHECK-NEXT: add.l %d2, %d0
; CHECK-NEXT: asr.l #5, %d0
diff --git a/llvm/test/CodeGen/M68k/Arith/imul.ll b/llvm/test/CodeGen/M68k/Arith/imul.ll
index f53568395c29b2..a1846e4d51bd2e 100644
--- a/llvm/test/CodeGen/M68k/Arith/imul.ll
+++ b/llvm/test/CodeGen/M68k/Arith/imul.ll
@@ -19,7 +19,7 @@ define i64 @mul4_64(i64 %A) {
; CHECK-NEXT: suba.l #4, %sp
; CHECK-NEXT: .cfi_def_cfa_offset -8
; CHECK-NEXT: movem.l %d2, (0,%sp) ; 8-byte Folded Spill
-; CHECK-NEXT: move.l #30, %d0
+; CHECK-NEXT: moveq #30, %d0
; CHECK-NEXT: move.l (12,%sp), %d1
; CHECK-NEXT: move.l %d1, %d2
; CHECK-NEXT: lsr.l %d0, %d2
@@ -38,7 +38,7 @@ define i32 @mul4096_32(i32 %A) {
; CHECK-LABEL: mul4096_32:
; CHECK: .cfi_startproc
; CHECK-NEXT: ; %bb.0:
-; CHECK-NEXT: move.l #12, %d1
+; CHECK-NEXT: moveq #12, %d1
; CHECK-NEXT: move.l (4,%sp), %d0
; CHECK-NEXT: lsl.l %d1, %d0
; CHECK-NEXT: rts
@@ -53,11 +53,11 @@ define i64 @mul4096_64(i64 %A) {
; CHECK-NEXT: suba.l #8, %sp
; CHECK-NEXT: .cfi_def_cfa_offset -12
; CHECK-NEXT: movem.l %d2-%d3, (0,%sp) ; 12-byte Folded Spill
-; CHECK-NEXT: move.l #20, %d0
+; CHECK-NEXT: moveq #20, %d0
; CHECK-NEXT: move.l (16,%sp), %d1
; CHECK-NEXT: move.l %d1, %d2
; CHECK-NEXT: lsr.l %d0, %d2
-; CHECK-NEXT: move.l #12, %d3
+; CHECK-NEXT: moveq #12, %d3
; CHECK-NEXT: move.l (12,%sp), %d0
; CHECK-NEXT: lsl.l %d3, %d0
; CHECK-NEXT: or.l %d2, %d0
@@ -73,7 +73,7 @@ define i32 @mulmin4096_32(i32 %A) {
; CHECK-LABEL: mulmin4096_32:
; CHECK: .cfi_startproc
; CHECK-NEXT: ; %bb.0:
-; CHECK-NEXT: move.l #12, %d1
+; CHECK-NEXT: moveq #12, %d1
; CHECK-NEXT: move.l (4,%sp), %d0
; CHECK-NEXT: lsl.l %d1, %d0
; CHECK-NEXT: neg.l %d0
@@ -89,11 +89,11 @@ define i64 @mulmin4096_64(i64 %A) {
; CHECK-NEXT: suba.l #8, %sp
; CHECK-NEXT: .cfi_def_cfa_offset -12
; CHECK-NEXT: movem.l %d2-%d3, (0,%sp) ; 12-byte Folded Spill
-; CHECK-NEXT: move.l #20, %d0
+; CHECK-NEXT: moveq #20, %d0
; CHECK-NEXT: move.l (16,%sp), %d1
; CHECK-NEXT: move.l %d1, %d2
; CHECK-NEXT: lsr.l %d0, %d2
-; CHECK-NEXT: move.l #12, %d3
+; CHECK-NEXT: moveq #12, %d3
; CHECK-NEXT: move.l (12,%sp), %d0
; CHECK-NEXT: lsl.l %d3, %d0
; CHECK-NEXT: or.l %d2, %d0
@@ -258,7 +258,7 @@ define i32 @mul0_32(i32 %A) {
; CHECK-LABEL: mul0_32:
; CHECK: .cfi_startproc
; CHECK-NEXT: ; %bb.0:
-; CHECK-NEXT: move.l #0, %d0
+; CHECK-NEXT: moveq #0, %d0
; CHECK-NEXT: rts
%mul = mul i32 %A, 0
ret i32 %mul
diff --git a/llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll b/llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll
index 5bd4d5d48bc859..10a797f1344141 100644
--- a/llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll
+++ b/llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll
@@ -24,7 +24,7 @@ entry:
define zeroext i8 @smul_i8_no_ovf(i8 signext %a, i8 signext %b) nounwind ssp {
; CHECK-LABEL: smul_i8_no_ovf:
; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: move.l #42, %d0
+; CHECK-NEXT: moveq #42, %d0
; CHECK-NEXT: rts
entry:
%smul = tail call { i8, i1 } @llvm.smul.with.overflow.i8(i8 %a, i8 %b)
@@ -70,7 +70,7 @@ define fastcc i1 @test1(i32 %v1, i32 %v2) nounwind {
; CHECK-NEXT: lea (no,%pc), %a0
; CHECK-NEXT: move.l %a0, (%sp)
; CHECK-NEXT: jsr printf at PLT
-; CHECK-NEXT: move.b #0, %d0
+; CHECK-NEXT: moveq #0, %d0
; CHECK-NEXT: adda.l #12, %sp
; CHECK-NEXT: rts
; CHECK-NEXT: .LBB3_1: ; %normal
@@ -78,7 +78,7 @@ define fastcc i1 @test1(i32 %v1, i32 %v2) nounwind {
; CHECK-NEXT: lea (ok,%pc), %a0
; CHECK-NEXT: move.l %a0, (%sp)
; CHECK-NEXT: jsr printf at PLT
-; CHECK-NEXT: move.b #1, %d0
+; CHECK-NEXT: moveq #1, %d0
; CHECK-NEXT: adda.l #12, %sp
; CHECK-NEXT: rts
entry:
@@ -108,7 +108,7 @@ define fastcc i1 @test2(i32 %v1, i32 %v2) nounwind {
; CHECK-NEXT: lea (no,%pc), %a0
; CHECK-NEXT: move.l %a0, (%sp)
; CHECK-NEXT: jsr printf at PLT
-; CHECK-NEXT: move.b #0, %d0
+; CHECK-NEXT: moveq #0, %d0
; CHECK-NEXT: adda.l #12, %sp
; CHECK-NEXT: rts
; CHECK-NEXT: .LBB4_2: ; %normal
@@ -116,7 +116,7 @@ define fastcc i1 @test2(i32 %v1, i32 %v2) nounwind {
; CHECK-NEXT: lea (ok,%pc), %a0
; CHECK-NEXT: move.l %a0, (%sp)
; CHECK-NEXT: jsr printf at PLT
-; CHECK-NEXT: move.b #1, %d0
+; CHECK-NEXT: moveq #1, %d0
; CHECK-NEXT: adda.l #12, %sp
; CHECK-NEXT: rts
entry:
@@ -155,7 +155,7 @@ define i32 @test4(i32 %a, i32 %b) nounwind readnone {
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: move.l (8,%sp), %d0
; CHECK-NEXT: add.l (4,%sp), %d0
-; CHECK-NEXT: move.l #4, %d1
+; CHECK-NEXT: moveq #4, %d1
; CHECK-NEXT: muls.l %d1, %d0
; CHECK-NEXT: rts
entry:
diff --git a/llvm/test/CodeGen/M68k/Arith/sub-with-overflow.ll b/llvm/test/CodeGen/M68k/Arith/sub-with-overflow.ll
index 8d47c7ebf7e56f..be3223156986e6 100644
--- a/llvm/test/CodeGen/M68k/Arith/sub-with-overflow.ll
+++ b/llvm/test/CodeGen/M68k/Arith/sub-with-overflow.ll
@@ -19,7 +19,7 @@ define i1 @func1(i32 %v1, i32 %v2) nounwind {
; CHECK-NEXT: lea (no,%pc), %a0
; CHECK-NEXT: move.l %a0, (%sp)
; CHECK-NEXT: jsr printf at PLT
-; CHECK-NEXT: move.b #0, %d0
+; CHECK-NEXT: moveq #0, %d0
; CHECK-NEXT: adda.l #12, %sp
; CHECK-NEXT: rts
; CHECK-NEXT: .LBB0_1: ; %normal
@@ -27,7 +27,7 @@ define i1 @func1(i32 %v1, i32 %v2) nounwind {
; CHECK-NEXT: lea (ok,%pc), %a0
; CHECK-NEXT: move.l %a0, (%sp)
; CHECK-NEXT: jsr printf at PLT
-; CHECK-NEXT: move.b #1, %d0
+; CHECK-NEXT: moveq #1, %d0
; CHECK-NEXT: adda.l #12, %sp
; CHECK-NEXT: rts
entry:
@@ -56,7 +56,7 @@ define i1 @func2(i32 %v1, i32 %v2) nounwind {
; CHECK-NEXT: lea (no,%pc), %a0
; CHECK-NEXT: move.l %a0, (%sp)
; CHECK-NEXT: jsr printf at PLT
-; CHECK-NEXT: move.b #0, %d0
+; CHECK-NEXT: moveq #0, %d0
; CHECK-NEXT: adda.l #12, %sp
; CHECK-NEXT: rts
; CHECK-NEXT: .LBB1_1: ; %normal
@@ -64,7 +64,7 @@ define i1 @func2(i32 %v1, i32 %v2) nounwind {
; CHECK-NEXT: lea (ok,%pc), %a0
; CHECK-NEXT: move.l %a0, (%sp)
; CHECK-NEXT: jsr printf at PLT
-; CHECK-NEXT: move.b #1, %d0
+; CHECK-NEXT: moveq #1, %d0
; CHECK-NEXT: adda.l #12, %sp
; CHECK-NEXT: rts
entry:
@@ -85,7 +85,7 @@ carry:
define i1 @func3(i32 %x) nounwind {
; CHECK-LABEL: func3:
; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: move.l #-1, %d0
+; CHECK-NEXT: moveq #-1, %d0
; CHECK-NEXT: add.l (4,%sp), %d0
; CHECK-NEXT: svs %d0
; CHECK-NEXT: rts
diff --git a/llvm/test/CodeGen/M68k/Arith/sub.ll b/llvm/test/CodeGen/M68k/Arith/sub.ll
index fff3601000dfa8..16d0498b3dbbc6 100644
--- a/llvm/test/CodeGen/M68k/Arith/sub.ll
+++ b/llvm/test/CodeGen/M68k/Arith/sub.ll
@@ -7,7 +7,7 @@ define i32 @test1(i32 %x) {
; CHECK-NEXT: ; %bb.0:
; CHECK-NEXT: move.l (4,%sp), %d1
; CHECK-NEXT: eori.l #31, %d1
-; CHECK-NEXT: move.l #32, %d0
+; CHECK-NEXT: moveq #32, %d0
; CHECK-NEXT: sub.l %d1, %d0
; CHECK-NEXT: rts
%xor = xor i32 %x, 31
diff --git a/llvm/test/CodeGen/M68k/Arith/umul-with-overflow.ll b/llvm/test/CodeGen/M68k/Arith/umul-with-overflow.ll
index fd128a3e52bd3e..3314e65399c431 100644
--- a/llvm/test/CodeGen/M68k/Arith/umul-with-overflow.ll
+++ b/llvm/test/CodeGen/M68k/Arith/umul-with-overflow.ll
@@ -24,7 +24,7 @@ entry:
define zeroext i8 @umul_i8_no_ovf(i8 signext %a, i8 signext %b) nounwind ssp {
; CHECK-LABEL: umul_i8_no_ovf:
; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: move.l #42, %d0
+; CHECK-NEXT: moveq #42, %d0
; CHECK-NEXT: rts
entry:
%umul = tail call { i8, i1 } @llvm.umul.with.overflow.i8(i8 %a, i8 %b)
@@ -59,7 +59,7 @@ declare {i32, i1} @llvm.umul.with.overflow.i32(i32 %a, i32 %b)
define i1 @a(i32 %x) nounwind {
; CHECK-LABEL: a:
; CHECK: ; %bb.0:
-; CHECK-NEXT: move.l #3, %d0
+; CHECK-NEXT: moveq #3, %d0
; CHECK-NEXT: move.l (4,%sp), %d1
; CHECK-NEXT: mulu.l %d0, %d1
; CHECK-NEXT: svs %d0
@@ -90,7 +90,7 @@ define i32 @test3(i32 %a, i32 %b) nounwind readnone {
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: move.l (8,%sp), %d0
; CHECK-NEXT: add.l (4,%sp), %d0
-; CHECK-NEXT: move.l #4, %d1
+; CHECK-NEXT: moveq #4, %d1
; CHECK-NEXT: mulu.l %d1, %d0
; CHECK-NEXT: rts
entry:
diff --git a/llvm/test/CodeGen/M68k/CConv/c-call.ll b/llvm/test/CodeGen/M68k/CConv/c-call.ll
index a9638eec6a3138..badd4e31f37d18 100644
--- a/llvm/test/CodeGen/M68k/CConv/c-call.ll
+++ b/llvm/test/CodeGen/M68k/CConv/c-call.ll
@@ -14,7 +14,7 @@ define i32 @test1() nounwind {
; CHECK-NEXT: move.l #2, (4,%sp)
; CHECK-NEXT: move.l #1, (%sp)
; CHECK-NEXT: jsr (test1_callee at PLT,%pc)
-; CHECK-NEXT: move.l #0, %d0
+; CHECK-NEXT: moveq #0, %d0
; CHECK-NEXT: adda.l #20, %sp
; CHECK-NEXT: rts
entry:
@@ -...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/88542
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