[llvm] [AArch64][SVE2] Generate SVE2 BSL instruction in LLVM for add/sub. (PR #88413)

[David Sherwood via llvm-commits]

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+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s | FileCheck %s
+
+target triple = "aarch64"
+
+; Check that an expanded vbsl(vneg(pre_cond), left, right) lowers to a VBSL
+; during ISEL.
+;
+; Subtly different from a plain vector bit select: operand representing the
+; condition has been negated (-v, not to be confused with bitwise_not(v)).
+
+; Each vbsl_neg_cond_xxxx tests one of the 16 permutations of the operands.
+
+define <vscale x 4 x i32> @vbsl_neg_cond_0000(<vscale x 4 x i32> %pre_cond, <vscale x 4 x i32> %left, <vscale x 4 x i32> %right) #0 {
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david-arm wrote:

Given all the tests in this file are repeats of those in neon-bitselect.ll I wonder if it's necessary to test all permutations? The NEON tests cover all cases and the code is the same for both NEON and SVE so perhaps we only need `@vbsl_neg_cond_0000` as a test?

Also, it's probably worth adding at least one test for the other DAG combine - (or (and a b) (and (not a) c)) => (bsl a b c). I think there are some NEON examples of this in neon-bitwise-instructions.ll

https://github.com/llvm/llvm-project/pull/88413