[llvm] [InstCombine] Support division of numbers that can be converted to a shift (PR #88220)

[via llvm-commits]

https://github.com/AtariDreams updated https://github.com/llvm/llvm-project/pull/88220

>From dcd1e090fc5c4674c926d15f2331c5bc9c7dbbc1 Mon Sep 17 00:00:00 2001
From: Rose <gfunni234 at gmail.com>
Date: Tue, 9 Apr 2024 21:04:26 -0400
Subject: [PATCH 1/2] Pre-commit tests (NFC)

---
 llvm/test/Transforms/InstCombine/div.ll | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/llvm/test/Transforms/InstCombine/div.ll b/llvm/test/Transforms/InstCombine/div.ll
index e8a25ff44d0296..a44731daf81ef7 100644
--- a/llvm/test/Transforms/InstCombine/div.ll
+++ b/llvm/test/Transforms/InstCombine/div.ll
@@ -1638,6 +1638,30 @@ define i32 @sdiv_mul_sub_nsw(i32 %x, i32 %y) {
   ret i32 %d
 }
 
+  define i32 @mul_by_150_udiv_by_100 (i32 %0) {
+; CHECK-LABEL: @mul_by_150_udiv_by_100(
+; CHECK-NEXT:    [[TMP2:%.*]] = mul nuw i32 [[TMP0:%.*]], 150
+; CHECK-NEXT:    [[TMP3:%.*]] = udiv i32 [[TMP2]], 100
+; CHECK-NEXT:    ret i32 [[TMP3]]
+;
+  %2 = mul nuw i32 %0, 150
+  %3 = udiv i32 %2, 100
+  ret i32 %3
+}
+
+;negative case, no nuw
+
+  define i32 @mul_by_150_sdiv_by_100 (i32 %0) {
+; CHECK-LABEL: @mul_by_150_sdiv_by_100(
+; CHECK-NEXT:    [[TMP2:%.*]] = mul nsw i32 [[TMP0:%.*]], 150
+; CHECK-NEXT:    [[TMP3:%.*]] = sdiv i32 [[TMP2]], 100
+; CHECK-NEXT:    ret i32 [[TMP3]]
+;
+  %2 = mul nsw i32 %0, 150
+  %3 = sdiv i32 %2, 100
+  ret i32 %3
+}
+
 define i32 @sdiv_mul_nsw_sub_nsw(i32 %x, i32 %y) {
 ; CHECK-LABEL: @sdiv_mul_nsw_sub_nsw(
 ; CHECK-NEXT:    ret i32 -1

>From 530f10d42091124b234f2776e68a68591f848590 Mon Sep 17 00:00:00 2001
From: Rose <gfunni234 at gmail.com>
Date: Tue, 9 Apr 2024 20:32:12 -0400
Subject: [PATCH 2/2] [InstCombine] Support division of numbers that can be
 converted to a shift

---
 .../InstCombine/InstCombineMulDivRem.cpp      | 26 +++++++++++++++++++
 llvm/test/Transforms/InstCombine/div.ll       |  4 +--
 2 files changed, 28 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp b/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
index 8c698e52b5a0e6..9e062aebc4a6e1 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
@@ -1149,6 +1149,32 @@ Instruction *InstCombinerImpl::commonIDivTransforms(BinaryOperator &I) {
         Mul->setHasNoSignedWrap(OBO->hasNoSignedWrap());
         return Mul;
       }
+
+      // If we can reduce these functions so they can factor out to a shift or
+      // something similar Why not? i.e Reduce (X * 150/100) -> (X * 3) >> 1
+
+      // (X * C1)/C2 -> X * (C1/C3) >> log2(C2/C3) where C3 divides exactly C1
+      // and C2 and C2/C3 is a power of 2.
+      // This WILL require NUW, and if it is sdiv then it also requires NSW
+      APInt C3 = APIntOps::GreatestCommonDivisor(*C1, *C2);
+      APInt Q(C2->getBitWidth(), /*val=*/0ULL, IsSigned);
+
+      // Returns false if division by 0
+      if (isMultiple(*C2, C3, Q, IsSigned) && Q.isPowerOf2()) {
+
+        auto *OBO = cast<OverflowingBinaryOperator>(Op0);
+        if (OBO->hasNoUnsignedWrap() && (!IsSigned || OBO->hasNoSignedWrap())) {
+
+          APInt C4 = IsSigned ? C1->sdiv(C3) : C1->udiv(C3);
+          auto *Mul =
+              Builder.CreateMul(X, ConstantInt::get(Ty, C4), "", true, true);
+
+          Instruction *Shift = BinaryOperator::CreateLShr(
+              Mul, ConstantInt::get(Ty, Q.logBase2()));
+          Shift->setIsExact(I.isExact());
+          return Shift;
+        }
+      }
     }
 
     if ((IsSigned && match(Op0, m_NSWShl(m_Value(X), m_APInt(C1))) &&
diff --git a/llvm/test/Transforms/InstCombine/div.ll b/llvm/test/Transforms/InstCombine/div.ll
index a44731daf81ef7..0b8a9ba8009089 100644
--- a/llvm/test/Transforms/InstCombine/div.ll
+++ b/llvm/test/Transforms/InstCombine/div.ll
@@ -1640,8 +1640,8 @@ define i32 @sdiv_mul_sub_nsw(i32 %x, i32 %y) {
 
   define i32 @mul_by_150_udiv_by_100 (i32 %0) {
 ; CHECK-LABEL: @mul_by_150_udiv_by_100(
-; CHECK-NEXT:    [[TMP2:%.*]] = mul nuw i32 [[TMP0:%.*]], 150
-; CHECK-NEXT:    [[TMP3:%.*]] = udiv i32 [[TMP2]], 100
+; CHECK-NEXT:    [[TMP2:%.*]] = mul nuw nsw i32 [[TMP0:%.*]], 3
+; CHECK-NEXT:    [[TMP3:%.*]] = lshr i32 [[TMP2]], 1
 ; CHECK-NEXT:    ret i32 [[TMP3]]
 ;
   %2 = mul nuw i32 %0, 150