[llvm] [AArch64] Remove copy in SVE/SME predicate spill and fill (PR #81716)

[Sam Tebbs via llvm-commits]

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@@ -6714,7 +6750,7 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
   case Match_InvalidSVEVectorListStrided4x16:
   case Match_InvalidSVEVectorListStrided4x32:
   case Match_InvalidSVEVectorListStrided4x64:
-  case Match_InvalidSVEPNRasPPRPredicateBReg:
+  case Match_InvalidSVEPPRorPNRBReg:
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SamTebbs33 wrote:

If we keep it here we retain the same error messages as the older reg class. I can move it up but it will require updating quite a few tests.

https://github.com/llvm/llvm-project/pull/81716