[llvm] [AMDGPU] Add type-generic llvm.amdgcn.readfirstlane2 intrinsic (PR #87334)
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 2 08:57:57 PDT 2024
================
@@ -1,71 +1,176 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope %s
-declare i32 @llvm.amdgcn.readfirstlane(i32) #0
-
-; CHECK-LABEL: {{^}}test_readfirstlane:
-; CHECK: v_readfirstlane_b32 s{{[0-9]+}}, v2
-define void @test_readfirstlane(ptr addrspace(1) %out, i32 %src) #1 {
+define void @test_readfirstlane(ptr addrspace(1) %out, i32 %src) {
+; CHECK-LABEL: test_readfirstlane:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_readfirstlane_b32 s4, v2
+; CHECK-NEXT: v_mov_b32_e32 v2, s4
+; CHECK-NEXT: flat_store_dword v[0:1], v2
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%readfirstlane = call i32 @llvm.amdgcn.readfirstlane(i32 %src)
store i32 %readfirstlane, ptr addrspace(1) %out, align 4
ret void
}
-; CHECK-LABEL: {{^}}test_readfirstlane_imm:
-; CHECK: s_mov_b32 [[SGPR_VAL:s[0-9]]], 32
-; CHECK-NOT: [[SGPR_VAL]]
-; CHECK: ; use [[SGPR_VAL]]
-define amdgpu_kernel void @test_readfirstlane_imm(ptr addrspace(1) %out) #1 {
+define amdgpu_kernel void @test_readfirstlane_imm(ptr addrspace(1) %out) {
+; CHECK-LABEL: test_readfirstlane_imm:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_mov_b32 s0, 32
+; CHECK-NEXT: ;;#ASMSTART
+; CHECK-NEXT: ; use s0
+; CHECK-NEXT: ;;#ASMEND
+; CHECK-NEXT: s_endpgm
%readfirstlane = call i32 @llvm.amdgcn.readfirstlane(i32 32)
call void asm sideeffect "; use $0", "s"(i32 %readfirstlane)
ret void
}
-; CHECK-LABEL: {{^}}test_readfirstlane_imm_fold:
-; CHECK: v_mov_b32_e32 [[VVAL:v[0-9]]], 32
-; CHECK-NOT: [[VVAL]]
-; CHECK: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[VVAL]]
-define amdgpu_kernel void @test_readfirstlane_imm_fold(ptr addrspace(1) %out) #1 {
+define amdgpu_kernel void @test_readfirstlane_imm_fold(ptr addrspace(1) %out) {
+; CHECK-LABEL: test_readfirstlane_imm_fold:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
+; CHECK-NEXT: v_mov_b32_e32 v2, 32
+; CHECK-NEXT: s_waitcnt lgkmcnt(0)
+; CHECK-NEXT: v_mov_b32_e32 v0, s0
+; CHECK-NEXT: v_mov_b32_e32 v1, s1
+; CHECK-NEXT: flat_store_dword v[0:1], v2
+; CHECK-NEXT: s_endpgm
%readfirstlane = call i32 @llvm.amdgcn.readfirstlane(i32 32)
store i32 %readfirstlane, ptr addrspace(1) %out, align 4
ret void
}
-; CHECK-LABEL: {{^}}test_readfirstlane_m0:
-; CHECK: s_mov_b32 m0, -1
-; CHECK: v_mov_b32_e32 [[VVAL:v[0-9]]], m0
-; CHECK: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[VVAL]]
-define amdgpu_kernel void @test_readfirstlane_m0(ptr addrspace(1) %out) #1 {
+define amdgpu_kernel void @test_readfirstlane_m0(ptr addrspace(1) %out) {
+; CHECK-LABEL: test_readfirstlane_m0:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
+; CHECK-NEXT: ;;#ASMSTART
+; CHECK-NEXT: s_mov_b32 m0, -1
+; CHECK-NEXT: ;;#ASMEND
+; CHECK-NEXT: v_mov_b32_e32 v2, m0
+; CHECK-NEXT: s_waitcnt lgkmcnt(0)
+; CHECK-NEXT: v_mov_b32_e32 v0, s0
+; CHECK-NEXT: v_mov_b32_e32 v1, s1
+; CHECK-NEXT: flat_store_dword v[0:1], v2
+; CHECK-NEXT: s_endpgm
%m0 = call i32 asm "s_mov_b32 m0, -1", "={m0}"()
%readfirstlane = call i32 @llvm.amdgcn.readfirstlane(i32 %m0)
store i32 %readfirstlane, ptr addrspace(1) %out, align 4
ret void
}
-; CHECK-LABEL: {{^}}test_readfirstlane_copy_from_sgpr:
-; CHECK: ;;#ASMSTART
-; CHECK-NEXT: s_mov_b32 [[SGPR:s[0-9]+]]
-; CHECK: ;;#ASMEND
-; CHECK-NOT: [[SGPR]]
-; CHECK-NOT: readfirstlane
-; CHECK: v_mov_b32_e32 [[VCOPY:v[0-9]+]], [[SGPR]]
-; CHECK: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[VCOPY]]
-define amdgpu_kernel void @test_readfirstlane_copy_from_sgpr(ptr addrspace(1) %out) #1 {
+define amdgpu_kernel void @test_readfirstlane_copy_from_sgpr(ptr addrspace(1) %out) {
+; CHECK-LABEL: test_readfirstlane_copy_from_sgpr:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
+; CHECK-NEXT: ;;#ASMSTART
+; CHECK-NEXT: s_mov_b32 s2, 0
+; CHECK-NEXT: ;;#ASMEND
+; CHECK-NEXT: v_mov_b32_e32 v2, s2
+; CHECK-NEXT: s_waitcnt lgkmcnt(0)
+; CHECK-NEXT: v_mov_b32_e32 v0, s0
+; CHECK-NEXT: v_mov_b32_e32 v1, s1
+; CHECK-NEXT: flat_store_dword v[0:1], v2
+; CHECK-NEXT: s_endpgm
%sgpr = call i32 asm "s_mov_b32 $0, 0", "=s"()
%readfirstlane = call i32 @llvm.amdgcn.readfirstlane(i32 %sgpr)
store i32 %readfirstlane, ptr addrspace(1) %out, align 4
ret void
}
-; Make sure this doesn't crash.
-; CHECK-LABEL: {{^}}test_readfirstlane_fi:
-; CHECK: s_mov_b32 [[FIVAL:s[0-9]]], 0
-define amdgpu_kernel void @test_readfirstlane_fi(ptr addrspace(1) %out) #1 {
+define amdgpu_kernel void @test_readfirstlane_fi(ptr addrspace(1) %out) {
+; CHECK-LABEL: test_readfirstlane_fi:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_add_u32 s0, s0, s9
+; CHECK-NEXT: s_addc_u32 s1, s1, 0
+; CHECK-NEXT: s_mov_b32 s4, 0
+; CHECK-NEXT: ;;#ASMSTART
+; CHECK-NEXT: ; use s4
+; CHECK-NEXT: ;;#ASMEND
+; CHECK-NEXT: s_endpgm
%alloca = alloca i32, addrspace(5)
%int = ptrtoint ptr addrspace(5) %alloca to i32
%readfirstlane = call i32 @llvm.amdgcn.readfirstlane(i32 %int)
call void asm sideeffect "; use $0", "s"(i32 %readfirstlane)
ret void
}
-attributes #0 = { nounwind readnone convergent }
-attributes #1 = { nounwind }
+define void @test_readfirstlane2_i32(ptr addrspace(1) %out, i32 %src) {
+; CHECK-LABEL: test_readfirstlane2_i32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_readfirstlane_b32 s4, v2
+; CHECK-NEXT: ;;#ASMSTART
+; CHECK-NEXT: ; use s4
+; CHECK-NEXT: ;;#ASMEND
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %x = call i32 @llvm.amdgcn.readfirstlane2.i32(i32 %src)
+ call void asm sideeffect "; use $0", "s"(i32 %x)
+ ret void
+}
+
+define void @test_readfirstlane2_i64(ptr addrspace(1) %out, i64 %src) {
+; CHECK-LABEL: test_readfirstlane2_i64:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_readfirstlane_b32 s5, v3
+; CHECK-NEXT: v_readfirstlane_b32 s4, v2
+; CHECK-NEXT: ;;#ASMSTART
+; CHECK-NEXT: ; use s[4:5]
+; CHECK-NEXT: ;;#ASMEND
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %x = call i64 @llvm.amdgcn.readfirstlane2.i64(i64 %src)
+ call void asm sideeffect "; use $0", "s"(i64 %x)
+ ret void
+}
+
+define void @test_readfirstlane2_v7i32(ptr addrspace(1) %out, <7 x i32> %src) {
+; CHECK-LABEL: test_readfirstlane2_v7i32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_readfirstlane_b32 s10, v8
+; CHECK-NEXT: v_readfirstlane_b32 s9, v7
+; CHECK-NEXT: v_readfirstlane_b32 s8, v6
+; CHECK-NEXT: v_readfirstlane_b32 s7, v5
+; CHECK-NEXT: v_readfirstlane_b32 s6, v4
+; CHECK-NEXT: v_readfirstlane_b32 s5, v3
+; CHECK-NEXT: v_readfirstlane_b32 s4, v2
+; CHECK-NEXT: ;;#ASMSTART
+; CHECK-NEXT: ; use s[4:10]
+; CHECK-NEXT: ;;#ASMEND
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %x = call <7 x i32> @llvm.amdgcn.readfirstlane2.v7i32(<7 x i32> %src)
+ call void asm sideeffect "; use $0", "s"(<7 x i32> %x)
+ ret void
+}
+
+define void @test_readfirstlane2_f16(ptr addrspace(1) %out, half %src) {
+; CHECK-LABEL: test_readfirstlane2_f16:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_readfirstlane_b32 s4, v2
+; CHECK-NEXT: ;;#ASMSTART
+; CHECK-NEXT: ; use s4
+; CHECK-NEXT: ;;#ASMEND
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %x = call half @llvm.amdgcn.readfirstlane2.f16(half %src)
+ call void asm sideeffect "; use $0", "s"(half %x)
+ ret void
+}
+
+define void @test_readfirstlane2_float(ptr addrspace(1) %out, float %src) {
+; CHECK-LABEL: test_readfirstlane2_float:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_readfirstlane_b32 s4, v2
+; CHECK-NEXT: ;;#ASMSTART
+; CHECK-NEXT: ; use s4
+; CHECK-NEXT: ;;#ASMEND
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %x = call float @llvm.amdgcn.readfirstlane2.f32(float %src)
+ call void asm sideeffect "; use $0", "s"(float %x)
+ ret void
+}
----------------
jayfoad wrote:
What is float2? Done the others.
https://github.com/llvm/llvm-project/pull/87334
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