[llvm] [X86][MC] Support enc/dec for SETZUCC and promoted SETCC. (PR #86473)

Freddy Ye via llvm-commits llvm-commits at lists.llvm.org
Mon Apr 1 22:15:25 PDT 2024


https://github.com/FreddyLeaf updated https://github.com/llvm/llvm-project/pull/86473

>From a57cc0bffc20c1e517fb1a927d241d21a43e7dd8 Mon Sep 17 00:00:00 2001
From: Freddy Ye <freddy.ye at intel.com>
Date: Tue, 19 Mar 2024 15:01:22 +0800
Subject: [PATCH 1/6] [X86][MC] Support enc/dec for SETZUCC and promoted SETCC.

---
 .../lib/Target/X86/AsmParser/X86AsmParser.cpp |   1 +
 .../X86/MCTargetDesc/X86MCCodeEmitter.cpp     |   2 +
 llvm/lib/Target/X86/X86InstrAsmAlias.td       |   5 +
 llvm/lib/Target/X86/X86InstrCMovSetCC.td      |  17 +++
 .../MC/Disassembler/X86/apx/evex-format.txt   |  10 ++
 .../MC/Disassembler/X86/apx/setcc-evex.txt    | 130 ++++++++++++++++++
 llvm/test/MC/Disassembler/X86/apx/setzucc.txt | 130 ++++++++++++++++++
 llvm/test/MC/X86/apx/evex-format-att.s        |  10 ++
 llvm/test/MC/X86/apx/evex-format-intel.s      |  10 ++
 llvm/test/MC/X86/apx/setcc-evex-att.s         |  98 +++++++++++++
 llvm/test/MC/X86/apx/setcc-evex-intel.s       |  98 +++++++++++++
 llvm/test/MC/X86/apx/setzucc-att.s            |  98 +++++++++++++
 llvm/test/MC/X86/apx/setzucc-intel.s          |  98 +++++++++++++
 llvm/test/TableGen/x86-fold-tables.inc        |   1 +
 14 files changed, 708 insertions(+)
 create mode 100644 llvm/test/MC/Disassembler/X86/apx/setcc-evex.txt
 create mode 100644 llvm/test/MC/Disassembler/X86/apx/setzucc.txt
 create mode 100644 llvm/test/MC/X86/apx/setcc-evex-att.s
 create mode 100644 llvm/test/MC/X86/apx/setcc-evex-intel.s
 create mode 100644 llvm/test/MC/X86/apx/setzucc-att.s
 create mode 100644 llvm/test/MC/X86/apx/setzucc-intel.s

diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index 6401df9f49f033..0b5d9d971c990b 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -3287,6 +3287,7 @@ bool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
 
   // FIXME: Hack to recognize setneb as setne.
   if (PatchedName.starts_with("set") && PatchedName.ends_with("b") &&
+      PatchedName != "setzub" && PatchedName != "setzunb"&&
       PatchedName != "setb" && PatchedName != "setnb")
     PatchedName = PatchedName.substr(0, Name.size()-1);
 
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
index 92a14226a0dc05..a5859f98bae026 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
@@ -1155,6 +1155,7 @@ X86MCCodeEmitter::emitVEXOpcodePrefix(int MemOperand, const MCInst &MI,
     Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg);
     break;
   }
+  case X86II::MRMXmCC:
   case X86II::MRM0m:
   case X86II::MRM1m:
   case X86II::MRM2m:
@@ -1282,6 +1283,7 @@ X86MCCodeEmitter::emitVEXOpcodePrefix(int MemOperand, const MCInst &MI,
     Prefix.setRR2(MI, CurOp++);
     break;
   }
+  case X86II::MRMXrCC:
   case X86II::MRM0r:
   case X86II::MRM1r:
   case X86II::MRM2r:
diff --git a/llvm/lib/Target/X86/X86InstrAsmAlias.td b/llvm/lib/Target/X86/X86InstrAsmAlias.td
index 6b15213a2e6833..b0e8bc5173dbda 100644
--- a/llvm/lib/Target/X86/X86InstrAsmAlias.td
+++ b/llvm/lib/Target/X86/X86InstrAsmAlias.td
@@ -791,6 +791,11 @@ let Predicates = [In64BitMode] in {
 
   def : InstAlias<"set"#Cond#"\t$dst", (SETCCr GR8:$dst, CC), 0>;
   def : InstAlias<"set"#Cond#"\t$dst", (SETCCm i8mem:$dst, CC), 0>;
+
+  def : InstAlias<"setzu"#Cond#"\t$dst", (SETZUCCr GR8:$dst, CC), 0>;
+  def : InstAlias<"setzu"#Cond#"\t$dst", (SETZUCCm i8mem:$dst, CC), 0>;
+  def : InstAlias<"set"#Cond#"\t$dst", (SETCCr_EVEX GR8:$dst, CC), 0>;
+  def : InstAlias<"set"#Cond#"\t$dst", (SETCCm_EVEX i8mem:$dst, CC), 0>;
 }
 
 defm : CMOV_SETCC_Aliases<"o" ,  0>;
diff --git a/llvm/lib/Target/X86/X86InstrCMovSetCC.td b/llvm/lib/Target/X86/X86InstrCMovSetCC.td
index d41591f68a6050..3cc15abd90daa2 100644
--- a/llvm/lib/Target/X86/X86InstrCMovSetCC.td
+++ b/llvm/lib/Target/X86/X86InstrCMovSetCC.td
@@ -127,6 +127,23 @@ let Uses = [EFLAGS], isCodeGenOnly = 1, ForceDisassemble = 1 in {
                 TB, Sched<[WriteSETCCStore]>;
 } // Uses = [EFLAGS]
 
+// SetZUCC and promoted SetCC instructions.
+let Uses = [EFLAGS], mayStore = 1, isCodeGenOnly = 1, ForceDisassemble = 1,
+  OpEnc = EncEVEX, hasSideEffects = 0, Predicates = [HasEGPR, In64BitMode] in {
+  def SETZUCCr : I<0x40, MRMXrCC, (outs GR8:$dst), (ins ccode:$cond),
+                "setzu${cond}\t$dst", []>,
+                T_MAP4, XD, EVEX_B, NoCD8, Sched<[WriteSETCC]>;
+  def SETZUCCm : I<0x40, MRMXmCC, (outs), (ins i8mem:$dst, ccode:$cond),
+                "setzu${cond}\t$dst", []>,
+                T_MAP4, XD, EVEX_B, NoCD8, Sched<[WriteSETCCStore]>;
+  def SETCCr_EVEX : I<0x40, MRMXrCC, (outs GR8:$dst), (ins ccode:$cond),
+                "set${cond}\t$dst", []>,
+                XD, PL, Sched<[WriteSETCC]>;
+  def SETCCm_EVEX : I<0x40, MRMXmCC, (outs), (ins i8mem:$dst, ccode:$cond),
+                "set${cond}\t$dst", []>,
+                XD, PL, Sched<[WriteSETCCStore]>;
+}
+
 // SALC is an undocumented instruction. Information for this instruction can be found
 // here http://www.rcollins.org/secrets/opcodes/SALC.html
 // Set AL if carry. 
diff --git a/llvm/test/MC/Disassembler/X86/apx/evex-format.txt b/llvm/test/MC/Disassembler/X86/apx/evex-format.txt
index 1156f5c409922a..e9a9f1327a17eb 100644
--- a/llvm/test/MC/Disassembler/X86/apx/evex-format.txt
+++ b/llvm/test/MC/Disassembler/X86/apx/evex-format.txt
@@ -215,6 +215,16 @@
 # INTEL: sar	r17, r16, 123
 0x62,0xfc,0xf4,0x10,0xc1,0xf8,0x7b
 
+## MRMXrCC
+# ATT:   setzuo	%r16b
+# INTEL: setzuo	r16b
+0x62,0xfc,0x7f,0x18,0x40,0xc0
+
+## MRMXmCC
+# ATT:   setzuo	(%r16,%r17)
+# INTEL: setzuo	byte ptr [r16 + r17]
+0x62,0xfc,0x7b,0x18,0x40,0x04,0x08
+
 ## NoCD8
 
 # ATT:   {nf}	negq	123(%r16)
diff --git a/llvm/test/MC/Disassembler/X86/apx/setcc-evex.txt b/llvm/test/MC/Disassembler/X86/apx/setcc-evex.txt
new file mode 100644
index 00000000000000..1c00acfb76672a
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/setcc-evex.txt
@@ -0,0 +1,130 @@
+# RUN: llvm-mc -triple x86_64 -disassemble %s | FileCheck %s --check-prefix=ATT
+# RUN: llvm-mc -triple x86_64 -disassemble -output-asm-variant=1 %s | FileCheck %s --check-prefix=INTEL
+
+# ATT:   {evex}	seto	%al
+# INTEL: {evex}	seto	al
+0x62,0xf4,0x7f,0x08,0x40,0xc0
+
+# ATT:   {evex}	setno	%al
+# INTEL: {evex}	setno	al
+0x62,0xf4,0x7f,0x08,0x41,0xc0
+
+# ATT:   {evex}	setb	%al
+# INTEL: {evex}	setb	al
+0x62,0xf4,0x7f,0x08,0x42,0xc0
+
+# ATT:   {evex}	setae	%al
+# INTEL: {evex}	setae	al
+0x62,0xf4,0x7f,0x08,0x43,0xc0
+
+# ATT:   {evex}	sete	%al
+# INTEL: {evex}	sete	al
+0x62,0xf4,0x7f,0x08,0x44,0xc0
+
+# ATT:   {evex}	setne	%al
+# INTEL: {evex}	setne	al
+0x62,0xf4,0x7f,0x08,0x45,0xc0
+
+# ATT:   {evex}	setbe	%al
+# INTEL: {evex}	setbe	al
+0x62,0xf4,0x7f,0x08,0x46,0xc0
+
+# ATT:   {evex}	seta	%al
+# INTEL: {evex}	seta	al
+0x62,0xf4,0x7f,0x08,0x47,0xc0
+
+# ATT:   {evex}	sets	%al
+# INTEL: {evex}	sets	al
+0x62,0xf4,0x7f,0x08,0x48,0xc0
+
+# ATT:   {evex}	setns	%al
+# INTEL: {evex}	setns	al
+0x62,0xf4,0x7f,0x08,0x49,0xc0
+
+# ATT:   {evex}	setp	%al
+# INTEL: {evex}	setp	al
+0x62,0xf4,0x7f,0x08,0x4a,0xc0
+
+# ATT:   {evex}	setnp	%al
+# INTEL: {evex}	setnp	al
+0x62,0xf4,0x7f,0x08,0x4b,0xc0
+
+# ATT:   {evex}	setl	%al
+# INTEL: {evex}	setl	al
+0x62,0xf4,0x7f,0x08,0x4c,0xc0
+
+# ATT:   {evex}	setge	%al
+# INTEL: {evex}	setge	al
+0x62,0xf4,0x7f,0x08,0x4d,0xc0
+
+# ATT:   {evex}	setle	%al
+# INTEL: {evex}	setle	al
+0x62,0xf4,0x7f,0x08,0x4e,0xc0
+
+# ATT:   {evex}	setg	%al
+# INTEL: {evex}	setg	al
+0x62,0xf4,0x7f,0x08,0x4f,0xc0
+
+# ATT:   {evex}	seto	(%rax)
+# INTEL: {evex}	seto	byte ptr [rax]
+0x62,0xf4,0x7f,0x08,0x40,0x00
+
+# ATT:   {evex}	setno	(%rax)
+# INTEL: {evex}	setno	byte ptr [rax]
+0x62,0xf4,0x7f,0x08,0x41,0x00
+
+# ATT:   {evex}	setb	(%rax)
+# INTEL: {evex}	setb	byte ptr [rax]
+0x62,0xf4,0x7f,0x08,0x42,0x00
+
+# ATT:   {evex}	setae	(%rax)
+# INTEL: {evex}	setae	byte ptr [rax]
+0x62,0xf4,0x7f,0x08,0x43,0x00
+
+# ATT:   {evex}	sete	(%rax)
+# INTEL: {evex}	sete	byte ptr [rax]
+0x62,0xf4,0x7f,0x08,0x44,0x00
+
+# ATT:   {evex}	setne	(%rax)
+# INTEL: {evex}	setne	byte ptr [rax]
+0x62,0xf4,0x7f,0x08,0x45,0x00
+
+# ATT:   {evex}	setbe	(%rax)
+# INTEL: {evex}	setbe	byte ptr [rax]
+0x62,0xf4,0x7f,0x08,0x46,0x00
+
+# ATT:   {evex}	seta	(%rax)
+# INTEL: {evex}	seta	byte ptr [rax]
+0x62,0xf4,0x7f,0x08,0x47,0x00
+
+# ATT:   {evex}	sets	(%rax)
+# INTEL: {evex}	sets	byte ptr [rax]
+0x62,0xf4,0x7f,0x08,0x48,0x00
+
+# ATT:   {evex}	setns	(%rax)
+# INTEL: {evex}	setns	byte ptr [rax]
+0x62,0xf4,0x7f,0x08,0x49,0x00
+
+# ATT:   {evex}	setp	(%rax)
+# INTEL: {evex}	setp	byte ptr [rax]
+0x62,0xf4,0x7f,0x08,0x4a,0x00
+
+# ATT:   {evex}	setnp	(%rax)
+# INTEL: {evex}	setnp	byte ptr [rax]
+0x62,0xf4,0x7f,0x08,0x4b,0x00
+
+# ATT:   {evex}	setl	(%rax)
+# INTEL: {evex}	setl	byte ptr [rax]
+0x62,0xf4,0x7f,0x08,0x4c,0x00
+
+# ATT:   {evex}	setge	(%rax)
+# INTEL: {evex}	setge	byte ptr [rax]
+0x62,0xf4,0x7f,0x08,0x4d,0x00
+
+# ATT:   {evex}	setle	(%rax)
+# INTEL: {evex}	setle	byte ptr [rax]
+0x62,0xf4,0x7f,0x08,0x4e,0x00
+
+# ATT:   {evex}	setg	(%rax)
+# INTEL: {evex}	setg	byte ptr [rax]
+0x62,0xf4,0x7f,0x08,0x4f,0x00
diff --git a/llvm/test/MC/Disassembler/X86/apx/setzucc.txt b/llvm/test/MC/Disassembler/X86/apx/setzucc.txt
new file mode 100644
index 00000000000000..44aaa4b33cc854
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/setzucc.txt
@@ -0,0 +1,130 @@
+# RUN: llvm-mc -triple x86_64 -disassemble %s | FileCheck %s --check-prefix=ATT
+# RUN: llvm-mc -triple x86_64 -disassemble -output-asm-variant=1 %s | FileCheck %s --check-prefix=INTEL
+
+# ATT:   setzuo	%al
+# INTEL: setzuo	al
+0x62,0xf4,0x7f,0x18,0x40,0xc0
+
+# ATT:   setzuno	%al
+# INTEL: setzuno	al
+0x62,0xf4,0x7f,0x18,0x41,0xc0
+
+# ATT:   setzub	%al
+# INTEL: setzub	al
+0x62,0xf4,0x7f,0x18,0x42,0xc0
+
+# ATT:   setzuae	%al
+# INTEL: setzuae	al
+0x62,0xf4,0x7f,0x18,0x43,0xc0
+
+# ATT:   setzue	%al
+# INTEL: setzue	al
+0x62,0xf4,0x7f,0x18,0x44,0xc0
+
+# ATT:   setzune	%al
+# INTEL: setzune	al
+0x62,0xf4,0x7f,0x18,0x45,0xc0
+
+# ATT:   setzube	%al
+# INTEL: setzube	al
+0x62,0xf4,0x7f,0x18,0x46,0xc0
+
+# ATT:   setzua	%al
+# INTEL: setzua	al
+0x62,0xf4,0x7f,0x18,0x47,0xc0
+
+# ATT:   setzus	%al
+# INTEL: setzus	al
+0x62,0xf4,0x7f,0x18,0x48,0xc0
+
+# ATT:   setzuns	%al
+# INTEL: setzuns	al
+0x62,0xf4,0x7f,0x18,0x49,0xc0
+
+# ATT:   setzup	%al
+# INTEL: setzup	al
+0x62,0xf4,0x7f,0x18,0x4a,0xc0
+
+# ATT:   setzunp	%al
+# INTEL: setzunp	al
+0x62,0xf4,0x7f,0x18,0x4b,0xc0
+
+# ATT:   setzul	%al
+# INTEL: setzul	al
+0x62,0xf4,0x7f,0x18,0x4c,0xc0
+
+# ATT:   setzuge	%al
+# INTEL: setzuge	al
+0x62,0xf4,0x7f,0x18,0x4d,0xc0
+
+# ATT:   setzule	%al
+# INTEL: setzule	al
+0x62,0xf4,0x7f,0x18,0x4e,0xc0
+
+# ATT:   setzug	%al
+# INTEL: setzug	al
+0x62,0xf4,0x7f,0x18,0x4f,0xc0
+
+# ATT:   setzuo	(%rax)
+# INTEL: setzuo	byte ptr [rax]
+0x62,0xf4,0x7f,0x18,0x40,0x00
+
+# ATT:   setzuno	(%rax)
+# INTEL: setzuno	byte ptr [rax]
+0x62,0xf4,0x7f,0x18,0x41,0x00
+
+# ATT:   setzub	(%rax)
+# INTEL: setzub	byte ptr [rax]
+0x62,0xf4,0x7f,0x18,0x42,0x00
+
+# ATT:   setzuae	(%rax)
+# INTEL: setzuae	byte ptr [rax]
+0x62,0xf4,0x7f,0x18,0x43,0x00
+
+# ATT:   setzue	(%rax)
+# INTEL: setzue	byte ptr [rax]
+0x62,0xf4,0x7f,0x18,0x44,0x00
+
+# ATT:   setzune	(%rax)
+# INTEL: setzune	byte ptr [rax]
+0x62,0xf4,0x7f,0x18,0x45,0x00
+
+# ATT:   setzube	(%rax)
+# INTEL: setzube	byte ptr [rax]
+0x62,0xf4,0x7f,0x18,0x46,0x00
+
+# ATT:   setzua	(%rax)
+# INTEL: setzua	byte ptr [rax]
+0x62,0xf4,0x7f,0x18,0x47,0x00
+
+# ATT:   setzus	(%rax)
+# INTEL: setzus	byte ptr [rax]
+0x62,0xf4,0x7f,0x18,0x48,0x00
+
+# ATT:   setzuns	(%rax)
+# INTEL: setzuns	byte ptr [rax]
+0x62,0xf4,0x7f,0x18,0x49,0x00
+
+# ATT:   setzup	(%rax)
+# INTEL: setzup	byte ptr [rax]
+0x62,0xf4,0x7f,0x18,0x4a,0x00
+
+# ATT:   setzunp	(%rax)
+# INTEL: setzunp	byte ptr [rax]
+0x62,0xf4,0x7f,0x18,0x4b,0x00
+
+# ATT:   setzul	(%rax)
+# INTEL: setzul	byte ptr [rax]
+0x62,0xf4,0x7f,0x18,0x4c,0x00
+
+# ATT:   setzuge	(%rax)
+# INTEL: setzuge	byte ptr [rax]
+0x62,0xf4,0x7f,0x18,0x4d,0x00
+
+# ATT:   setzule	(%rax)
+# INTEL: setzule	byte ptr [rax]
+0x62,0xf4,0x7f,0x18,0x4e,0x00
+
+# ATT:   setzug	(%rax)
+# INTEL: setzug	byte ptr [rax]
+0x62,0xf4,0x7f,0x18,0x4f,0x00
diff --git a/llvm/test/MC/X86/apx/evex-format-att.s b/llvm/test/MC/X86/apx/evex-format-att.s
index 36df3f3757dc3f..e59039ea2d8225 100644
--- a/llvm/test/MC/X86/apx/evex-format-att.s
+++ b/llvm/test/MC/X86/apx/evex-format-att.s
@@ -210,6 +210,16 @@
 # CHECK: encoding: [0x62,0xfc,0xf4,0x10,0xc1,0xf8,0x7b]
          sarq	$123, %r16, %r17
 
+## MRMXrCC
+# CHECK: setzuo	%r16b
+# CHECK: encoding: [0x62,0xfc,0x7f,0x18,0x40,0xc0]
+         setzuo	%r16b
+
+## MRMXmCC
+# CHECK: setzuo	(%r16,%r17)
+# CHECK: encoding: [0x62,0xfc,0x7b,0x18,0x40,0x04,0x08]
+         setzuo	(%r16,%r17)
+
 ## NoCD8
 
 # CHECK: {nf}	negq	123(%r16)
diff --git a/llvm/test/MC/X86/apx/evex-format-intel.s b/llvm/test/MC/X86/apx/evex-format-intel.s
index 2b346e0e858063..42d4c0c0081a74 100644
--- a/llvm/test/MC/X86/apx/evex-format-intel.s
+++ b/llvm/test/MC/X86/apx/evex-format-intel.s
@@ -210,6 +210,16 @@
 # CHECK: encoding: [0x62,0xfc,0xf4,0x10,0xc1,0xf8,0x7b]
          sar	r17, r16, 123
 
+## MRMXrCC
+# CHECK: setzuo	r16b
+# CHECK: encoding: [0x62,0xfc,0x7f,0x18,0x40,0xc0]
+         setzuo r16b
+
+## MRMXmCC
+# CHECK: setzuo byte ptr [r16 + r17]
+# CHECK: encoding: [0x62,0xfc,0x7b,0x18,0x40,0x04,0x08]
+         setzuo byte ptr [r16 + r17]
+
 ## NoCD8
 
 # CHECK: {nf}	neg	qword ptr [r16 + 123]
diff --git a/llvm/test/MC/X86/apx/setcc-evex-att.s b/llvm/test/MC/X86/apx/setcc-evex-att.s
new file mode 100644
index 00000000000000..364c5ee77bf60c
--- /dev/null
+++ b/llvm/test/MC/X86/apx/setcc-evex-att.s
@@ -0,0 +1,98 @@
+# RUN: llvm-mc -triple x86_64 -show-encoding %s | FileCheck %s
+
+# CHECK: {evex}	seto	%al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x40,0xc0]
+         {evex}	setob	%al
+# CHECK: {evex}	setno	%al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x41,0xc0]
+         {evex}	setnob	%al
+# CHECK: {evex}	setb	%al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x42,0xc0]
+         {evex}	setbb	%al
+# CHECK: {evex}	setae	%al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x43,0xc0]
+         {evex}	setaeb	%al
+# CHECK: {evex}	sete	%al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x44,0xc0]
+         {evex}	seteb	%al
+# CHECK: {evex}	setne	%al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x45,0xc0]
+         {evex}	setneb	%al
+# CHECK: {evex}	setbe	%al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x46,0xc0]
+         {evex}	setbeb	%al
+# CHECK: {evex}	seta	%al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x47,0xc0]
+         {evex}	setab	%al
+# CHECK: {evex}	sets	%al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x48,0xc0]
+         {evex}	setsb	%al
+# CHECK: {evex}	setns	%al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x49,0xc0]
+         {evex}	setnsb	%al
+# CHECK: {evex}	setp	%al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4a,0xc0]
+         {evex}	setpb	%al
+# CHECK: {evex}	setnp	%al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4b,0xc0]
+         {evex}	setnpb	%al
+# CHECK: {evex}	setl	%al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4c,0xc0]
+         {evex}	setlb	%al
+# CHECK: {evex}	setge	%al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4d,0xc0]
+         {evex}	setgeb	%al
+# CHECK: {evex}	setle	%al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4e,0xc0]
+         {evex}	setleb	%al
+# CHECK: {evex}	setg	%al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4f,0xc0]
+         {evex}	setgb	%al
+# CHECK: {evex}	seto	(%rax)
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x40,0x00]
+         {evex}	setob	(%rax)
+# CHECK: {evex}	setno	(%rax)
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x41,0x00]
+         {evex}	setnob	(%rax)
+# CHECK: {evex}	setb	(%rax)
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x42,0x00]
+         {evex}	setbb	(%rax)
+# CHECK: {evex}	setae	(%rax)
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x43,0x00]
+         {evex}	setaeb	(%rax)
+# CHECK: {evex}	sete	(%rax)
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x44,0x00]
+         {evex}	seteb	(%rax)
+# CHECK: {evex}	setne	(%rax)
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x45,0x00]
+         {evex}	setneb	(%rax)
+# CHECK: {evex}	setbe	(%rax)
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x46,0x00]
+         {evex}	setbeb	(%rax)
+# CHECK: {evex}	seta	(%rax)
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x47,0x00]
+         {evex}	setab	(%rax)
+# CHECK: {evex}	sets	(%rax)
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x48,0x00]
+         {evex}	setsb	(%rax)
+# CHECK: {evex}	setns	(%rax)
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x49,0x00]
+         {evex}	setnsb	(%rax)
+# CHECK: {evex}	setp	(%rax)
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4a,0x00]
+         {evex}	setpb	(%rax)
+# CHECK: {evex}	setnp	(%rax)
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4b,0x00]
+         {evex}	setnpb	(%rax)
+# CHECK: {evex}	setl	(%rax)
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4c,0x00]
+         {evex}	setlb	(%rax)
+# CHECK: {evex}	setge	(%rax)
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4d,0x00]
+         {evex}	setgeb	(%rax)
+# CHECK: {evex}	setle	(%rax)
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4e,0x00]
+         {evex}	setleb	(%rax)
+# CHECK: {evex}	setg	(%rax)
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4f,0x00]
+         {evex}	setgb	(%rax)
diff --git a/llvm/test/MC/X86/apx/setcc-evex-intel.s b/llvm/test/MC/X86/apx/setcc-evex-intel.s
new file mode 100644
index 00000000000000..e005c2edb95c4b
--- /dev/null
+++ b/llvm/test/MC/X86/apx/setcc-evex-intel.s
@@ -0,0 +1,98 @@
+# RUN: llvm-mc -triple x86_64 -show-encoding -x86-asm-syntax=intel -output-asm-variant=1 %s | FileCheck %s
+
+# CHECK: {evex}	seto	al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x40,0xc0]
+         {evex}	seto	al
+# CHECK: {evex}	setno	al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x41,0xc0]
+         {evex}	setno	al
+# CHECK: {evex}	setb	al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x42,0xc0]
+         {evex}	setb	al
+# CHECK: {evex}	setae	al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x43,0xc0]
+         {evex}	setae	al
+# CHECK: {evex}	sete	al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x44,0xc0]
+         {evex}	sete	al
+# CHECK: {evex}	setne	al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x45,0xc0]
+         {evex}	setne	al
+# CHECK: {evex}	setbe	al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x46,0xc0]
+         {evex}	setbe	al
+# CHECK: {evex}	seta	al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x47,0xc0]
+         {evex}	seta	al
+# CHECK: {evex}	sets	al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x48,0xc0]
+         {evex}	sets	al
+# CHECK: {evex}	setns	al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x49,0xc0]
+         {evex}	setns	al
+# CHECK: {evex}	setp	al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4a,0xc0]
+         {evex}	setp	al
+# CHECK: {evex}	setnp	al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4b,0xc0]
+         {evex}	setnp	al
+# CHECK: {evex}	setl	al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4c,0xc0]
+         {evex}	setl	al
+# CHECK: {evex}	setge	al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4d,0xc0]
+         {evex}	setge	al
+# CHECK: {evex}	setle	al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4e,0xc0]
+         {evex}	setle	al
+# CHECK: {evex}	setg	al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4f,0xc0]
+         {evex}	setg	al
+# CHECK: {evex}	seto	byte ptr [rax]
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x40,0x00]
+         {evex}	seto	byte ptr [rax]
+# CHECK: {evex}	setno	byte ptr [rax]
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x41,0x00]
+         {evex}	setno	byte ptr [rax]
+# CHECK: {evex}	setb	byte ptr [rax]
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x42,0x00]
+         {evex}	setb	byte ptr [rax]
+# CHECK: {evex}	setae	byte ptr [rax]
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x43,0x00]
+         {evex}	setae	byte ptr [rax]
+# CHECK: {evex}	sete	byte ptr [rax]
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x44,0x00]
+         {evex}	sete	byte ptr [rax]
+# CHECK: {evex}	setne	byte ptr [rax]
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x45,0x00]
+         {evex}	setne	byte ptr [rax]
+# CHECK: {evex}	setbe	byte ptr [rax]
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x46,0x00]
+         {evex}	setbe	byte ptr [rax]
+# CHECK: {evex}	seta	byte ptr [rax]
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x47,0x00]
+         {evex}	seta	byte ptr [rax]
+# CHECK: {evex}	sets	byte ptr [rax]
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x48,0x00]
+         {evex}	sets	byte ptr [rax]
+# CHECK: {evex}	setns	byte ptr [rax]
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x49,0x00]
+         {evex}	setns	byte ptr [rax]
+# CHECK: {evex}	setp	byte ptr [rax]
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4a,0x00]
+         {evex}	setp	byte ptr [rax]
+# CHECK: {evex}	setnp	byte ptr [rax]
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4b,0x00]
+         {evex}	setnp	byte ptr [rax]
+# CHECK: {evex}	setl	byte ptr [rax]
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4c,0x00]
+         {evex}	setl	byte ptr [rax]
+# CHECK: {evex}	setge	byte ptr [rax]
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4d,0x00]
+         {evex}	setge	byte ptr [rax]
+# CHECK: {evex}	setle	byte ptr [rax]
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4e,0x00]
+         {evex}	setle	byte ptr [rax]
+# CHECK: {evex}	setg	byte ptr [rax]
+# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4f,0x00]
+         {evex}	setg	byte ptr [rax]
diff --git a/llvm/test/MC/X86/apx/setzucc-att.s b/llvm/test/MC/X86/apx/setzucc-att.s
new file mode 100644
index 00000000000000..31c1ab27db7f83
--- /dev/null
+++ b/llvm/test/MC/X86/apx/setzucc-att.s
@@ -0,0 +1,98 @@
+# RUN: llvm-mc -triple x86_64 -show-encoding %s | FileCheck %s
+
+# CHECK: setzuo	%al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x40,0xc0]
+         setzuo	%al
+# CHECK: setzuno	%al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x41,0xc0]
+         setzuno	%al
+# CHECK: setzub	%al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x42,0xc0]
+         setzub	%al
+# CHECK: setzuae	%al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x43,0xc0]
+         setzuae	%al
+# CHECK: setzue	%al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+         setzue	%al
+# CHECK: setzune	%al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+         setzune	%al
+# CHECK: setzube	%al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x46,0xc0]
+         setzube	%al
+# CHECK: setzua	%al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x47,0xc0]
+         setzua	%al
+# CHECK: setzus	%al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x48,0xc0]
+         setzus	%al
+# CHECK: setzuns	%al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x49,0xc0]
+         setzuns	%al
+# CHECK: setzup	%al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4a,0xc0]
+         setzup	%al
+# CHECK: setzunp	%al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4b,0xc0]
+         setzunp	%al
+# CHECK: setzul	%al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4c,0xc0]
+         setzul	%al
+# CHECK: setzuge	%al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4d,0xc0]
+         setzuge	%al
+# CHECK: setzule	%al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4e,0xc0]
+         setzule	%al
+# CHECK: setzug	%al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4f,0xc0]
+         setzug	%al
+# CHECK: setzuo	(%rax)
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x40,0x00]
+         setzuo	(%rax)
+# CHECK: setzuno	(%rax)
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x41,0x00]
+         setzuno	(%rax)
+# CHECK: setzub	(%rax)
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x42,0x00]
+         setzub	(%rax)
+# CHECK: setzuae	(%rax)
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x43,0x00]
+         setzuae	(%rax)
+# CHECK: setzue	(%rax)
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x44,0x00]
+         setzue	(%rax)
+# CHECK: setzune	(%rax)
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x45,0x00]
+         setzune	(%rax)
+# CHECK: setzube	(%rax)
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x46,0x00]
+         setzube	(%rax)
+# CHECK: setzua	(%rax)
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x47,0x00]
+         setzua	(%rax)
+# CHECK: setzus	(%rax)
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x48,0x00]
+         setzus	(%rax)
+# CHECK: setzuns	(%rax)
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x49,0x00]
+         setzuns	(%rax)
+# CHECK: setzup	(%rax)
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4a,0x00]
+         setzup	(%rax)
+# CHECK: setzunp	(%rax)
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4b,0x00]
+         setzunp	(%rax)
+# CHECK: setzul	(%rax)
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4c,0x00]
+         setzul	(%rax)
+# CHECK: setzuge	(%rax)
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4d,0x00]
+         setzuge	(%rax)
+# CHECK: setzule	(%rax)
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4e,0x00]
+         setzule	(%rax)
+# CHECK: setzug	(%rax)
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4f,0x00]
+         setzug	(%rax)
diff --git a/llvm/test/MC/X86/apx/setzucc-intel.s b/llvm/test/MC/X86/apx/setzucc-intel.s
new file mode 100644
index 00000000000000..bdefba6ac8d30a
--- /dev/null
+++ b/llvm/test/MC/X86/apx/setzucc-intel.s
@@ -0,0 +1,98 @@
+# RUN: llvm-mc -triple x86_64 -show-encoding -x86-asm-syntax=intel -output-asm-variant=1 %s | FileCheck %s
+
+# CHECK: setzuo	al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x40,0xc0]
+         setzuo	al
+# CHECK: setzuno	al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x41,0xc0]
+         setzuno	al
+# CHECK: setzub	al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x42,0xc0]
+         setzub	al
+# CHECK: setzuae	al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x43,0xc0]
+         setzuae	al
+# CHECK: setzue	al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+         setzue	al
+# CHECK: setzune	al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+         setzune	al
+# CHECK: setzube	al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x46,0xc0]
+         setzube	al
+# CHECK: setzua	al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x47,0xc0]
+         setzua	al
+# CHECK: setzus	al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x48,0xc0]
+         setzus	al
+# CHECK: setzuns	al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x49,0xc0]
+         setzuns	al
+# CHECK: setzup	al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4a,0xc0]
+         setzup	al
+# CHECK: setzunp	al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4b,0xc0]
+         setzunp	al
+# CHECK: setzul	al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4c,0xc0]
+         setzul	al
+# CHECK: setzuge	al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4d,0xc0]
+         setzuge	al
+# CHECK: setzule	al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4e,0xc0]
+         setzule	al
+# CHECK: setzug	al
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4f,0xc0]
+         setzug	al
+# CHECK: setzuo	byte ptr [rax]
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x40,0x00]
+         setzuo	byte ptr [rax]
+# CHECK: setzuno	byte ptr [rax]
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x41,0x00]
+         setzuno	byte ptr [rax]
+# CHECK: setzub	byte ptr [rax]
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x42,0x00]
+         setzub	byte ptr [rax]
+# CHECK: setzuae	byte ptr [rax]
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x43,0x00]
+         setzuae	byte ptr [rax]
+# CHECK: setzue	byte ptr [rax]
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x44,0x00]
+         setzue	byte ptr [rax]
+# CHECK: setzune	byte ptr [rax]
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x45,0x00]
+         setzune	byte ptr [rax]
+# CHECK: setzube	byte ptr [rax]
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x46,0x00]
+         setzube	byte ptr [rax]
+# CHECK: setzua	byte ptr [rax]
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x47,0x00]
+         setzua	byte ptr [rax]
+# CHECK: setzus	byte ptr [rax]
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x48,0x00]
+         setzus	byte ptr [rax]
+# CHECK: setzuns	byte ptr [rax]
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x49,0x00]
+         setzuns	byte ptr [rax]
+# CHECK: setzup	byte ptr [rax]
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4a,0x00]
+         setzup	byte ptr [rax]
+# CHECK: setzunp	byte ptr [rax]
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4b,0x00]
+         setzunp	byte ptr [rax]
+# CHECK: setzul	byte ptr [rax]
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4c,0x00]
+         setzul	byte ptr [rax]
+# CHECK: setzuge	byte ptr [rax]
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4d,0x00]
+         setzuge	byte ptr [rax]
+# CHECK: setzule	byte ptr [rax]
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4e,0x00]
+         setzule	byte ptr [rax]
+# CHECK: setzug	byte ptr [rax]
+# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4f,0x00]
+         setzug	byte ptr [rax]
diff --git a/llvm/test/TableGen/x86-fold-tables.inc b/llvm/test/TableGen/x86-fold-tables.inc
index 7b65e483c39d0d..25af859f7b7a1b 100644
--- a/llvm/test/TableGen/x86-fold-tables.inc
+++ b/llvm/test/TableGen/x86-fold-tables.inc
@@ -468,6 +468,7 @@ static const X86FoldTableEntry Table0[] = {
   {X86::PUSH32r, X86::PUSH32rmm, TB_FOLDED_LOAD},
   {X86::PUSH64r, X86::PUSH64rmm, TB_FOLDED_LOAD},
   {X86::SETCCr, X86::SETCCm, TB_FOLDED_STORE},
+  {X86::SETZUCCr, X86::SETZUCCm, TB_FOLDED_STORE},
   {X86::TAILJMPr, X86::TAILJMPm, TB_FOLDED_LOAD},
   {X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD},
   {X86::TAILJMPr64_REX, X86::TAILJMPm64_REX, TB_FOLDED_LOAD},

>From 5f8ae8978f53bb0a3d9f5636b2e95a4e4779202d Mon Sep 17 00:00:00 2001
From: Freddy Ye <freddy.ye at intel.com>
Date: Mon, 25 Mar 2024 16:08:33 +0800
Subject: [PATCH 2/6] clang-format

---
 llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index 0b5d9d971c990b..b05a036fb2f06b 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -3287,7 +3287,7 @@ bool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
 
   // FIXME: Hack to recognize setneb as setne.
   if (PatchedName.starts_with("set") && PatchedName.ends_with("b") &&
-      PatchedName != "setzub" && PatchedName != "setzunb"&&
+      PatchedName != "setzub" && PatchedName != "setzunb" &&
       PatchedName != "setb" && PatchedName != "setnb")
     PatchedName = PatchedName.substr(0, Name.size()-1);
 

>From 85f8ab0b7986b8e1f823ac4cc5b639440b0ce77c Mon Sep 17 00:00:00 2001
From: Freddy Ye <freddy.ye at intel.com>
Date: Tue, 26 Mar 2024 17:07:59 +0800
Subject: [PATCH 3/6] Address comments.

---
 .../X86/apx/{setcc-evex.txt => setcc.txt}     |  0
 .../X86/apx/{setcc-evex-att.s => setcc-att.s} | 62 +++++++++----------
 .../apx/{setcc-evex-intel.s => setcc-intel.s} |  0
 3 files changed, 31 insertions(+), 31 deletions(-)
 rename llvm/test/MC/Disassembler/X86/apx/{setcc-evex.txt => setcc.txt} (100%)
 rename llvm/test/MC/X86/apx/{setcc-evex-att.s => setcc-att.s} (74%)
 rename llvm/test/MC/X86/apx/{setcc-evex-intel.s => setcc-intel.s} (100%)

diff --git a/llvm/test/MC/Disassembler/X86/apx/setcc-evex.txt b/llvm/test/MC/Disassembler/X86/apx/setcc.txt
similarity index 100%
rename from llvm/test/MC/Disassembler/X86/apx/setcc-evex.txt
rename to llvm/test/MC/Disassembler/X86/apx/setcc.txt
diff --git a/llvm/test/MC/X86/apx/setcc-evex-att.s b/llvm/test/MC/X86/apx/setcc-att.s
similarity index 74%
rename from llvm/test/MC/X86/apx/setcc-evex-att.s
rename to llvm/test/MC/X86/apx/setcc-att.s
index 364c5ee77bf60c..319564704575ad 100644
--- a/llvm/test/MC/X86/apx/setcc-evex-att.s
+++ b/llvm/test/MC/X86/apx/setcc-att.s
@@ -2,97 +2,97 @@
 
 # CHECK: {evex}	seto	%al
 # CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x40,0xc0]
-         {evex}	setob	%al
+         {evex}	seto	%al
 # CHECK: {evex}	setno	%al
 # CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x41,0xc0]
-         {evex}	setnob	%al
+         {evex}	setno	%al
 # CHECK: {evex}	setb	%al
 # CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x42,0xc0]
-         {evex}	setbb	%al
+         {evex}	setb	%al
 # CHECK: {evex}	setae	%al
 # CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x43,0xc0]
-         {evex}	setaeb	%al
+         {evex}	setae	%al
 # CHECK: {evex}	sete	%al
 # CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x44,0xc0]
-         {evex}	seteb	%al
+         {evex}	sete	%al
 # CHECK: {evex}	setne	%al
 # CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x45,0xc0]
-         {evex}	setneb	%al
+         {evex}	setne	%al
 # CHECK: {evex}	setbe	%al
 # CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x46,0xc0]
-         {evex}	setbeb	%al
+         {evex}	setbe	%al
 # CHECK: {evex}	seta	%al
 # CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x47,0xc0]
-         {evex}	setab	%al
+         {evex}	seta	%al
 # CHECK: {evex}	sets	%al
 # CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x48,0xc0]
-         {evex}	setsb	%al
+         {evex}	sets	%al
 # CHECK: {evex}	setns	%al
 # CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x49,0xc0]
-         {evex}	setnsb	%al
+         {evex}	setns	%al
 # CHECK: {evex}	setp	%al
 # CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4a,0xc0]
-         {evex}	setpb	%al
+         {evex}	setp	%al
 # CHECK: {evex}	setnp	%al
 # CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4b,0xc0]
-         {evex}	setnpb	%al
+         {evex}	setnp	%al
 # CHECK: {evex}	setl	%al
 # CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4c,0xc0]
-         {evex}	setlb	%al
+         {evex}	setl	%al
 # CHECK: {evex}	setge	%al
 # CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4d,0xc0]
-         {evex}	setgeb	%al
+         {evex}	setge	%al
 # CHECK: {evex}	setle	%al
 # CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4e,0xc0]
-         {evex}	setleb	%al
+         {evex}	setle	%al
 # CHECK: {evex}	setg	%al
 # CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4f,0xc0]
-         {evex}	setgb	%al
+         {evex}	setg	%al
 # CHECK: {evex}	seto	(%rax)
 # CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x40,0x00]
-         {evex}	setob	(%rax)
+         {evex}	seto	(%rax)
 # CHECK: {evex}	setno	(%rax)
 # CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x41,0x00]
-         {evex}	setnob	(%rax)
+         {evex}	setno	(%rax)
 # CHECK: {evex}	setb	(%rax)
 # CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x42,0x00]
-         {evex}	setbb	(%rax)
+         {evex}	setb	(%rax)
 # CHECK: {evex}	setae	(%rax)
 # CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x43,0x00]
-         {evex}	setaeb	(%rax)
+         {evex}	setae	(%rax)
 # CHECK: {evex}	sete	(%rax)
 # CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x44,0x00]
-         {evex}	seteb	(%rax)
+         {evex}	sete	(%rax)
 # CHECK: {evex}	setne	(%rax)
 # CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x45,0x00]
-         {evex}	setneb	(%rax)
+         {evex}	setne	(%rax)
 # CHECK: {evex}	setbe	(%rax)
 # CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x46,0x00]
-         {evex}	setbeb	(%rax)
+         {evex}	setbe	(%rax)
 # CHECK: {evex}	seta	(%rax)
 # CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x47,0x00]
-         {evex}	setab	(%rax)
+         {evex}	seta	(%rax)
 # CHECK: {evex}	sets	(%rax)
 # CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x48,0x00]
-         {evex}	setsb	(%rax)
+         {evex}	sets	(%rax)
 # CHECK: {evex}	setns	(%rax)
 # CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x49,0x00]
-         {evex}	setnsb	(%rax)
+         {evex}	setns	(%rax)
 # CHECK: {evex}	setp	(%rax)
 # CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4a,0x00]
-         {evex}	setpb	(%rax)
+         {evex}	setp	(%rax)
 # CHECK: {evex}	setnp	(%rax)
 # CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4b,0x00]
-         {evex}	setnpb	(%rax)
+         {evex}	setnp	(%rax)
 # CHECK: {evex}	setl	(%rax)
 # CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4c,0x00]
-         {evex}	setlb	(%rax)
+         {evex}	setl	(%rax)
 # CHECK: {evex}	setge	(%rax)
 # CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4d,0x00]
-         {evex}	setgeb	(%rax)
+         {evex}	setge	(%rax)
 # CHECK: {evex}	setle	(%rax)
 # CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4e,0x00]
-         {evex}	setleb	(%rax)
+         {evex}	setle	(%rax)
 # CHECK: {evex}	setg	(%rax)
 # CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4f,0x00]
          {evex}	setgb	(%rax)
diff --git a/llvm/test/MC/X86/apx/setcc-evex-intel.s b/llvm/test/MC/X86/apx/setcc-intel.s
similarity index 100%
rename from llvm/test/MC/X86/apx/setcc-evex-intel.s
rename to llvm/test/MC/X86/apx/setcc-intel.s

>From 7d8a1a2a528537b22f2c14ad6b3d520cd34bedea Mon Sep 17 00:00:00 2001
From: Freddy Ye <freddy.ye at intel.com>
Date: Thu, 28 Mar 2024 13:17:48 +0800
Subject: [PATCH 4/6] Address comments.

---
 llvm/lib/Target/X86/X86InstrCMovSetCC.td | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/llvm/lib/Target/X86/X86InstrCMovSetCC.td b/llvm/lib/Target/X86/X86InstrCMovSetCC.td
index 3cc15abd90daa2..c80f6e94083a15 100644
--- a/llvm/lib/Target/X86/X86InstrCMovSetCC.td
+++ b/llvm/lib/Target/X86/X86InstrCMovSetCC.td
@@ -128,20 +128,23 @@ let Uses = [EFLAGS], isCodeGenOnly = 1, ForceDisassemble = 1 in {
 } // Uses = [EFLAGS]
 
 // SetZUCC and promoted SetCC instructions.
-let Uses = [EFLAGS], mayStore = 1, isCodeGenOnly = 1, ForceDisassemble = 1,
-  OpEnc = EncEVEX, hasSideEffects = 0, Predicates = [HasEGPR, In64BitMode] in {
+let Uses = [EFLAGS], isCodeGenOnly = 1, ForceDisassemble = 1, OpEnc = EncEVEX,
+  hasSideEffects = 0, Predicates = [HasEGPR, In64BitMode] in {
   def SETZUCCr : I<0x40, MRMXrCC, (outs GR8:$dst), (ins ccode:$cond),
                 "setzu${cond}\t$dst", []>,
                 T_MAP4, XD, EVEX_B, NoCD8, Sched<[WriteSETCC]>;
-  def SETZUCCm : I<0x40, MRMXmCC, (outs), (ins i8mem:$dst, ccode:$cond),
-                "setzu${cond}\t$dst", []>,
-                T_MAP4, XD, EVEX_B, NoCD8, Sched<[WriteSETCCStore]>;
   def SETCCr_EVEX : I<0x40, MRMXrCC, (outs GR8:$dst), (ins ccode:$cond),
                 "set${cond}\t$dst", []>,
                 XD, PL, Sched<[WriteSETCC]>;
+  let mayStore = 1 {
+  def SETZUCCm : I<0x40, MRMXmCC, (outs), (ins i8mem:$dst, ccode:$cond),
+                "setzu${cond}\t$dst", []>,
+                T_MAP4, XD, EVEX_B, NoCD8, Sched<[WriteSETCCStore]>;
+
   def SETCCm_EVEX : I<0x40, MRMXmCC, (outs), (ins i8mem:$dst, ccode:$cond),
                 "set${cond}\t$dst", []>,
                 XD, PL, Sched<[WriteSETCCStore]>;
+  }
 }
 
 // SALC is an undocumented instruction. Information for this instruction can be found

>From 1c21eaf6f6cc01e641f9832b6c9ad55ae49cf75c Mon Sep 17 00:00:00 2001
From: Freddy Ye <freddy.ye at intel.com>
Date: Tue, 2 Apr 2024 11:48:59 +0800
Subject: [PATCH 5/6] [Hack] Address comments.

---
 llvm/lib/Target/X86/X86InstrAsmAlias.td  | 12 ++++++++++--
 llvm/lib/Target/X86/X86InstrCMovSetCC.td | 17 ++++++++---------
 llvm/test/MC/X86/apx/setcc-att.s         |  3 +++
 llvm/test/MC/X86/apx/setzucc-att.s       |  3 +++
 4 files changed, 24 insertions(+), 11 deletions(-)

diff --git a/llvm/lib/Target/X86/X86InstrAsmAlias.td b/llvm/lib/Target/X86/X86InstrAsmAlias.td
index b0e8bc5173dbda..9610688e156af5 100644
--- a/llvm/lib/Target/X86/X86InstrAsmAlias.td
+++ b/llvm/lib/Target/X86/X86InstrAsmAlias.td
@@ -760,7 +760,7 @@ def : InstAlias<"xor{q}\t{$imm, %rax|rax, $imm}", (XOR64ri8 RAX, i64i8imm:$imm),
 def : InstAlias<"movq.s\t{$src, $dst|$dst, $src}",
                 (MMX_MOVQ64rr_REV VR64:$dst, VR64:$src), 0>;
 
-//  CMOV SETCC Aliases
+//  CMOV SETCC SETZUCC Aliases
 multiclass CMOV_SETCC_Aliases<string Cond, int CC> {
   def : InstAlias<"cmov"#Cond#"{w}\t{$src, $dst|$dst, $src}",
                   (CMOV16rr GR16:$dst, GR16:$src, CC), 0>;
@@ -787,8 +787,9 @@ let Predicates = [In64BitMode] in {
                   (CMOV64rr_ND GR64:$dst, GR64:$src1, GR64:$src2, CC), 0>;
   def : InstAlias<"cmov"#Cond#"{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
                   (CMOV64rm_ND GR64:$dst, GR64:$src1, i64mem:$src2, CC), 0>;
-}
 
+  // FIXME: below codes is to hack 32bit codes encoded as Legacy version but
+  // not EVEX versoin.
   def : InstAlias<"set"#Cond#"\t$dst", (SETCCr GR8:$dst, CC), 0>;
   def : InstAlias<"set"#Cond#"\t$dst", (SETCCm i8mem:$dst, CC), 0>;
 
@@ -797,6 +798,13 @@ let Predicates = [In64BitMode] in {
   def : InstAlias<"set"#Cond#"\t$dst", (SETCCr_EVEX GR8:$dst, CC), 0>;
   def : InstAlias<"set"#Cond#"\t$dst", (SETCCm_EVEX i8mem:$dst, CC), 0>;
 }
+  // FIXME: below codes is to hack 32bit codes encoded as Legacy version but
+  // not EVEX versoin.
+  let Predicates = [Not64BitMode] in {
+    def : InstAlias<"set"#Cond#"\t$dst", (SETCCr GR8:$dst, CC), 0>;
+    def : InstAlias<"set"#Cond#"\t$dst", (SETCCm i8mem:$dst, CC), 0>;
+  }
+}
 
 defm : CMOV_SETCC_Aliases<"o" ,  0>;
 defm : CMOV_SETCC_Aliases<"no",  1>;
diff --git a/llvm/lib/Target/X86/X86InstrCMovSetCC.td b/llvm/lib/Target/X86/X86InstrCMovSetCC.td
index c80f6e94083a15..0d518b83a9f439 100644
--- a/llvm/lib/Target/X86/X86InstrCMovSetCC.td
+++ b/llvm/lib/Target/X86/X86InstrCMovSetCC.td
@@ -129,21 +129,20 @@ let Uses = [EFLAGS], isCodeGenOnly = 1, ForceDisassemble = 1 in {
 
 // SetZUCC and promoted SetCC instructions.
 let Uses = [EFLAGS], isCodeGenOnly = 1, ForceDisassemble = 1, OpEnc = EncEVEX,
-  hasSideEffects = 0, Predicates = [HasEGPR, In64BitMode] in {
+  hasSideEffects = 0, Predicates = [In64BitMode], Predicates = [HasNDD] in {
   def SETZUCCr : I<0x40, MRMXrCC, (outs GR8:$dst), (ins ccode:$cond),
                 "setzu${cond}\t$dst", []>,
                 T_MAP4, XD, EVEX_B, NoCD8, Sched<[WriteSETCC]>;
   def SETCCr_EVEX : I<0x40, MRMXrCC, (outs GR8:$dst), (ins ccode:$cond),
                 "set${cond}\t$dst", []>,
                 XD, PL, Sched<[WriteSETCC]>;
-  let mayStore = 1 {
-  def SETZUCCm : I<0x40, MRMXmCC, (outs), (ins i8mem:$dst, ccode:$cond),
-                "setzu${cond}\t$dst", []>,
-                T_MAP4, XD, EVEX_B, NoCD8, Sched<[WriteSETCCStore]>;
-
-  def SETCCm_EVEX : I<0x40, MRMXmCC, (outs), (ins i8mem:$dst, ccode:$cond),
-                "set${cond}\t$dst", []>,
-                XD, PL, Sched<[WriteSETCCStore]>;
+  let mayStore = 1 in {
+    def SETZUCCm : I<0x40, MRMXmCC, (outs), (ins i8mem:$dst, ccode:$cond),
+                  "setzu${cond}\t$dst", []>,
+                  T_MAP4, XD, EVEX_B, NoCD8, Sched<[WriteSETCCStore]>;
+    def SETCCm_EVEX : I<0x40, MRMXmCC, (outs), (ins i8mem:$dst, ccode:$cond),
+                  "set${cond}\t$dst", []>,
+                  XD, PL, Sched<[WriteSETCCStore]>;
   }
 }
 
diff --git a/llvm/test/MC/X86/apx/setcc-att.s b/llvm/test/MC/X86/apx/setcc-att.s
index 319564704575ad..b5518081a82012 100644
--- a/llvm/test/MC/X86/apx/setcc-att.s
+++ b/llvm/test/MC/X86/apx/setcc-att.s
@@ -1,5 +1,8 @@
 # RUN: llvm-mc -triple x86_64 -show-encoding %s | FileCheck %s
+# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
 
+# ERROR-COUNT-32: error:
+# ERROR-NOT: error:
 # CHECK: {evex}	seto	%al
 # CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x40,0xc0]
          {evex}	seto	%al
diff --git a/llvm/test/MC/X86/apx/setzucc-att.s b/llvm/test/MC/X86/apx/setzucc-att.s
index 31c1ab27db7f83..b4b7a633fa319a 100644
--- a/llvm/test/MC/X86/apx/setzucc-att.s
+++ b/llvm/test/MC/X86/apx/setzucc-att.s
@@ -1,5 +1,8 @@
 # RUN: llvm-mc -triple x86_64 -show-encoding %s | FileCheck %s
+# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
 
+# ERROR-COUNT-32: error:
+# ERROR-NOT: error:
 # CHECK: setzuo	%al
 # CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x40,0xc0]
          setzuo	%al

>From 176c2f1715ba5cdbaa238d19634930d0bbba0514 Mon Sep 17 00:00:00 2001
From: Freddy Ye <freddy.ye at intel.com>
Date: Tue, 2 Apr 2024 13:14:55 +0800
Subject: [PATCH 6/6] use ZU

---
 llvm/lib/Target/X86/X86InstrCMovSetCC.td | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/Target/X86/X86InstrCMovSetCC.td b/llvm/lib/Target/X86/X86InstrCMovSetCC.td
index 0d518b83a9f439..27a0c889a4da3e 100644
--- a/llvm/lib/Target/X86/X86InstrCMovSetCC.td
+++ b/llvm/lib/Target/X86/X86InstrCMovSetCC.td
@@ -128,18 +128,18 @@ let Uses = [EFLAGS], isCodeGenOnly = 1, ForceDisassemble = 1 in {
 } // Uses = [EFLAGS]
 
 // SetZUCC and promoted SetCC instructions.
-let Uses = [EFLAGS], isCodeGenOnly = 1, ForceDisassemble = 1, OpEnc = EncEVEX,
+let Uses = [EFLAGS], isCodeGenOnly = 1, ForceDisassemble = 1,
   hasSideEffects = 0, Predicates = [In64BitMode], Predicates = [HasNDD] in {
   def SETZUCCr : I<0x40, MRMXrCC, (outs GR8:$dst), (ins ccode:$cond),
                 "setzu${cond}\t$dst", []>,
-                T_MAP4, XD, EVEX_B, NoCD8, Sched<[WriteSETCC]>;
+                XD, ZU, NoCD8, Sched<[WriteSETCC]>;
   def SETCCr_EVEX : I<0x40, MRMXrCC, (outs GR8:$dst), (ins ccode:$cond),
                 "set${cond}\t$dst", []>,
                 XD, PL, Sched<[WriteSETCC]>;
   let mayStore = 1 in {
     def SETZUCCm : I<0x40, MRMXmCC, (outs), (ins i8mem:$dst, ccode:$cond),
                   "setzu${cond}\t$dst", []>,
-                  T_MAP4, XD, EVEX_B, NoCD8, Sched<[WriteSETCCStore]>;
+                  XD, ZU, NoCD8, Sched<[WriteSETCCStore]>;
     def SETCCm_EVEX : I<0x40, MRMXmCC, (outs), (ins i8mem:$dst, ccode:$cond),
                   "set${cond}\t$dst", []>,
                   XD, PL, Sched<[WriteSETCCStore]>;



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