[llvm] [RISCV] Support postRA vsetvl insertion pass (PR #70549)

[Piyou Chen via llvm-commits]

================
@@ -1551,11 +1735,29 @@ void RISCVInsertVSETVLI::doLocalPostpass(MachineBasicBlock &MBB) {
       Used.demandVL();
 
     if (NextMI) {
+
+      // A tail undefined vmv.v.i/x or vfmv.v.f with VL=1 can be treated in the
+      // same semantically as vmv.s.x.
+      if (MIInBetween.size() == 1 && isScalarSplatInstr(*MIInBetween[0]) &&
+          MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 1 &&
+          isLMUL1OrSmaller(RISCVVType::getVLMUL(MI.getOperand(2).getImm())) &&
+          hasUndefinedMergeOp(*MIInBetween[0], *MRI, LIS)) {
+        Used.LMUL = false;
+        Used.SEWLMULRatio = false;
+        Used.VLAny = false;
+        if (isFloatScalarMoveOrScalarSplatInstr(*MIInBetween[0]) &&
+            !ST->hasVInstructionsF64())
+          Used.SEW = DemandedFields::SEWGreaterThanOrEqualAndLessThan64;
+        else
+          Used.SEW = DemandedFields::SEWGreaterThanOrEqual;
+        Used.TailPolicy = false;
+      }
+
       if (!Used.usedVL() && !Used.usedVTYPE()) {
         ToDelete.push_back(&MI);
         // Leave NextMI unchanged
         continue;
-      } else if (canMutatePriorConfig(MI, *NextMI, Used, *MRI)) {
+      } else if (canMutatePriorConfig(MI, *NextMI, Used, *MRI, LIS)) {
         if (!isVLPreservingConfig(*NextMI)) {
           MI.getOperand(0).setReg(NextMI->getOperand(0).getReg());
----------------
BeMg wrote:

It is possible to redefine the same virtual register between MI and NextMI (Due to no longer SSA form). I added further checks to ensure they share the same virtual register definition.

https://github.com/llvm/llvm-project/pull/70549/commits/8cf0423982e3517557ec9beae2acb4b52e349036 

However, I found that this change doesn't affect the LLVM lit at all.

https://github.com/llvm/llvm-project/pull/70549