[llvm] [AVR][NFC] Improve format of target description files (PR #87212)
Ben Shi via llvm-commits
llvm-commits at lists.llvm.org
Sun Mar 31 18:31:45 PDT 2024
https://github.com/benshi001 created https://github.com/llvm/llvm-project/pull/87212
None
>From e2d698bd2516e1f6d665d1e5154eea1fc6567c1a Mon Sep 17 00:00:00 2001
From: Ben Shi <bennshi at tencent.com>
Date: Mon, 1 Apr 2024 09:26:53 +0800
Subject: [PATCH] [AVR][NFC] Improve format of target description files
---
llvm/lib/Target/AVR/AVRInstrInfo.td | 320 +++++++---------------------
1 file changed, 75 insertions(+), 245 deletions(-)
diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.td b/llvm/lib/Target/AVR/AVRInstrInfo.td
index fe0d3b6c8189b7..38ebfab64c618d 100644
--- a/llvm/lib/Target/AVR/AVRInstrInfo.td
+++ b/llvm/lib/Target/AVR/AVRInstrInfo.td
@@ -343,13 +343,9 @@ def AVR_COND_PL : PatLeaf<(i8 7)>;
// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
// sub / add which can clobber SREG.
let Defs = [SP, SREG], Uses = [SP] in {
- def ADJCALLSTACKDOWN : Pseudo<(outs),
- (ins i16imm
- : $amt, i16imm
- : $amt2),
- "#ADJCALLSTACKDOWN", [(AVRcallseq_start timm
- : $amt, timm
- : $amt2)]>;
+ def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i16imm:$amt, i16imm:$amt2),
+ "#ADJCALLSTACKDOWN",
+ [(AVRcallseq_start timm:$amt, timm:$amt2)]>;
// R31R30 is used to update SP. It is normally free because it is a
// call-clobbered register but it is necessary to set it as a def as the
@@ -357,13 +353,8 @@ let Defs = [SP, SREG], Uses = [SP] in {
// seems). hasSideEffects needs to be set to true so this instruction isn't
// considered dead.
let Defs = [R31R30], hasSideEffects = 1 in def ADJCALLSTACKUP
- : Pseudo<(outs),
- (ins i16imm
- : $amt1, i16imm
- : $amt2),
- "#ADJCALLSTACKUP", [(AVRcallseq_end timm
- : $amt1, timm
- : $amt2)]>;
+ : Pseudo<(outs), (ins i16imm:$amt1, i16imm:$amt2),
+ "#ADJCALLSTACKUP", [(AVRcallseq_end timm:$amt1, timm:$amt2)]>;
}
//===----------------------------------------------------------------------===//
@@ -372,19 +363,9 @@ let Defs = [SP, SREG], Uses = [SP] in {
let isCommutable = 1, Constraints = "$src = $rd", Defs = [SREG] in {
// ADD Rd, Rr
// Adds two 8-bit registers.
- def ADDRdRr
- : FRdRr<0b0000, 0b11,
- (outs GPR8
- : $rd),
- (ins GPR8
- : $src, GPR8
- : $rr),
- "add\t$rd, $rr",
- [(set i8
- : $rd, (add i8
- : $src, i8
- : $rr)),
- (implicit SREG)]>;
+ def ADDRdRr : FRdRr<0b0000, 0b11, (outs GPR8:$rd),(ins GPR8:$src, GPR8:$rr),
+ "add\t$rd, $rr",
+ [(set i8:$rd, (add i8:$src, i8:$rr)), (implicit SREG)]>;
// ADDW Rd+1:Rd, Rr+1:Rr
// Pseudo instruction to add four 8-bit registers as two 16-bit values.
@@ -392,34 +373,17 @@ let isCommutable = 1, Constraints = "$src = $rd", Defs = [SREG] in {
// Expands to:
// add Rd, Rr
// adc Rd+1, Rr+1
- def ADDWRdRr
- : Pseudo<(outs DREGS
- : $rd),
- (ins DREGS
- : $src, DREGS
- : $rr),
- "addw\t$rd, $rr",
- [(set i16
- : $rd, (add i16
- : $src, i16
- : $rr)),
- (implicit SREG)]>;
+ def ADDWRdRr : Pseudo<(outs DREGS:$rd), (ins DREGS:$src, DREGS:$rr),
+ "addw\t$rd, $rr",
+ [(set i16:$rd, (add i16:$src, i16:$rr)),
+ (implicit SREG)]>;
// ADC Rd, Rr
// Adds two 8-bit registers with carry.
- let Uses = [SREG] in def ADCRdRr
- : FRdRr<0b0001, 0b11,
- (outs GPR8
- : $rd),
- (ins GPR8
- : $src, GPR8
- : $rr),
- "adc\t$rd, $rr",
- [(set i8
- : $rd, (adde i8
- : $src, i8
- : $rr)),
- (implicit SREG)]>;
+ let Uses = [SREG] in
+ def ADCRdRr : FRdRr<0b0001, 0b11, (outs GPR8:$rd), (ins GPR8:$src, GPR8:$rr),
+ "adc\t$rd, $rr",
+ [(set i8:$rd, (adde i8:$src, i8:$rr)), (implicit SREG)]>;
// ADCW Rd+1:Rd, Rr+1:Rr
// Pseudo instruction to add four 8-bit registers as two 16-bit values with
@@ -428,56 +392,30 @@ let isCommutable = 1, Constraints = "$src = $rd", Defs = [SREG] in {
// Expands to:
// adc Rd, Rr
// adc Rd+1, Rr+1
- let Uses = [SREG] in def ADCWRdRr : Pseudo<(outs DREGS
- : $rd),
- (ins DREGS
- : $src, DREGS
- : $rr),
- "adcw\t$rd, $rr", [
- (set i16
- : $rd, (adde i16
- : $src, i16
- : $rr)),
- (implicit SREG)
- ]>;
+ let Uses = [SREG] in
+ def ADCWRdRr : Pseudo<(outs DREGS:$rd), (ins DREGS:$src, DREGS:$rr),
+ "adcw\t$rd, $rr",
+ [(set i16:$rd, (adde i16:$src, i16:$rr)),
+ (implicit SREG)]>;
// AIDW Rd, k
// Adds an immediate 6-bit value K to Rd, placing the result in Rd.
- def ADIWRdK
- : FWRdK<0b0,
- (outs IWREGS
- : $rd),
- (ins IWREGS
- : $src, imm_arith6
- : $k),
- "adiw\t$rd, $k",
- [(set i16
- : $rd, (add i16
- : $src, uimm6
- : $k)),
- (implicit SREG)]>,
- Requires<[HasADDSUBIW]>;
+ def ADIWRdK : FWRdK<0b0, (outs IWREGS:$rd), (ins IWREGS :$src, imm_arith6:$k),
+ "adiw\t$rd, $k",
+ [(set i16:$rd, (add i16:$src, uimm6:$k)),
+ (implicit SREG)]>,
+ Requires<[HasADDSUBIW]>;
}
//===----------------------------------------------------------------------===//
// Subtraction
//===----------------------------------------------------------------------===//
-let Constraints = "$src = $rd", Defs = [SREG] in {
+let Constraints = "$rs = $rd", Defs = [SREG] in {
// SUB Rd, Rr
// Subtracts the 8-bit value of Rr from Rd and places the value in Rd.
- def SUBRdRr
- : FRdRr<0b0001, 0b10,
- (outs GPR8
- : $rd),
- (ins GPR8
- : $src, GPR8
- : $rr),
- "sub\t$rd, $rr",
- [(set i8
- : $rd, (sub i8
- : $src, i8
- : $rr)),
- (implicit SREG)]>;
+ def SUBRdRr : FRdRr<0b0001, 0b10, (outs GPR8:$rd), (ins GPR8:$rs, GPR8:$rr),
+ "sub\t$rd, $rr",
+ [(set i8:$rd, (sub i8:$rs, i8:$rr)), (implicit SREG)]>;
// SUBW Rd+1:Rd, Rr+1:Rr
// Subtracts two 16-bit values and places the result into Rd.
@@ -485,129 +423,58 @@ let Constraints = "$src = $rd", Defs = [SREG] in {
// Expands to:
// sub Rd, Rr
// sbc Rd+1, Rr+1
- def SUBWRdRr
- : Pseudo<(outs DREGS
- : $rd),
- (ins DREGS
- : $src, DREGS
- : $rr),
- "subw\t$rd, $rr",
- [(set i16
- : $rd, (sub i16
- : $src, i16
- : $rr)),
- (implicit SREG)]>;
+ def SUBWRdRr : Pseudo<(outs DREGS:$rd), (ins DREGS:$rs, DREGS:$rr),
+ "subw\t$rd, $rr",
+ [(set i16:$rd, (sub i16:$rs, i16:$rr)),
+ (implicit SREG)]>;
- def SUBIRdK
- : FRdK<0b0101,
- (outs LD8
- : $rd),
- (ins LD8
- : $src, imm_ldi8
- : $k),
- "subi\t$rd, $k",
- [(set i8
- : $rd, (sub i8
- : $src, imm
- : $k)),
- (implicit SREG)]>;
+ def SUBIRdK : FRdK<0b0101, (outs LD8:$rd), (ins LD8:$rs, imm_ldi8:$k),
+ "subi\t$rd, $k",
+ [(set i8:$rd, (sub i8:$rs, imm:$k)), (implicit SREG)]>;
// SUBIW Rd+1:Rd, K+1:K
//
// Expands to:
// subi Rd, K
// sbci Rd+1, K+1
- def SUBIWRdK
- : Pseudo<(outs DLDREGS
- : $rd),
- (ins DLDREGS
- : $src, i16imm
- : $rr),
- "subiw\t$rd, $rr",
- [(set i16
- : $rd, (sub i16
- : $src, imm
- : $rr)),
- (implicit SREG)]>;
+ def SUBIWRdK : Pseudo<(outs DLDREGS:$rd), (ins DLDREGS:$rs, i16imm:$rr),
+ "subiw\t$rd, $rr",
+ [(set i16:$rd, (sub i16:$rs, imm:$rr)),
+ (implicit SREG)]>;
- def SBIWRdK
- : FWRdK<0b1,
- (outs IWREGS
- : $rd),
- (ins IWREGS
- : $src, imm_arith6
- : $k),
- "sbiw\t$rd, $k",
- [(set i16
- : $rd, (sub i16
- : $src, uimm6
- : $k)),
- (implicit SREG)]>,
- Requires<[HasADDSUBIW]>;
+ def SBIWRdK : FWRdK<0b1, (outs IWREGS:$rd), (ins IWREGS:$rs, imm_arith6:$k),
+ "sbiw\t$rd, $k",
+ [(set i16:$rd, (sub i16:$rs, uimm6:$k)),
+ (implicit SREG)]>,
+ Requires<[HasADDSUBIW]>;
// Subtract with carry operations which must read the carry flag in SREG.
let Uses = [SREG] in {
- def SBCRdRr
- : FRdRr<0b0000, 0b10,
- (outs GPR8
- : $rd),
- (ins GPR8
- : $src, GPR8
- : $rr),
- "sbc\t$rd, $rr",
- [(set i8
- : $rd, (sube i8
- : $src, i8
- : $rr)),
- (implicit SREG)]>;
+ def SBCRdRr : FRdRr<0b0000, 0b10, (outs GPR8:$rd), (ins GPR8:$rs, GPR8:$rr),
+ "sbc\t$rd, $rr",
+ [(set i8:$rd, (sube i8:$rs, i8:$rr)), (implicit SREG)]>;
// SBCW Rd+1:Rd, Rr+1:Rr
//
// Expands to:
// sbc Rd, Rr
// sbc Rd+1, Rr+1
- def SBCWRdRr : Pseudo<(outs DREGS
- : $rd),
- (ins DREGS
- : $src, DREGS
- : $rr),
- "sbcw\t$rd, $rr", [
- (set i16
- : $rd, (sube i16
- : $src, i16
- : $rr)),
- (implicit SREG)
- ]>;
+ def SBCWRdRr : Pseudo<(outs DREGS:$rd), (ins DREGS:$rs, DREGS:$rr),
+ "sbcw\t$rd, $rr",
+ [(set i16:$rd, (sube i16:$rs, i16:$rr)),
+ (implicit SREG)]>;
- def SBCIRdK
- : FRdK<0b0100,
- (outs LD8
- : $rd),
- (ins LD8
- : $src, imm_ldi8
- : $k),
- "sbci\t$rd, $k",
- [(set i8
- : $rd, (sube i8
- : $src, imm
- : $k)),
- (implicit SREG)]>;
+ def SBCIRdK : FRdK<0b0100, (outs LD8:$rd), (ins LD8:$rs, imm_ldi8:$k),
+ "sbci\t$rd, $k",
+ [(set i8:$rd, (sube i8:$rs, imm:$k)), (implicit SREG)]>;
// SBCIW Rd+1:Rd, K+1:K
// sbci Rd, K
// sbci Rd+1, K+1
- def SBCIWRdK : Pseudo<(outs DLDREGS
- : $rd),
- (ins DLDREGS
- : $src, i16imm
- : $rr),
- "sbciw\t$rd, $rr", [
- (set i16
- : $rd, (sube i16
- : $src, imm
- : $rr)),
- (implicit SREG)
- ]>;
+ def SBCIWRdK : Pseudo<(outs DLDREGS:$rd), (ins DLDREGS:$rs, i16imm:$rr),
+ "sbciw\t$rd, $rr",
+ [(set i16:$rd, (sube i16:$rs, imm:$rr)),
+ (implicit SREG)]>;
}
}
@@ -615,27 +482,13 @@ let Constraints = "$src = $rd", Defs = [SREG] in {
// Increment and Decrement
//===----------------------------------------------------------------------===//
let Constraints = "$src = $rd", Defs = [SREG] in {
- def INCRd
- : FRd<0b1001, 0b0100011,
- (outs GPR8
- : $rd),
- (ins GPR8
- : $src),
- "inc\t$rd", [(set i8
- : $rd, (add i8
- : $src, 1)),
- (implicit SREG)]>;
+ def INCRd : FRd<0b1001, 0b0100011, (outs GPR8:$rd), (ins GPR8:$src),
+ "inc\t$rd",
+ [(set i8:$rd, (add i8:$src, 1)), (implicit SREG)]>;
- def DECRd
- : FRd<0b1001, 0b0101010,
- (outs GPR8
- : $rd),
- (ins GPR8
- : $src),
- "dec\t$rd", [(set i8
- : $rd, (add i8
- : $src, -1)),
- (implicit SREG)]>;
+ def DECRd : FRd<0b1001, 0b0101010, (outs GPR8:$rd), (ins GPR8:$src),
+ "dec\t$rd",
+ [(set i8:$rd, (add i8:$src, -1)), (implicit SREG)]>;
}
//===----------------------------------------------------------------------===//
@@ -646,58 +499,35 @@ let isCommutable = 1, Defs = [R1, R0, SREG] in {
// MUL Rd, Rr
// Multiplies Rd by Rr and places the result into R1:R0.
let usesCustomInserter = 1 in {
- def MULRdRr : FRdRr<0b1001, 0b11, (outs),
- (ins GPR8
- : $rd, GPR8
- : $rr),
- "mul\t$rd, $rr",
- [/*(set R1, R0, (smullohi i8:$rd, i8:$rr))*/]>,
+ def MULRdRr : FRdRr<0b1001, 0b11, (outs), (ins GPR8:$rd, GPR8:$rr),
+ "mul\t$rd, $rr", []>,
Requires<[SupportsMultiplication]>;
- def MULSRdRr : FMUL2RdRr<0, (outs),
- (ins LD8
- : $rd, LD8
- : $rr),
+ def MULSRdRr : FMUL2RdRr<0, (outs), (ins LD8:$rd, LD8:$rr),
"muls\t$rd, $rr", []>,
Requires<[SupportsMultiplication]>;
}
- def MULSURdRr : FMUL2RdRr<1, (outs),
- (ins LD8lo
- : $rd, LD8lo
- : $rr),
+ def MULSURdRr : FMUL2RdRr<1, (outs), (ins LD8lo:$rd, LD8lo:$rr),
"mulsu\t$rd, $rr", []>,
Requires<[SupportsMultiplication]>;
- def FMUL : FFMULRdRr<0b01, (outs),
- (ins LD8lo
- : $rd, LD8lo
- : $rr),
+ def FMUL : FFMULRdRr<0b01, (outs), (ins LD8lo:$rd, LD8lo:$rr),
"fmul\t$rd, $rr", []>,
Requires<[SupportsMultiplication]>;
- def FMULS : FFMULRdRr<0b10, (outs),
- (ins LD8lo
- : $rd, LD8lo
- : $rr),
+ def FMULS : FFMULRdRr<0b10, (outs), (ins LD8lo:$rd, LD8lo:$rr),
"fmuls\t$rd, $rr", []>,
Requires<[SupportsMultiplication]>;
- def FMULSU : FFMULRdRr<0b11, (outs),
- (ins LD8lo
- : $rd, LD8lo
- : $rr),
+ def FMULSU : FFMULRdRr<0b11, (outs), (ins LD8lo:$rd, LD8lo:$rr),
"fmulsu\t$rd, $rr", []>,
Requires<[SupportsMultiplication]>;
}
let Defs =
- [R15, R14, R13, R12, R11, R10, R9, R8, R7, R6, R5, R4, R3, R2, R1,
- R0] in def DESK : FDES<(outs),
- (ins i8imm
- : $k),
- "des\t$k", []>,
- Requires<[HasDES]>;
+ [R15, R14, R13, R12, R11, R10, R9, R8, R7, R6, R5, R4, R3, R2, R1, R0] in
+def DESK : FDES<(outs), (ins i8imm:$k), "des\t$k", []>, Requires<[HasDES]>;
//===----------------------------------------------------------------------===//
// Logic
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