[llvm] [X86][MC] Support enc/dec for IMULZU. (PR #86653)
Freddy Ye via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 28 21:18:49 PDT 2024
https://github.com/FreddyLeaf updated https://github.com/llvm/llvm-project/pull/86653
>From c77fc1a3afd24e20b4dab1be825b7cbbf08f37bc Mon Sep 17 00:00:00 2001
From: Freddy Ye <freddy.ye at intel.com>
Date: Tue, 26 Mar 2024 17:06:39 +0800
Subject: [PATCH 1/3] [X86][MC] Support enc/dec for IMULZU.
apx-spec: https://cdrdv2.intel.com/v1/dl/getContent/784266
apx-syntax-recommendation: https://cdrdv2.intel.com/v1/dl/getContent/817241
---
llvm/lib/Target/X86/X86InstrArithmetic.td | 48 +++++++++++++++++++
llvm/test/MC/Disassembler/X86/apx/imulzu.txt | 50 ++++++++++++++++++++
llvm/test/MC/X86/apx/imulzu-att.s | 38 +++++++++++++++
llvm/test/MC/X86/apx/imulzu-intel.s | 38 +++++++++++++++
llvm/test/TableGen/x86-fold-tables.inc | 6 +++
5 files changed, 180 insertions(+)
create mode 100644 llvm/test/MC/Disassembler/X86/apx/imulzu.txt
create mode 100644 llvm/test/MC/X86/apx/imulzu-att.s
create mode 100644 llvm/test/MC/X86/apx/imulzu-intel.s
diff --git a/llvm/lib/Target/X86/X86InstrArithmetic.td b/llvm/lib/Target/X86/X86InstrArithmetic.td
index fef0a5a90cd6f0..0ec991dfe34ddd 100644
--- a/llvm/lib/Target/X86/X86InstrArithmetic.td
+++ b/llvm/lib/Target/X86/X86InstrArithmetic.td
@@ -334,6 +334,54 @@ let Predicates = [In64BitMode] in {
def IMUL32rmi_EVEX : IMulOpMI_RF<Xi32, WriteIMul32Imm>, PL;
def IMUL64rmi32_EVEX : IMulOpMI_RF<Xi64, WriteIMul64Imm>, PL;
}
+
+// IMULZU instructions
+let Defs = [EFLAGS], ForceDisassemble = 1, OpEnc = EncEVEX, hasSideEffects = 0,
+ Predicates = [HasEGPR, In64BitMode] in {
+ let SchedRW = [WriteIMul16Imm] in {
+ def IMULZU16rri8 : BinOpRI8<0x6B, "imulzu", binop_ndd_args, Xi16, MRMSrcReg,
+ (outs GR16:$dst)>, T_MAP4, PD, EVEX_B;
+ let Opcode = 0x6B, mayLoad = 1 in {
+ def IMULZU16rmi8 : BinOpMI8<"imulzu", binop_ndd_args, Xi16, MRMSrcMem,
+ (outs GR16:$dst)>, T_MAP4, PD, EVEX_B;
+ }
+ def IMULZU16rri : BinOpRI<0x69, "imulzu", binop_ndd_args, Xi16, MRMSrcReg,
+ (outs GR16:$dst), []>, T_MAP4, PD, EVEX_B;
+ let mayLoad = 1 in {
+ def IMULZU16rmi : BinOpMI<0x69, "imulzu", binop_ndd_args, Xi16, MRMSrcMem,
+ (outs GR16:$dst), []>, T_MAP4, PD, EVEX_B;
+ }
+ }
+ let SchedRW = [WriteIMul32Imm] in {
+ def IMULZU32rri8 : BinOpRI8<0x6B, "imulzu", binop_ndd_args, Xi32, MRMSrcReg,
+ (outs GR32:$dst)>, T_MAP4, PS, EVEX_B;
+ let Opcode = 0x6B, mayLoad = 1 in {
+ def IMULZU32rmi8 : BinOpMI8<"imulzu", binop_ndd_args, Xi32, MRMSrcMem,
+ (outs GR32:$dst)>, T_MAP4, PS, EVEX_B;
+ }
+ def IMULZU32rri : BinOpRI<0x69, "imulzu", binop_ndd_args, Xi32, MRMSrcReg,
+ (outs GR32:$dst), []>, T_MAP4, PS, EVEX_B;
+ let mayLoad = 1 in {
+ def IMULZU32rmi : BinOpMI<0x69, "imulzu", binop_ndd_args, Xi32, MRMSrcMem,
+ (outs GR32:$dst), []>, T_MAP4, PS, EVEX_B;
+ }
+ }
+ let SchedRW = [WriteIMul64Imm] in {
+ def IMULZU64rri8 : BinOpRI8<0x6B, "imulzu", binop_ndd_args, Xi64, MRMSrcReg,
+ (outs GR64:$dst)>, T_MAP4, PS, EVEX_B, REX_W;
+ let Opcode = 0x6B, mayLoad = 1 in {
+ def IMULZU64rmi8 : BinOpMI8<"imulzu", binop_ndd_args, Xi64, MRMSrcMem,
+ (outs GR64:$dst)>, T_MAP4, PS, EVEX_B, REX_W;
+ }
+ def IMULZU64rri32 : BinOpRI<0x69, "imulzu", binop_ndd_args, Xi64, MRMSrcReg,
+ (outs GR64:$dst), []>, T_MAP4, PS, EVEX_B, REX_W;
+ let mayLoad = 1 in {
+ def IMULZU64rmi32 : BinOpMI<0x69, "imulzu", binop_ndd_args, Xi64, MRMSrcMem,
+ (outs GR64:$dst), []>, T_MAP4, PS, EVEX_B, REX_W;
+ }
+ }
+}
+
//===----------------------------------------------------------------------===//
// INC and DEC Instructions
//
diff --git a/llvm/test/MC/Disassembler/X86/apx/imulzu.txt b/llvm/test/MC/Disassembler/X86/apx/imulzu.txt
new file mode 100644
index 00000000000000..86142e0540970b
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/imulzu.txt
@@ -0,0 +1,50 @@
+# RUN: llvm-mc -triple x86_64 -disassemble %s | FileCheck %s --check-prefix=ATT
+# RUN: llvm-mc -triple x86_64 -disassemble -output-asm-variant=1 %s | FileCheck %s --check-prefix=INTEL
+
+# ATT: imulzuw $123, %dx, %dx
+# INTEL: imulzu dx, dx, 123
+0x62,0xf4,0x7d,0x18,0x6b,0xd2,0x7b
+
+# ATT: imulzul $123, %ecx, %ecx
+# INTEL: imulzu ecx, ecx, 123
+0x62,0xf4,0x7c,0x18,0x6b,0xc9,0x7b
+
+# ATT: imulzuq $123, %r9, %r9
+# INTEL: imulzu r9, r9, 123
+0x62,0x54,0xfc,0x18,0x6b,0xc9,0x7b
+
+# ATT: imulzuw $123, 291(%r8,%rax,4), %dx
+# INTEL: imulzu dx, word ptr [r8 + 4*rax + 291], 123
+0x62,0xd4,0x7d,0x18,0x6b,0x94,0x80,0x23,0x01,0x00,0x00,0x7b
+
+# ATT: imulzul $123, 291(%r8,%rax,4), %ecx
+# INTEL: imulzu ecx, dword ptr [r8 + 4*rax + 291], 123
+0x62,0xd4,0x7c,0x18,0x6b,0x8c,0x80,0x23,0x01,0x00,0x00,0x7b
+
+# ATT: imulzuq $123, 291(%r8,%rax,4), %r9
+# INTEL: imulzu r9, qword ptr [r8 + 4*rax + 291], 123
+0x62,0x54,0xfc,0x18,0x6b,0x8c,0x80,0x23,0x01,0x00,0x00,0x7b
+
+# ATT: imulzuw $1234, %dx, %dx
+# INTEL: imulzu dx, dx, 1234
+0x62,0xf4,0x7d,0x18,0x69,0xd2,0xd2,0x04
+
+# ATT: imulzuw $1234, 291(%r8,%rax,4), %dx
+# INTEL: imulzu dx, word ptr [r8 + 4*rax + 291], 1234
+0x62,0xd4,0x7d,0x18,0x69,0x94,0x80,0x23,0x01,0x00,0x00,0xd2,0x04
+
+# ATT: imulzul $123456, %ecx, %ecx
+# INTEL: imulzu ecx, ecx, 123456
+0x62,0xf4,0x7c,0x18,0x69,0xc9,0x40,0xe2,0x01,0x00
+
+# ATT: imulzuq $123456, %r9, %r9
+# INTEL: imulzu r9, r9, 123456
+0x62,0x54,0xfc,0x18,0x69,0xc9,0x40,0xe2,0x01,0x00
+
+# ATT: imulzul $123456, 291(%r8,%rax,4), %ecx
+# INTEL: imulzu ecx, dword ptr [r8 + 4*rax + 291], 123456
+0x62,0xd4,0x7c,0x18,0x69,0x8c,0x80,0x23,0x01,0x00,0x00,0x40,0xe2,0x01,0x00
+
+# ATT: imulzuq $123456, 291(%r8,%rax,4), %r9
+# INTEL: imulzu r9, qword ptr [r8 + 4*rax + 291], 123456
+0x62,0x54,0xfc,0x18,0x69,0x8c,0x80,0x23,0x01,0x00,0x00,0x40,0xe2,0x01,0x00
diff --git a/llvm/test/MC/X86/apx/imulzu-att.s b/llvm/test/MC/X86/apx/imulzu-att.s
new file mode 100644
index 00000000000000..52bd6b12167d55
--- /dev/null
+++ b/llvm/test/MC/X86/apx/imulzu-att.s
@@ -0,0 +1,38 @@
+# RUN: llvm-mc -triple x86_64 -show-encoding %s | FileCheck %s
+
+# CHECK: imulzuw $123, %dx, %dx
+# CHECK: encoding: [0x62,0xf4,0x7d,0x18,0x6b,0xd2,0x7b]
+ imulzuw $123, %dx, %dx
+# CHECK: imulzul $123, %ecx, %ecx
+# CHECK: encoding: [0x62,0xf4,0x7c,0x18,0x6b,0xc9,0x7b]
+ imulzul $123, %ecx, %ecx
+# CHECK: imulzuq $123, %r9, %r9
+# CHECK: encoding: [0x62,0x54,0xfc,0x18,0x6b,0xc9,0x7b]
+ imulzuq $123, %r9, %r9
+# CHECK: imulzuw $123, 291(%r8,%rax,4), %dx
+# CHECK: encoding: [0x62,0xd4,0x7d,0x18,0x6b,0x94,0x80,0x23,0x01,0x00,0x00,0x7b]
+ imulzuw $123, 291(%r8,%rax,4), %dx
+# CHECK: imulzul $123, 291(%r8,%rax,4), %ecx
+# CHECK: encoding: [0x62,0xd4,0x7c,0x18,0x6b,0x8c,0x80,0x23,0x01,0x00,0x00,0x7b]
+ imulzul $123, 291(%r8,%rax,4), %ecx
+# CHECK: imulzuq $123, 291(%r8,%rax,4), %r9
+# CHECK: encoding: [0x62,0x54,0xfc,0x18,0x6b,0x8c,0x80,0x23,0x01,0x00,0x00,0x7b]
+ imulzuq $123, 291(%r8,%rax,4), %r9
+# CHECK: imulzuw $1234, %dx, %dx
+# CHECK: encoding: [0x62,0xf4,0x7d,0x18,0x69,0xd2,0xd2,0x04]
+ imulzuw $1234, %dx, %dx
+# CHECK: imulzuw $1234, 291(%r8,%rax,4), %dx
+# CHECK: encoding: [0x62,0xd4,0x7d,0x18,0x69,0x94,0x80,0x23,0x01,0x00,0x00,0xd2,0x04]
+ imulzuw $1234, 291(%r8,%rax,4), %dx
+# CHECK: imulzul $123456, %ecx, %ecx
+# CHECK: encoding: [0x62,0xf4,0x7c,0x18,0x69,0xc9,0x40,0xe2,0x01,0x00]
+ imulzul $123456, %ecx, %ecx
+# CHECK: imulzuq $123456, %r9, %r9
+# CHECK: encoding: [0x62,0x54,0xfc,0x18,0x69,0xc9,0x40,0xe2,0x01,0x00]
+ imulzuq $123456, %r9, %r9
+# CHECK: imulzul $123456, 291(%r8,%rax,4), %ecx
+# CHECK: encoding: [0x62,0xd4,0x7c,0x18,0x69,0x8c,0x80,0x23,0x01,0x00,0x00,0x40,0xe2,0x01,0x00]
+ imulzul $123456, 291(%r8,%rax,4), %ecx
+# CHECK: imulzuq $123456, 291(%r8,%rax,4), %r9
+# CHECK: encoding: [0x62,0x54,0xfc,0x18,0x69,0x8c,0x80,0x23,0x01,0x00,0x00,0x40,0xe2,0x01,0x00]
+ imulzuq $123456, 291(%r8,%rax,4), %r9
diff --git a/llvm/test/MC/X86/apx/imulzu-intel.s b/llvm/test/MC/X86/apx/imulzu-intel.s
new file mode 100644
index 00000000000000..3a01fdca148950
--- /dev/null
+++ b/llvm/test/MC/X86/apx/imulzu-intel.s
@@ -0,0 +1,38 @@
+# RUN: llvm-mc -triple x86_64 -show-encoding -x86-asm-syntax=intel -output-asm-variant=1 %s | FileCheck %s
+
+# CHECK: imulzu dx, dx, 123
+# CHECK: encoding: [0x62,0xf4,0x7d,0x18,0x6b,0xd2,0x7b]
+ imulzu dx, dx, 123
+# CHECK: imulzu ecx, ecx, 123
+# CHECK: encoding: [0x62,0xf4,0x7c,0x18,0x6b,0xc9,0x7b]
+ imulzu ecx, ecx, 123
+# CHECK: imulzu r9, r9, 123
+# CHECK: encoding: [0x62,0x54,0xfc,0x18,0x6b,0xc9,0x7b]
+ imulzu r9, r9, 123
+# CHECK: imulzu dx, word ptr [r8 + 4*rax + 291], 123
+# CHECK: encoding: [0x62,0xd4,0x7d,0x18,0x6b,0x94,0x80,0x23,0x01,0x00,0x00,0x7b]
+ imulzu dx, word ptr [r8 + 4*rax + 291], 123
+# CHECK: imulzu ecx, dword ptr [r8 + 4*rax + 291], 123
+# CHECK: encoding: [0x62,0xd4,0x7c,0x18,0x6b,0x8c,0x80,0x23,0x01,0x00,0x00,0x7b]
+ imulzu ecx, dword ptr [r8 + 4*rax + 291], 123
+# CHECK: imulzu r9, qword ptr [r8 + 4*rax + 291], 123
+# CHECK: encoding: [0x62,0x54,0xfc,0x18,0x6b,0x8c,0x80,0x23,0x01,0x00,0x00,0x7b]
+ imulzu r9, qword ptr [r8 + 4*rax + 291], 123
+# CHECK: imulzu dx, dx, 1234
+# CHECK: encoding: [0x62,0xf4,0x7d,0x18,0x69,0xd2,0xd2,0x04]
+ imulzu dx, dx, 1234
+# CHECK: imulzu dx, word ptr [r8 + 4*rax + 291], 1234
+# CHECK: encoding: [0x62,0xd4,0x7d,0x18,0x69,0x94,0x80,0x23,0x01,0x00,0x00,0xd2,0x04]
+ imulzu dx, word ptr [r8 + 4*rax + 291], 1234
+# CHECK: imulzu ecx, ecx, 123456
+# CHECK: encoding: [0x62,0xf4,0x7c,0x18,0x69,0xc9,0x40,0xe2,0x01,0x00]
+ imulzu ecx, ecx, 123456
+# CHECK: imulzu r9, r9, 123456
+# CHECK: encoding: [0x62,0x54,0xfc,0x18,0x69,0xc9,0x40,0xe2,0x01,0x00]
+ imulzu r9, r9, 123456
+# CHECK: imulzu ecx, dword ptr [r8 + 4*rax + 291], 123456
+# CHECK: encoding: [0x62,0xd4,0x7c,0x18,0x69,0x8c,0x80,0x23,0x01,0x00,0x00,0x40,0xe2,0x01,0x00]
+ imulzu ecx, dword ptr [r8 + 4*rax + 291], 123456
+# CHECK: imulzu r9, qword ptr [r8 + 4*rax + 291], 123456
+# CHECK: encoding: [0x62,0x54,0xfc,0x18,0x69,0x8c,0x80,0x23,0x01,0x00,0x00,0x40,0xe2,0x01,0x00]
+ imulzu r9, qword ptr [r8 + 4*rax + 291], 123456
diff --git a/llvm/test/TableGen/x86-fold-tables.inc b/llvm/test/TableGen/x86-fold-tables.inc
index 7b65e483c39d0d..4ab5567f628763 100644
--- a/llvm/test/TableGen/x86-fold-tables.inc
+++ b/llvm/test/TableGen/x86-fold-tables.inc
@@ -756,6 +756,12 @@ static const X86FoldTableEntry Table1[] = {
{X86::IMUL64rri32_NF, X86::IMUL64rmi32_NF, 0},
{X86::IMUL64rri8, X86::IMUL64rmi8, 0},
{X86::IMUL64rri8_NF, X86::IMUL64rmi8_NF, 0},
+ {X86::IMULZU16rri, X86::IMULZU16rmi, 0},
+ {X86::IMULZU16rri8, X86::IMULZU16rmi8, 0},
+ {X86::IMULZU32rri, X86::IMULZU32rmi, 0},
+ {X86::IMULZU32rri8, X86::IMULZU32rmi8, 0},
+ {X86::IMULZU64rri32, X86::IMULZU64rmi32, 0},
+ {X86::IMULZU64rri8, X86::IMULZU64rmi8, 0},
{X86::INC16r_ND, X86::INC16m_ND, 0},
{X86::INC16r_NF_ND, X86::INC16m_NF_ND, 0},
{X86::INC32r_ND, X86::INC32m_ND, 0},
>From ed49ecd8e677d4659640b4db89ddd04f13cc4732 Mon Sep 17 00:00:00 2001
From: Freddy Ye <freddy.ye at intel.com>
Date: Thu, 28 Mar 2024 15:17:11 +0800
Subject: [PATCH 2/3] address comments.
---
llvm/lib/Target/X86/X86InstrArithmetic.td | 74 ++++++++++++-----------
llvm/test/MC/X86/apx/imulzu-att.s | 3 +
2 files changed, 41 insertions(+), 36 deletions(-)
diff --git a/llvm/lib/Target/X86/X86InstrArithmetic.td b/llvm/lib/Target/X86/X86InstrArithmetic.td
index 0ec991dfe34ddd..0ca508619a2845 100644
--- a/llvm/lib/Target/X86/X86InstrArithmetic.td
+++ b/llvm/lib/Target/X86/X86InstrArithmetic.td
@@ -339,46 +339,48 @@ let Predicates = [In64BitMode] in {
let Defs = [EFLAGS], ForceDisassemble = 1, OpEnc = EncEVEX, hasSideEffects = 0,
Predicates = [HasEGPR, In64BitMode] in {
let SchedRW = [WriteIMul16Imm] in {
- def IMULZU16rri8 : BinOpRI8<0x6B, "imulzu", binop_ndd_args, Xi16, MRMSrcReg,
- (outs GR16:$dst)>, T_MAP4, PD, EVEX_B;
- let Opcode = 0x6B, mayLoad = 1 in {
- def IMULZU16rmi8 : BinOpMI8<"imulzu", binop_ndd_args, Xi16, MRMSrcMem,
- (outs GR16:$dst)>, T_MAP4, PD, EVEX_B;
- }
- def IMULZU16rri : BinOpRI<0x69, "imulzu", binop_ndd_args, Xi16, MRMSrcReg,
- (outs GR16:$dst), []>, T_MAP4, PD, EVEX_B;
- let mayLoad = 1 in {
- def IMULZU16rmi : BinOpMI<0x69, "imulzu", binop_ndd_args, Xi16, MRMSrcMem,
- (outs GR16:$dst), []>, T_MAP4, PD, EVEX_B;
- }
+ def IMULZU16rri8 : BinOpRI8<0x6B, "imulzu", binop_ndd_args, Xi16, MRMSrcReg,
+ (outs GR16:$dst)>, T_MAP4, PD, EVEX_B;
+ def IMULZU16rri : BinOpRI<0x69, "imulzu", binop_ndd_args, Xi16, MRMSrcReg,
+ (outs GR16:$dst), []>, T_MAP4, PD, EVEX_B;
+ let mayLoad = 1 in {
+ def IMULZU16rmi : BinOpMI<0x69, "imulzu", binop_ndd_args, Xi16, MRMSrcMem,
+ (outs GR16:$dst), []>, T_MAP4, PD, EVEX_B;
+ let Opcode = 0x6B in {
+ def IMULZU16rmi8 : BinOpMI8<"imulzu", binop_ndd_args, Xi16, MRMSrcMem,
+ (outs GR16:$dst)>, T_MAP4, PD, EVEX_B;
+ }
+ }
}
+
let SchedRW = [WriteIMul32Imm] in {
- def IMULZU32rri8 : BinOpRI8<0x6B, "imulzu", binop_ndd_args, Xi32, MRMSrcReg,
- (outs GR32:$dst)>, T_MAP4, PS, EVEX_B;
- let Opcode = 0x6B, mayLoad = 1 in {
- def IMULZU32rmi8 : BinOpMI8<"imulzu", binop_ndd_args, Xi32, MRMSrcMem,
- (outs GR32:$dst)>, T_MAP4, PS, EVEX_B;
- }
- def IMULZU32rri : BinOpRI<0x69, "imulzu", binop_ndd_args, Xi32, MRMSrcReg,
- (outs GR32:$dst), []>, T_MAP4, PS, EVEX_B;
- let mayLoad = 1 in {
- def IMULZU32rmi : BinOpMI<0x69, "imulzu", binop_ndd_args, Xi32, MRMSrcMem,
- (outs GR32:$dst), []>, T_MAP4, PS, EVEX_B;
- }
+ def IMULZU32rri8 : BinOpRI8<0x6B, "imulzu", binop_ndd_args, Xi32, MRMSrcReg,
+ (outs GR32:$dst)>, T_MAP4, PS, EVEX_B;
+ def IMULZU32rri : BinOpRI<0x69, "imulzu", binop_ndd_args, Xi32, MRMSrcReg,
+ (outs GR32:$dst), []>, T_MAP4, PS, EVEX_B;
+ let mayLoad = 1 in {
+ def IMULZU32rmi : BinOpMI<0x69, "imulzu", binop_ndd_args, Xi32, MRMSrcMem,
+ (outs GR32:$dst), []>, T_MAP4, PS, EVEX_B;
+ let Opcode = 0x6B in {
+ def IMULZU32rmi8 : BinOpMI8<"imulzu", binop_ndd_args, Xi32, MRMSrcMem,
+ (outs GR32:$dst)>, T_MAP4, PS, EVEX_B;
+ }
+ }
}
+
let SchedRW = [WriteIMul64Imm] in {
- def IMULZU64rri8 : BinOpRI8<0x6B, "imulzu", binop_ndd_args, Xi64, MRMSrcReg,
- (outs GR64:$dst)>, T_MAP4, PS, EVEX_B, REX_W;
- let Opcode = 0x6B, mayLoad = 1 in {
- def IMULZU64rmi8 : BinOpMI8<"imulzu", binop_ndd_args, Xi64, MRMSrcMem,
- (outs GR64:$dst)>, T_MAP4, PS, EVEX_B, REX_W;
- }
- def IMULZU64rri32 : BinOpRI<0x69, "imulzu", binop_ndd_args, Xi64, MRMSrcReg,
- (outs GR64:$dst), []>, T_MAP4, PS, EVEX_B, REX_W;
- let mayLoad = 1 in {
- def IMULZU64rmi32 : BinOpMI<0x69, "imulzu", binop_ndd_args, Xi64, MRMSrcMem,
- (outs GR64:$dst), []>, T_MAP4, PS, EVEX_B, REX_W;
- }
+ def IMULZU64rri8 : BinOpRI8<0x6B, "imulzu", binop_ndd_args, Xi64, MRMSrcReg,
+ (outs GR64:$dst)>, T_MAP4, PS, EVEX_B;
+ def IMULZU64rri32 : BinOpRI<0x69, "imulzu", binop_ndd_args, Xi64, MRMSrcReg,
+ (outs GR64:$dst), []>, T_MAP4, PS, EVEX_B;
+ let mayLoad = 1 in {
+ def IMULZU64rmi32 : BinOpMI<0x69, "imulzu", binop_ndd_args, Xi64, MRMSrcMem,
+ (outs GR64:$dst), []>, T_MAP4, PS, EVEX_B;
+ let Opcode = 0x6B in {
+ def IMULZU64rmi8 : BinOpMI8<"imulzu", binop_ndd_args, Xi64, MRMSrcMem,
+ (outs GR64:$dst)>, T_MAP4, PS, EVEX_B;
+ }
+ }
}
}
diff --git a/llvm/test/MC/X86/apx/imulzu-att.s b/llvm/test/MC/X86/apx/imulzu-att.s
index 52bd6b12167d55..f56bfa77e1ce28 100644
--- a/llvm/test/MC/X86/apx/imulzu-att.s
+++ b/llvm/test/MC/X86/apx/imulzu-att.s
@@ -1,5 +1,8 @@
# RUN: llvm-mc -triple x86_64 -show-encoding %s | FileCheck %s
+# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
+# ERROR-COUNT-12: error:
+# ERROR-NOT: error:
# CHECK: imulzuw $123, %dx, %dx
# CHECK: encoding: [0x62,0xf4,0x7d,0x18,0x6b,0xd2,0x7b]
imulzuw $123, %dx, %dx
>From 3dcdc3db3a176da43455db3b445314570fd0881d Mon Sep 17 00:00:00 2001
From: Freddy Ye <freddy.ye at intel.com>
Date: Fri, 29 Mar 2024 12:18:29 +0800
Subject: [PATCH 3/3] Refactor
---
llvm/lib/Target/X86/X86InstrArithmetic.td | 78 ++++++++++-------------
llvm/lib/Target/X86/X86InstrUtils.td | 2 +
2 files changed, 35 insertions(+), 45 deletions(-)
diff --git a/llvm/lib/Target/X86/X86InstrArithmetic.td b/llvm/lib/Target/X86/X86InstrArithmetic.td
index 0ca508619a2845..c45ec8981ab1fe 100644
--- a/llvm/lib/Target/X86/X86InstrArithmetic.td
+++ b/llvm/lib/Target/X86/X86InstrArithmetic.td
@@ -336,52 +336,40 @@ let Predicates = [In64BitMode] in {
}
// IMULZU instructions
-let Defs = [EFLAGS], ForceDisassemble = 1, OpEnc = EncEVEX, hasSideEffects = 0,
- Predicates = [HasEGPR, In64BitMode] in {
- let SchedRW = [WriteIMul16Imm] in {
- def IMULZU16rri8 : BinOpRI8<0x6B, "imulzu", binop_ndd_args, Xi16, MRMSrcReg,
- (outs GR16:$dst)>, T_MAP4, PD, EVEX_B;
- def IMULZU16rri : BinOpRI<0x69, "imulzu", binop_ndd_args, Xi16, MRMSrcReg,
- (outs GR16:$dst), []>, T_MAP4, PD, EVEX_B;
- let mayLoad = 1 in {
- def IMULZU16rmi : BinOpMI<0x69, "imulzu", binop_ndd_args, Xi16, MRMSrcMem,
- (outs GR16:$dst), []>, T_MAP4, PD, EVEX_B;
- let Opcode = 0x6B in {
- def IMULZU16rmi8 : BinOpMI8<"imulzu", binop_ndd_args, Xi16, MRMSrcMem,
- (outs GR16:$dst)>, T_MAP4, PD, EVEX_B;
- }
- }
- }
-
- let SchedRW = [WriteIMul32Imm] in {
- def IMULZU32rri8 : BinOpRI8<0x6B, "imulzu", binop_ndd_args, Xi32, MRMSrcReg,
- (outs GR32:$dst)>, T_MAP4, PS, EVEX_B;
- def IMULZU32rri : BinOpRI<0x69, "imulzu", binop_ndd_args, Xi32, MRMSrcReg,
- (outs GR32:$dst), []>, T_MAP4, PS, EVEX_B;
- let mayLoad = 1 in {
- def IMULZU32rmi : BinOpMI<0x69, "imulzu", binop_ndd_args, Xi32, MRMSrcMem,
- (outs GR32:$dst), []>, T_MAP4, PS, EVEX_B;
- let Opcode = 0x6B in {
- def IMULZU32rmi8 : BinOpMI8<"imulzu", binop_ndd_args, Xi32, MRMSrcMem,
- (outs GR32:$dst)>, T_MAP4, PS, EVEX_B;
- }
- }
- }
+class IMulZUOpRI8_R<X86TypeInfo t, X86FoldableSchedWrite sched>
+ : BinOpRI8<0x6B, "imulzu", binop_ndd_args, t, MRMSrcReg,
+ (outs t.RegClass:$dst)> {
+ let SchedRW = [sched];
+}
+class IMulZUOpRI_R<X86TypeInfo t, X86FoldableSchedWrite sched>
+ : BinOpRI<0x69, "imulzu", binop_ndd_args, t, MRMSrcReg,
+ (outs t.RegClass:$dst), []> {
+ let SchedRW = [sched];
+}
+class IMulZUOpMI8_R<X86TypeInfo t, X86FoldableSchedWrite sched>
+ : BinOpMI8<"imulzu", binop_ndd_args, t, MRMSrcMem, (outs t.RegClass:$dst)> {
+ let Opcode = 0x6B;
+ let SchedRW = [sched.Folded];
+}
+class IMulZUOpMI_R<X86TypeInfo t, X86FoldableSchedWrite sched>
+ : BinOpMI<0x69, "imulzu", binop_ndd_args, t, MRMSrcMem,
+ (outs t.RegClass:$dst), []> {
+ let SchedRW = [sched.Folded];
+}
- let SchedRW = [WriteIMul64Imm] in {
- def IMULZU64rri8 : BinOpRI8<0x6B, "imulzu", binop_ndd_args, Xi64, MRMSrcReg,
- (outs GR64:$dst)>, T_MAP4, PS, EVEX_B;
- def IMULZU64rri32 : BinOpRI<0x69, "imulzu", binop_ndd_args, Xi64, MRMSrcReg,
- (outs GR64:$dst), []>, T_MAP4, PS, EVEX_B;
- let mayLoad = 1 in {
- def IMULZU64rmi32 : BinOpMI<0x69, "imulzu", binop_ndd_args, Xi64, MRMSrcMem,
- (outs GR64:$dst), []>, T_MAP4, PS, EVEX_B;
- let Opcode = 0x6B in {
- def IMULZU64rmi8 : BinOpMI8<"imulzu", binop_ndd_args, Xi64, MRMSrcMem,
- (outs GR64:$dst)>, T_MAP4, PS, EVEX_B;
- }
- }
- }
+let Defs = [EFLAGS], Predicates = [HasEGPR, In64BitMode] in {
+ def IMULZU16rri8 : IMulZUOpRI8_R<Xi16, WriteIMul16Imm>, ZU, PD;
+ def IMULZU16rmi8 : IMulZUOpMI8_R<Xi16, WriteIMul16Imm>, ZU, PD;
+ def IMULZU16rri : IMulZUOpRI_R<Xi16, WriteIMul16Imm>, ZU, PD;
+ def IMULZU16rmi : IMulZUOpMI_R<Xi16, WriteIMul16Imm>, ZU, PD;
+ def IMULZU32rri8 : IMulZUOpRI8_R<Xi32, WriteIMul32Imm>, ZU;
+ def IMULZU32rmi8 : IMulZUOpMI8_R<Xi32, WriteIMul32Imm>, ZU;
+ def IMULZU32rri : IMulZUOpRI_R<Xi32, WriteIMul32Imm>, ZU;
+ def IMULZU32rmi : IMulZUOpMI_R<Xi32, WriteIMul32Imm>, ZU;
+ def IMULZU64rri8 : IMulZUOpRI8_R<Xi64, WriteIMul64Imm>, ZU;
+ def IMULZU64rmi8 : IMulZUOpMI8_R<Xi64, WriteIMul64Imm>, ZU;
+ def IMULZU64rri32 : IMulZUOpRI_R<Xi64, WriteIMul64Imm>, ZU;
+ def IMULZU64rmi32 : IMulZUOpMI_R<Xi64, WriteIMul64Imm>, ZU;
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/X86/X86InstrUtils.td b/llvm/lib/Target/X86/X86InstrUtils.td
index 04d9d104ebc4b0..8387b76a40cdda 100644
--- a/llvm/lib/Target/X86/X86InstrUtils.td
+++ b/llvm/lib/Target/X86/X86InstrUtils.td
@@ -119,6 +119,8 @@ class NDD<bit ndd> {
class NF: T_MAP4, EVEX, EVEX_NF;
// PL - Helper for promoted legacy instructions
class PL: T_MAP4, EVEX, ExplicitEVEXPrefix;
+// ZU - Helper for Zero Upper instructions
+class ZU: T_MAP4, EVEX, EVEX_B;
//===----------------------------------------------------------------------===//
// X86 Type infomation definitions
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