[llvm] [PowerPC] Add flag to DAG combiner to improve compile time. (PR #86884)
Stefan Pintilie via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 27 16:24:39 PDT 2024
https://github.com/stefanp-ibm updated https://github.com/llvm/llvm-project/pull/86884
>From 4d71ff9308fdeda7aa3948f5b9ad23d7032f517e Mon Sep 17 00:00:00 2001
From: Stefan Pintilie <stefanp at ca.ibm.com>
Date: Wed, 27 Mar 2024 17:21:59 -0500
Subject: [PATCH 1/3] [PowerPC] Add flag to DAG combiner to improve compile
time.
When combining loads we automatically add any new nodes to the list to be
combined in turn. This has a positive effect on overall performance but a
negative effect on compile time. We have an internal example where compile time
becomes much too long to be acceptable. This option (off by default) disables
the addition of the new nodes.
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 8 +++-
llvm/test/CodeGen/PowerPC/legalize-vaarg.ll | 47 +++++++++++++++++--
2 files changed, 49 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 36abe27d262176..a80b0fdc804ab8 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -150,6 +150,12 @@ static cl::opt<bool> EnableVectorFCopySignExtendRound(
cl::desc(
"Enable merging extends and rounds into FCOPYSIGN on vector types"));
+static cl::opt<bool>
+AddLoadBack("combiner-add-load-back", cl::Hidden,
+ cl::desc("When combining a load are new nodes added back in"),
+ cl::init(true));
+
+
namespace {
class DAGCombiner {
@@ -18808,7 +18814,7 @@ SDValue DAGCombiner::visitLOAD(SDNode *N) {
MVT::Other, Chain, ReplLoad.getValue(1));
// Replace uses with load result and token factor
- return CombineTo(N, ReplLoad.getValue(0), Token);
+ return CombineTo(N, ReplLoad.getValue(0), Token, AddLoadBack);
}
}
diff --git a/llvm/test/CodeGen/PowerPC/legalize-vaarg.ll b/llvm/test/CodeGen/PowerPC/legalize-vaarg.ll
index b7f8b8af2472aa..264da54f8e6149 100644
--- a/llvm/test/CodeGen/PowerPC/legalize-vaarg.ll
+++ b/llvm/test/CodeGen/PowerPC/legalize-vaarg.ll
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
;RUN: llc < %s --mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec | FileCheck %s -check-prefix=BE
;RUN: llc < %s --mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec | FileCheck %s -check-prefix=LE
+;RUN: llc < %s --mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -combiner-add-load-back=false | FileCheck %s -check-prefix=BENOLOAD
+;RUN: llc < %s --mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec -combiner-add-load-back=false | FileCheck %s -check-prefix=LENOLOAD
define <8 x i32> @test_large_vec_vaarg(i32 %n, ...) {
; BE-LABEL: test_large_vec_vaarg:
@@ -9,13 +11,14 @@ define <8 x i32> @test_large_vec_vaarg(i32 %n, ...) {
; BE-NEXT: addi 3, 3, 15
; BE-NEXT: rldicr 3, 3, 0, 59
; BE-NEXT: addi 4, 3, 16
-; BE-NEXT: addi 5, 3, 31
; BE-NEXT: std 4, -8(1)
-; BE-NEXT: rldicr 4, 5, 0, 59
+; BE-NEXT: ld 4, -8(1)
; BE-NEXT: lvx 2, 0, 3
-; BE-NEXT: addi 3, 4, 16
-; BE-NEXT: std 3, -8(1)
-; BE-NEXT: lvx 3, 0, 4
+; BE-NEXT: addi 4, 4, 15
+; BE-NEXT: rldicr 3, 4, 0, 59
+; BE-NEXT: addi 4, 3, 16
+; BE-NEXT: std 4, -8(1)
+; BE-NEXT: lvx 3, 0, 3
; BE-NEXT: blr
;
; LE-LABEL: test_large_vec_vaarg:
@@ -35,6 +38,40 @@ define <8 x i32> @test_large_vec_vaarg(i32 %n, ...) {
; LE-NEXT: lxvd2x 0, 0, 3
; LE-NEXT: xxswapd 35, 0
; LE-NEXT: blr
+;
+; BENOLOAD-LABEL: test_large_vec_vaarg:
+; BENOLOAD: # %bb.0:
+; BENOLOAD-NEXT: ld 3, -8(1)
+; BENOLOAD-NEXT: addi 3, 3, 15
+; BENOLOAD-NEXT: rldicr 3, 3, 0, 59
+; BENOLOAD-NEXT: addi 4, 3, 16
+; BENOLOAD-NEXT: std 4, -8(1)
+; BENOLOAD-NEXT: ld 4, -8(1)
+; BENOLOAD-NEXT: lvx 2, 0, 3
+; BENOLOAD-NEXT: addi 4, 4, 15
+; BENOLOAD-NEXT: rldicr 3, 4, 0, 59
+; BENOLOAD-NEXT: addi 4, 3, 16
+; BENOLOAD-NEXT: std 4, -8(1)
+; BENOLOAD-NEXT: lvx 3, 0, 3
+; BENOLOAD-NEXT: blr
+;
+; LENOLOAD-LABEL: test_large_vec_vaarg:
+; LENOLOAD: # %bb.0:
+; LENOLOAD-NEXT: ld 3, -8(1)
+; LENOLOAD-NEXT: addi 3, 3, 15
+; LENOLOAD-NEXT: rldicr 3, 3, 0, 59
+; LENOLOAD-NEXT: addi 4, 3, 16
+; LENOLOAD-NEXT: std 4, -8(1)
+; LENOLOAD-NEXT: lxvd2x 0, 0, 3
+; LENOLOAD-NEXT: ld 3, -8(1)
+; LENOLOAD-NEXT: addi 3, 3, 15
+; LENOLOAD-NEXT: rldicr 3, 3, 0, 59
+; LENOLOAD-NEXT: addi 4, 3, 16
+; LENOLOAD-NEXT: std 4, -8(1)
+; LENOLOAD-NEXT: xxswapd 34, 0
+; LENOLOAD-NEXT: lxvd2x 0, 0, 3
+; LENOLOAD-NEXT: xxswapd 35, 0
+; LENOLOAD-NEXT: blr
%args = alloca ptr, align 4
%x = va_arg ptr %args, <8 x i32>
ret <8 x i32> %x
>From 84fe3fd9cf4d40212627da0e99dfaf89350cfaea Mon Sep 17 00:00:00 2001
From: Stefan Pintilie <stefanp at ca.ibm.com>
Date: Wed, 27 Mar 2024 18:00:43 -0500
Subject: [PATCH 2/3] Forgot to run git clang format. This fixes the format.
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index a80b0fdc804ab8..f1908233805c31 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -151,10 +151,9 @@ static cl::opt<bool> EnableVectorFCopySignExtendRound(
"Enable merging extends and rounds into FCOPYSIGN on vector types"));
static cl::opt<bool>
-AddLoadBack("combiner-add-load-back", cl::Hidden,
- cl::desc("When combining a load are new nodes added back in"),
- cl::init(true));
-
+ AddLoadBack("combiner-add-load-back", cl::Hidden,
+ cl::desc("When combining a load are new nodes added back in"),
+ cl::init(true));
namespace {
>From b08dba0d39d873fc83101bf09b2a56b3a8d5f442 Mon Sep 17 00:00:00 2001
From: Stefan Pintilie <stefanp at ca.ibm.com>
Date: Wed, 27 Mar 2024 18:24:15 -0500
Subject: [PATCH 3/3] Updated the test case.
---
llvm/test/CodeGen/PowerPC/legalize-vaarg.ll | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/llvm/test/CodeGen/PowerPC/legalize-vaarg.ll b/llvm/test/CodeGen/PowerPC/legalize-vaarg.ll
index 264da54f8e6149..6c5eaf75b288eb 100644
--- a/llvm/test/CodeGen/PowerPC/legalize-vaarg.ll
+++ b/llvm/test/CodeGen/PowerPC/legalize-vaarg.ll
@@ -11,14 +11,13 @@ define <8 x i32> @test_large_vec_vaarg(i32 %n, ...) {
; BE-NEXT: addi 3, 3, 15
; BE-NEXT: rldicr 3, 3, 0, 59
; BE-NEXT: addi 4, 3, 16
+; BE-NEXT: addi 5, 3, 31
; BE-NEXT: std 4, -8(1)
-; BE-NEXT: ld 4, -8(1)
+; BE-NEXT: rldicr 4, 5, 0, 59
; BE-NEXT: lvx 2, 0, 3
-; BE-NEXT: addi 4, 4, 15
-; BE-NEXT: rldicr 3, 4, 0, 59
-; BE-NEXT: addi 4, 3, 16
-; BE-NEXT: std 4, -8(1)
-; BE-NEXT: lvx 3, 0, 3
+; BE-NEXT: addi 3, 4, 16
+; BE-NEXT: std 3, -8(1)
+; BE-NEXT: lvx 3, 0, 4
; BE-NEXT: blr
;
; LE-LABEL: test_large_vec_vaarg:
More information about the llvm-commits
mailing list