[llvm] [RISCV][GISEL] Legalize G_VSCALE (PR #85967)
Michael Maitland via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 26 10:28:31 PDT 2024
https://github.com/michaelmaitland updated https://github.com/llvm/llvm-project/pull/85967
>From 48c7ae53773666c3ce982850666686e5b8bb35d9 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Thu, 7 Mar 2024 13:35:22 -0800
Subject: [PATCH 1/8] [RISCV][GISEL] Legalize G_VSCALE
G_VSCALE should be lowered using VLENB.
---
.../Target/RISCV/GISel/RISCVLegalizerInfo.cpp | 44 +++++++
.../Target/RISCV/GISel/RISCVLegalizerInfo.h | 1 +
llvm/lib/Target/RISCV/RISCVInstrGISel.td | 8 ++
.../legalizer/rvv/legalize-vscale-rv32.mir | 120 ++++++++++++++++++
.../legalizer/rvv/legalize-vscale-rv64.mir | 120 ++++++++++++++++++
5 files changed, 293 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-vscale-rv32.mir
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-vscale-rv64.mir
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index 64ae4e94a8c929..a7829d4819ebd0 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -374,6 +374,8 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
.clampScalar(0, s32, sXLen)
.lowerForCartesianProduct({s32, sXLen, p0}, {p0});
+ getActionDefinitionsBuilder(G_VSCALE).customFor({sXLen});
+
getLegacyLegalizerInfo().computeTables();
}
@@ -495,6 +497,46 @@ bool RISCVLegalizerInfo::shouldBeInConstantPool(APInt APImm,
return !(!SeqLo.empty() && (SeqLo.size() + 2) <= STI.getMaxBuildIntsCost());
}
+bool RISCVLegalizerInfo::legalizeVScale(MachineInstr &MI,
+ MachineIRBuilder &MIB) const {
+ const LLT XLenTy(STI.getXLenVT());
+ Register Dst = MI.getOperand(0).getReg();
+
+ // We define our scalable vector types for lmul=1 to use a 64 bit known
+ // minimum size. e.g. <vscale x 2 x i32>. VLENB is in bytes so we calculate
+ // vscale as VLENB / 8.
+ static_assert(RISCV::RVVBitsPerBlock == 64, "Unexpected bits per block!");
+ if (STI.getRealMinVLen() < RISCV::RVVBitsPerBlock)
+ report_fatal_error("Support for VLEN==32 is incomplete.");
+ // We assume VLENB is a multiple of 8. We manually choose the best shift
+ // here because SimplifyDemandedBits isn't always able to simplify it.
+ uint64_t Val = MI.getOperand(1).getCImm()->getZExtValue();
+ if (isPowerOf2_64(Val)) {
+ uint64_t Log2 = Log2_64(Val);
+ if (Log2 < 3) {
+ auto VLENB = MIB.buildInstr(RISCV::G_READ_VLENB, {XLenTy}, {});
+ MIB.buildLShr(Dst, VLENB, MIB.buildConstant(XLenTy, 3 - Log2));
+ } else if (Log2 > 3) {
+ auto VLENB = MIB.buildInstr(RISCV::G_READ_VLENB, {XLenTy}, {});
+ MIB.buildShl(Dst, VLENB, MIB.buildConstant(XLenTy, Log2 - 3));
+ } else {
+ MIB.buildInstr(RISCV::G_READ_VLENB, {Dst}, {});
+ }
+ } else if ((Val % 8) == 0) {
+ // If the multiplier is a multiple of 8, scale it down to avoid needing
+ // to shift the VLENB value.
+ auto VLENB = MIB.buildInstr(RISCV::G_READ_VLENB, {XLenTy}, {});
+ MIB.buildMul(Dst, VLENB, MIB.buildConstant(XLenTy, Val / 8));
+ } else {
+ auto VLENB = MIB.buildInstr(RISCV::G_READ_VLENB, {XLenTy}, {});
+ auto VScale = MIB.buildLShr(XLenTy, VLENB, MIB.buildConstant(XLenTy, 3));
+ MIB.buildMul(Dst, VScale, MIB.buildConstant(XLenTy, Val));
+ }
+
+ MI.eraseFromParent();
+ return true;
+}
+
bool RISCVLegalizerInfo::legalizeCustom(
LegalizerHelper &Helper, MachineInstr &MI,
LostDebugLocObserver &LocObserver) const {
@@ -552,6 +594,8 @@ bool RISCVLegalizerInfo::legalizeCustom(
}
case TargetOpcode::G_VASTART:
return legalizeVAStart(MI, MIRBuilder);
+ case TargetOpcode::G_VSCALE:
+ return legalizeVScale(MI, MIRBuilder);
}
llvm_unreachable("expected switch to return");
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h
index 323426034827e4..e2a98c8d2c736c 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h
@@ -42,6 +42,7 @@ class RISCVLegalizerInfo : public LegalizerInfo {
GISelChangeObserver &Observer) const;
bool legalizeVAStart(MachineInstr &MI, MachineIRBuilder &MIRBuilder) const;
+ bool legalizeVScale(MachineInstr &MI, MachineIRBuilder &MIB) const;
};
} // end namespace llvm
#endif
diff --git a/llvm/lib/Target/RISCV/RISCVInstrGISel.td b/llvm/lib/Target/RISCV/RISCVInstrGISel.td
index ede8c9809833cc..54e22d6257814a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrGISel.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrGISel.td
@@ -24,3 +24,11 @@ def G_FCLASS : RISCVGenericInstruction {
let hasSideEffects = false;
}
def : GINodeEquiv<G_FCLASS, riscv_fclass>;
+
+// Pseudo equivalent to a RISCVISD::READ_VLENB.
+def G_READ_VLENB : RISCVGenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins);
+ let hasSideEffects = false;
+}
+def : GINodeEquiv<G_READ_VLENB, riscv_read_vlenb>;
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-vscale-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-vscale-rv32.mir
new file mode 100644
index 00000000000000..60fc3c66adec4a
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-vscale-rv32.mir
@@ -0,0 +1,120 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s
+
+---
+name: test_1
+body: |
+ bb.0.entry:
+
+ ; CHECK-LABEL: name: test_1
+ ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = G_VSCALE i32 1
+ $x10 = COPY %0
+ PseudoRET implicit $x10
+...
+---
+name: test_2
+body: |
+ bb.0.entry:
+
+ ; CHECK-LABEL: name: test_2
+ ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = G_VSCALE i32 2
+ $x10 = COPY %0
+ PseudoRET implicit $x10
+...
+---
+name: test_3
+body: |
+ bb.0.entry:
+
+ ; CHECK-LABEL: name: test_3
+ ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
+ ; CHECK-NEXT: $x11 = COPY [[C1]](s32)
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: $x10 = COPY [[COPY]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = G_VSCALE i32 3
+ $x10 = COPY %0
+ PseudoRET implicit $x10
+...
+---
+name: test_4
+body: |
+ bb.0.entry:
+
+ ; CHECK-LABEL: name: test_4
+ ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = G_VSCALE i32 4
+ $x10 = COPY %0
+ PseudoRET implicit $x10
+...
+---
+name: test_8
+body: |
+ bb.0.entry:
+
+ ; CHECK-LABEL: name: test_8
+ ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
+ ; CHECK-NEXT: $x10 = COPY [[READ_VLENB]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = G_VSCALE i32 8
+ $x10 = COPY %0
+ PseudoRET implicit $x10
+...
+---
+name: test_16
+body: |
+ bb.0.entry:
+
+ ; CHECK-LABEL: name: test_16
+ ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[READ_VLENB]], [[C]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[SHL]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = G_VSCALE i32 16
+ $x10 = COPY %0
+ PseudoRET implicit $x10
+...
+---
+name: test_40
+body: |
+ bb.0.entry:
+
+ ; CHECK-LABEL: name: test_40
+ ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[READ_VLENB]](s32)
+ ; CHECK-NEXT: $x11 = COPY [[C]](s32)
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: $x10 = COPY [[COPY]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = G_VSCALE i32 40
+ $x10 = COPY %0
+ PseudoRET implicit $x10
+...
+
+
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-vscale-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-vscale-rv64.mir
new file mode 100644
index 00000000000000..3e140a5ef72a84
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-vscale-rv64.mir
@@ -0,0 +1,120 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s
+
+---
+name: test_1
+body: |
+ bb.0.entry:
+
+ ; CHECK-LABEL: name: test_1
+ ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[READ_VLENB]], [[C]](s64)
+ ; CHECK-NEXT: $x10 = COPY [[LSHR]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = G_VSCALE i64 1
+ $x10 = COPY %0
+ PseudoRET implicit $x10
+...
+---
+name: test_2
+body: |
+ bb.0.entry:
+
+ ; CHECK-LABEL: name: test_2
+ ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[READ_VLENB]], [[C]](s64)
+ ; CHECK-NEXT: $x10 = COPY [[LSHR]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = G_VSCALE i64 2
+ $x10 = COPY %0
+ PseudoRET implicit $x10
+...
+---
+name: test_3
+body: |
+ bb.0.entry:
+
+ ; CHECK-LABEL: name: test_3
+ ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[READ_VLENB]], [[C]](s64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[LSHR]](s64)
+ ; CHECK-NEXT: $x11 = COPY [[C1]](s64)
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; CHECK-NEXT: $x10 = COPY [[COPY]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = G_VSCALE i64 3
+ $x10 = COPY %0
+ PseudoRET implicit $x10
+...
+---
+name: test_4
+body: |
+ bb.0.entry:
+
+ ; CHECK-LABEL: name: test_4
+ ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[READ_VLENB]], [[C]](s64)
+ ; CHECK-NEXT: $x10 = COPY [[LSHR]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = G_VSCALE i64 4
+ $x10 = COPY %0
+ PseudoRET implicit $x10
+...
+---
+name: test_8
+body: |
+ bb.0.entry:
+
+ ; CHECK-LABEL: name: test_8
+ ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB
+ ; CHECK-NEXT: $x10 = COPY [[READ_VLENB]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = G_VSCALE i64 8
+ $x10 = COPY %0
+ PseudoRET implicit $x10
+...
+---
+name: test_16
+body: |
+ bb.0.entry:
+
+ ; CHECK-LABEL: name: test_16
+ ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[READ_VLENB]], [[C]](s64)
+ ; CHECK-NEXT: $x10 = COPY [[SHL]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = G_VSCALE i64 16
+ $x10 = COPY %0
+ PseudoRET implicit $x10
+...
+---
+name: test_40
+body: |
+ bb.0.entry:
+
+ ; CHECK-LABEL: name: test_40
+ ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[READ_VLENB]](s64)
+ ; CHECK-NEXT: $x11 = COPY [[C]](s64)
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; CHECK-NEXT: $x10 = COPY [[COPY]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = G_VSCALE i64 40
+ $x10 = COPY %0
+ PseudoRET implicit $x10
+...
+
+
>From c6b84cc34ca7c3077e21fe244cd863b391589d4c Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Thu, 21 Mar 2024 06:07:08 -0700
Subject: [PATCH 2/8] !fixup support clampScalar for G_VSCALE; respond to
comments
---
.../CodeGen/GlobalISel/MachineIRBuilder.h | 11 +
.../CodeGen/GlobalISel/LegalizerHelper.cpp | 51 ++++-
.../CodeGen/GlobalISel/MachineIRBuilder.cpp | 7 +
.../Target/RISCV/GISel/RISCVLegalizerInfo.cpp | 8 +-
.../legalizer/rvv/legalize-vscale-rv32.mir | 193 ++++++++++++++++--
5 files changed, 252 insertions(+), 18 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
index aaa81342845bff..616db4fc6fb6cb 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
@@ -1165,6 +1165,17 @@ class MachineIRBuilder {
/// \return a MachineInstrBuilder for the newly created instruction.
MachineInstrBuilder buildVScale(const DstOp &Res, const ConstantInt &MinElts);
+ /// Build and insert \p Res = G_VSCALE \p MinElts
+ ///
+ /// G_VSCALE puts the value of the runtime vscale multiplied by \p MinElts
+ /// into \p Res.
+ ///
+ /// \pre setBasicBlock or setMI must have been called.
+ /// \pre \p Res must be a generic virtual register with scalar type.
+ ///
+ /// \return a MachineInstrBuilder for the newly created instruction.
+ MachineInstrBuilder buildVScale(const DstOp &Res, const APInt &MinElts);
+
/// Build and insert a G_INTRINSIC instruction.
///
/// There are four different opcodes based on combinations of whether the
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index abe23af00a7890..41de4d94ab4a02 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -1699,6 +1699,36 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
case TargetOpcode::G_FLDEXP:
case TargetOpcode::G_STRICT_FLDEXP:
return narrowScalarFLDEXP(MI, TypeIdx, NarrowTy);
+ case TargetOpcode::G_VSCALE: {
+ LLT Ty = MRI.getType(MI.getOperand(0).getReg());
+ const APInt &Val = MI.getOperand(1).getCImm()->getValue();
+ unsigned TotalSize = Ty.getSizeInBits();
+ unsigned NarrowSize = NarrowTy.getSizeInBits();
+ int NumParts = TotalSize / NarrowSize;
+
+ SmallVector<Register, 4> PartRegs;
+ for (int I = 0; I != NumParts; ++I) {
+ unsigned Offset = I * NarrowSize;
+ auto K =
+ MIRBuilder.buildVScale(NarrowTy, Val.lshr(Offset).trunc(NarrowSize));
+ PartRegs.push_back(K.getReg(0));
+ }
+ LLT LeftoverTy;
+ unsigned LeftoverBits = TotalSize - NumParts * NarrowSize;
+ SmallVector<Register, 1> LeftoverRegs;
+ if (LeftoverBits != 0) {
+ LeftoverTy = LLT::scalar(LeftoverBits);
+ auto K = MIRBuilder.buildVScale(
+ LeftoverTy, Val.lshr(NumParts * NarrowSize).trunc(LeftoverBits));
+ LeftoverRegs.push_back(K.getReg(0));
+ }
+
+ insertParts(MI.getOperand(0).getReg(), Ty, NarrowTy, PartRegs, LeftoverTy,
+ LeftoverRegs);
+
+ MI.eraseFromParent();
+ return Legalized;
+ }
}
}
@@ -2966,7 +2996,7 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
case TargetOpcode::G_VECREDUCE_FMIN:
case TargetOpcode::G_VECREDUCE_FMAX:
case TargetOpcode::G_VECREDUCE_FMINIMUM:
- case TargetOpcode::G_VECREDUCE_FMAXIMUM:
+ case TargetOpcode::G_VECREDUCE_FMAXIMUM: {
if (TypeIdx != 0)
return UnableToLegalize;
Observer.changingInstr(MI);
@@ -2980,6 +3010,25 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
Observer.changedInstr(MI);
return Legalized;
}
+ case TargetOpcode::G_VSCALE: {
+ MachineOperand &SrcMO = MI.getOperand(1);
+ LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
+ unsigned ExtOpc = LI.getExtOpcodeForWideningConstant(
+ MRI.getType(MI.getOperand(0).getReg()));
+ assert((ExtOpc == TargetOpcode::G_ZEXT || ExtOpc == TargetOpcode::G_SEXT ||
+ ExtOpc == TargetOpcode::G_ANYEXT) &&
+ "Illegal Extend");
+ const APInt &SrcVal = SrcMO.getCImm()->getValue();
+ const APInt &Val = (ExtOpc == TargetOpcode::G_SEXT)
+ ? SrcVal.sext(WideTy.getSizeInBits())
+ : SrcVal.zext(WideTy.getSizeInBits());
+ Observer.changingInstr(MI);
+ SrcMO.setCImm(ConstantInt::get(Ctx, Val));
+ widenScalarDst(MI, WideTy);
+ Observer.changedInstr(MI);
+ return Legalized;
+ }
+ }
}
static void getUnmergePieces(SmallVectorImpl<Register> &Pieces,
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
index f7aaa0f02efcb3..f2665e25d195e9 100644
--- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
@@ -811,6 +811,13 @@ MachineInstrBuilder MachineIRBuilder::buildVScale(const DstOp &Res,
return VScale;
}
+MachineInstrBuilder MachineIRBuilder::buildVScale(const DstOp &Res,
+ const APInt &MinElts) {
+ ConstantInt *CI =
+ ConstantInt::get(getMF().getFunction().getContext(), MinElts);
+ return buildVScale(Res, *CI);
+}
+
static unsigned getIntrinsicOpcode(bool HasSideEffects, bool IsConvergent) {
if (HasSideEffects && IsConvergent)
return TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS;
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index a7829d4819ebd0..a4b344ba6377e7 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -374,7 +374,9 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
.clampScalar(0, s32, sXLen)
.lowerForCartesianProduct({s32, sXLen, p0}, {p0});
- getActionDefinitionsBuilder(G_VSCALE).customFor({sXLen});
+ getActionDefinitionsBuilder(G_VSCALE)
+ .clampScalar(0, sXLen, sXLen)
+ .customFor({sXLen});
getLegacyLegalizerInfo().computeTables();
}
@@ -507,7 +509,9 @@ bool RISCVLegalizerInfo::legalizeVScale(MachineInstr &MI,
// vscale as VLENB / 8.
static_assert(RISCV::RVVBitsPerBlock == 64, "Unexpected bits per block!");
if (STI.getRealMinVLen() < RISCV::RVVBitsPerBlock)
- report_fatal_error("Support for VLEN==32 is incomplete.");
+ // Support for VLEN==32 is incomplete.
+ return false;
+
// We assume VLENB is a multiple of 8. We manually choose the best shift
// here because SimplifyDemandedBits isn't always able to simplify it.
uint64_t Val = MI.getOperand(1).getCImm()->getZExtValue();
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-vscale-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-vscale-rv32.mir
index 60fc3c66adec4a..39634954223622 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-vscale-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-vscale-rv32.mir
@@ -2,11 +2,11 @@
# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s
---
-name: test_1
+name: test_1_s32
body: |
bb.0.entry:
- ; CHECK-LABEL: name: test_1
+ ; CHECK-LABEL: name: test_1_s32
; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
@@ -17,11 +17,11 @@ body: |
PseudoRET implicit $x10
...
---
-name: test_2
+name: test_2_s32
body: |
bb.0.entry:
- ; CHECK-LABEL: name: test_2
+ ; CHECK-LABEL: name: test_2_s32
; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
@@ -32,11 +32,11 @@ body: |
PseudoRET implicit $x10
...
---
-name: test_3
+name: test_3_s32
body: |
bb.0.entry:
- ; CHECK-LABEL: name: test_3
+ ; CHECK-LABEL: name: test_3_s32
; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
@@ -54,11 +54,11 @@ body: |
PseudoRET implicit $x10
...
---
-name: test_4
+name: test_4_s32
body: |
bb.0.entry:
- ; CHECK-LABEL: name: test_4
+ ; CHECK-LABEL: name: test_4_s32
; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
@@ -69,11 +69,11 @@ body: |
PseudoRET implicit $x10
...
---
-name: test_8
+name: test_8_s32
body: |
bb.0.entry:
- ; CHECK-LABEL: name: test_8
+ ; CHECK-LABEL: name: test_8_s32
; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
; CHECK-NEXT: $x10 = COPY [[READ_VLENB]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
@@ -82,11 +82,11 @@ body: |
PseudoRET implicit $x10
...
---
-name: test_16
+name: test_16_s32
body: |
bb.0.entry:
- ; CHECK-LABEL: name: test_16
+ ; CHECK-LABEL: name: test_16_s32
; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[READ_VLENB]], [[C]](s32)
@@ -97,11 +97,11 @@ body: |
PseudoRET implicit $x10
...
---
-name: test_40
+name: test_40_s32
body: |
bb.0.entry:
- ; CHECK-LABEL: name: test_40
+ ; CHECK-LABEL: name: test_40_s32
; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
@@ -117,4 +117,167 @@ body: |
PseudoRET implicit $x10
...
-
+---
+name: test_1_s64
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_1_s64
+ ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
+ ; CHECK-NEXT: [[READ_VLENB1:%[0-9]+]]:_(s32) = G_READ_VLENB
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[READ_VLENB1]](s32)
+ ; CHECK-NEXT: $x11 = COPY [[C1]](s32)
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = G_VSCALE i64 1
+ %1:_(s32) = G_TRUNC %0
+ $x10 = COPY %1
+ PseudoRET implicit $x10
+...
+---
+name: test_2_s64
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_2_s64
+ ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
+ ; CHECK-NEXT: [[READ_VLENB1:%[0-9]+]]:_(s32) = G_READ_VLENB
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[READ_VLENB1]](s32)
+ ; CHECK-NEXT: $x11 = COPY [[C1]](s32)
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = G_VSCALE i64 2
+ %1:_(s32) = G_TRUNC %0
+ $x10 = COPY %1
+ PseudoRET implicit $x10
+...
+---
+name: test_3_s64
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_3_s64
+ ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
+ ; CHECK-NEXT: $x11 = COPY [[C1]](s32)
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: [[READ_VLENB1:%[0-9]+]]:_(s32) = G_READ_VLENB
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[READ_VLENB1]](s32)
+ ; CHECK-NEXT: $x11 = COPY [[C2]](s32)
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[COPY]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = G_VSCALE i64 3
+ %1:_(s32) = G_TRUNC %0
+ $x10 = COPY %1
+ PseudoRET implicit $x10
+...
+---
+name: test_4_s64
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_4_s64
+ ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
+ ; CHECK-NEXT: [[READ_VLENB1:%[0-9]+]]:_(s32) = G_READ_VLENB
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[READ_VLENB1]](s32)
+ ; CHECK-NEXT: $x11 = COPY [[C1]](s32)
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = G_VSCALE i64 4
+ %1:_(s32) = G_TRUNC %0
+ $x10 = COPY %1
+ PseudoRET implicit $x10
+...
+---
+name: test_8_s64
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_8_s64
+ ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
+ ; CHECK-NEXT: [[READ_VLENB1:%[0-9]+]]:_(s32) = G_READ_VLENB
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[READ_VLENB1]](s32)
+ ; CHECK-NEXT: $x11 = COPY [[C]](s32)
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[READ_VLENB]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = G_VSCALE i64 8
+ %1:_(s32) = G_TRUNC %0
+ $x10 = COPY %1
+ PseudoRET implicit $x10
+...
+---
+name: test_16_s64
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_16_s64
+ ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[READ_VLENB]], [[C]](s32)
+ ; CHECK-NEXT: [[READ_VLENB1:%[0-9]+]]:_(s32) = G_READ_VLENB
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[READ_VLENB1]](s32)
+ ; CHECK-NEXT: $x11 = COPY [[C1]](s32)
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[SHL]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = G_VSCALE i64 16
+ %1:_(s32) = G_TRUNC %0
+ $x10 = COPY %1
+ PseudoRET implicit $x10
+...
+---
+name: test_40_s64
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_40_s64
+ ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[READ_VLENB]](s32)
+ ; CHECK-NEXT: $x11 = COPY [[C]](s32)
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: [[READ_VLENB1:%[0-9]+]]:_(s32) = G_READ_VLENB
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[READ_VLENB1]](s32)
+ ; CHECK-NEXT: $x11 = COPY [[C1]](s32)
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[COPY]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = G_VSCALE i64 40
+ %1:_(s32) = G_TRUNC %0
+ $x10 = COPY %1
+ PseudoRET implicit $x10
+...
>From f28fb49d6a78775518c2c89e04ef1702443a6378 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Thu, 21 Mar 2024 09:22:04 -0700
Subject: [PATCH 3/8] [RISCV][GISEL] Add regbankselect tests for G_VSCALE
---
.../regbankselect/rvv/vscale-rv32.mir | 409 ++++++++++++++++++
.../regbankselect/rvv/vscale-rv64.mir | 158 +++++++
2 files changed, 567 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv32.mir
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv64.mir
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv32.mir
new file mode 100644
index 00000000000000..2bc33f94978ce6
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv32.mir
@@ -0,0 +1,409 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN: -o - | FileCheck %s
+
+---
+name: test_1_s32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_1_s32
+ ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s32) = G_READ_VLENB
+ ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:gprb(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %1:_(s32) = G_READ_VLENB
+ %2:_(s32) = G_CONSTANT i32 3
+ %0:_(s32) = G_LSHR %1, %2(s32)
+ $x10 = COPY %0(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: test_2_s32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_2_s32
+ ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s32) = G_READ_VLENB
+ ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 2
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:gprb(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %1:_(s32) = G_READ_VLENB
+ %2:_(s32) = G_CONSTANT i32 2
+ %0:_(s32) = G_LSHR %1, %2(s32)
+ $x10 = COPY %0(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: test_3_s32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_3_s32
+ ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s32) = G_READ_VLENB
+ ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:gprb(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
+ ; CHECK-NEXT: $x11 = COPY [[C1]](s32)
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+ ; CHECK-NEXT: $x10 = COPY [[COPY]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %1:_(s32) = G_READ_VLENB
+ %2:_(s32) = G_CONSTANT i32 3
+ %3:_(s32) = G_LSHR %1, %2(s32)
+ %4:_(s32) = G_CONSTANT i32 3
+ ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ $x10 = COPY %3(s32)
+ $x11 = COPY %4(s32)
+ PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ %0:_(s32) = COPY $x10
+ $x10 = COPY %0(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: test_4_s32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_4_s32
+ ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s32) = G_READ_VLENB
+ ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:gprb(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %1:_(s32) = G_READ_VLENB
+ %2:_(s32) = G_CONSTANT i32 1
+ %0:_(s32) = G_LSHR %1, %2(s32)
+ $x10 = COPY %0(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: test_8_s32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_8_s32
+ ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s32) = G_READ_VLENB
+ ; CHECK-NEXT: $x10 = COPY [[READ_VLENB]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = G_READ_VLENB
+ $x10 = COPY %0(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: test_16_s32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_16_s32
+ ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s32) = G_READ_VLENB
+ ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:gprb(s32) = G_SHL [[READ_VLENB]], [[C]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[SHL]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %1:_(s32) = G_READ_VLENB
+ %2:_(s32) = G_CONSTANT i32 1
+ %0:_(s32) = G_SHL %1, %2(s32)
+ $x10 = COPY %0(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: test_40_s32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_40_s32
+ ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s32) = G_READ_VLENB
+ ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 5
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[READ_VLENB]](s32)
+ ; CHECK-NEXT: $x11 = COPY [[C]](s32)
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+ ; CHECK-NEXT: $x10 = COPY [[COPY]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %1:_(s32) = G_READ_VLENB
+ %2:_(s32) = G_CONSTANT i32 5
+ ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ $x10 = COPY %1(s32)
+ $x11 = COPY %2(s32)
+ PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ %0:_(s32) = COPY $x10
+ $x10 = COPY %0(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: test_1_s64
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_1_s64
+ ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s32) = G_READ_VLENB
+ ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:gprb(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
+ ; CHECK-NEXT: [[READ_VLENB1:%[0-9]+]]:gprb(s32) = G_READ_VLENB
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[READ_VLENB1]](s32)
+ ; CHECK-NEXT: $x11 = COPY [[C1]](s32)
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %6:_(s32) = G_READ_VLENB
+ %7:_(s32) = G_CONSTANT i32 3
+ %2:_(s32) = G_LSHR %6, %7(s32)
+ %4:_(s32) = G_READ_VLENB
+ %5:_(s32) = G_CONSTANT i32 0
+ ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ $x10 = COPY %4(s32)
+ $x11 = COPY %5(s32)
+ PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: test_2_s64
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_2_s64
+ ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s32) = G_READ_VLENB
+ ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 2
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:gprb(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
+ ; CHECK-NEXT: [[READ_VLENB1:%[0-9]+]]:gprb(s32) = G_READ_VLENB
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[READ_VLENB1]](s32)
+ ; CHECK-NEXT: $x11 = COPY [[C1]](s32)
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %6:_(s32) = G_READ_VLENB
+ %7:_(s32) = G_CONSTANT i32 2
+ %2:_(s32) = G_LSHR %6, %7(s32)
+ %4:_(s32) = G_READ_VLENB
+ %5:_(s32) = G_CONSTANT i32 0
+ ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ $x10 = COPY %4(s32)
+ $x11 = COPY %5(s32)
+ PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: test_3_s64
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_3_s64
+ ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s32) = G_READ_VLENB
+ ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:gprb(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
+ ; CHECK-NEXT: $x11 = COPY [[C1]](s32)
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+ ; CHECK-NEXT: [[READ_VLENB1:%[0-9]+]]:gprb(s32) = G_READ_VLENB
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[READ_VLENB1]](s32)
+ ; CHECK-NEXT: $x11 = COPY [[C2]](s32)
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[COPY]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %6:_(s32) = G_READ_VLENB
+ %7:_(s32) = G_CONSTANT i32 3
+ %8:_(s32) = G_LSHR %6, %7(s32)
+ %9:_(s32) = G_CONSTANT i32 3
+ ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ $x10 = COPY %8(s32)
+ $x11 = COPY %9(s32)
+ PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ %2:_(s32) = COPY $x10
+ %4:_(s32) = G_READ_VLENB
+ %5:_(s32) = G_CONSTANT i32 0
+ ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ $x10 = COPY %4(s32)
+ $x11 = COPY %5(s32)
+ PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: test_4_s64
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_4_s64
+ ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s32) = G_READ_VLENB
+ ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:gprb(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
+ ; CHECK-NEXT: [[READ_VLENB1:%[0-9]+]]:gprb(s32) = G_READ_VLENB
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[READ_VLENB1]](s32)
+ ; CHECK-NEXT: $x11 = COPY [[C1]](s32)
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %6:_(s32) = G_READ_VLENB
+ %7:_(s32) = G_CONSTANT i32 1
+ %2:_(s32) = G_LSHR %6, %7(s32)
+ %4:_(s32) = G_READ_VLENB
+ %5:_(s32) = G_CONSTANT i32 0
+ ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ $x10 = COPY %4(s32)
+ $x11 = COPY %5(s32)
+ PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: test_8_s64
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_8_s64
+ ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s32) = G_READ_VLENB
+ ; CHECK-NEXT: [[READ_VLENB1:%[0-9]+]]:gprb(s32) = G_READ_VLENB
+ ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[READ_VLENB1]](s32)
+ ; CHECK-NEXT: $x11 = COPY [[C]](s32)
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[READ_VLENB]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %2:_(s32) = G_READ_VLENB
+ %4:_(s32) = G_READ_VLENB
+ %5:_(s32) = G_CONSTANT i32 0
+ ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ $x10 = COPY %4(s32)
+ $x11 = COPY %5(s32)
+ PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: test_16_s64
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_16_s64
+ ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s32) = G_READ_VLENB
+ ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:gprb(s32) = G_SHL [[READ_VLENB]], [[C]](s32)
+ ; CHECK-NEXT: [[READ_VLENB1:%[0-9]+]]:gprb(s32) = G_READ_VLENB
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[READ_VLENB1]](s32)
+ ; CHECK-NEXT: $x11 = COPY [[C1]](s32)
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[SHL]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %6:_(s32) = G_READ_VLENB
+ %7:_(s32) = G_CONSTANT i32 1
+ %2:_(s32) = G_SHL %6, %7(s32)
+ %4:_(s32) = G_READ_VLENB
+ %5:_(s32) = G_CONSTANT i32 0
+ ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ $x10 = COPY %4(s32)
+ $x11 = COPY %5(s32)
+ PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: test_40_s64
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_40_s64
+ ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s32) = G_READ_VLENB
+ ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 5
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[READ_VLENB]](s32)
+ ; CHECK-NEXT: $x11 = COPY [[C]](s32)
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+ ; CHECK-NEXT: [[READ_VLENB1:%[0-9]+]]:gprb(s32) = G_READ_VLENB
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[READ_VLENB1]](s32)
+ ; CHECK-NEXT: $x11 = COPY [[C1]](s32)
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[COPY]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %6:_(s32) = G_READ_VLENB
+ %7:_(s32) = G_CONSTANT i32 5
+ ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ $x10 = COPY %6(s32)
+ $x11 = COPY %7(s32)
+ PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ %2:_(s32) = COPY $x10
+ %4:_(s32) = G_READ_VLENB
+ %5:_(s32) = G_CONSTANT i32 0
+ ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ $x10 = COPY %4(s32)
+ $x11 = COPY %5(s32)
+ PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv64.mir
new file mode 100644
index 00000000000000..45a5a1d84646eb
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv64.mir
@@ -0,0 +1,158 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \
+# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN: -o - | FileCheck %s
+
+---
+name: test_1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_1
+ ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s64) = G_READ_VLENB
+ ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:gprb(s64) = G_LSHR [[READ_VLENB]], [[C]](s64)
+ ; CHECK-NEXT: $x10 = COPY [[LSHR]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %1:_(s64) = G_READ_VLENB
+ %2:_(s64) = G_CONSTANT i64 3
+ %0:_(s64) = G_LSHR %1, %2(s64)
+ $x10 = COPY %0(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: test_2
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_2
+ ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s64) = G_READ_VLENB
+ ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:gprb(s64) = G_LSHR [[READ_VLENB]], [[C]](s64)
+ ; CHECK-NEXT: $x10 = COPY [[LSHR]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %1:_(s64) = G_READ_VLENB
+ %2:_(s64) = G_CONSTANT i64 2
+ %0:_(s64) = G_LSHR %1, %2(s64)
+ $x10 = COPY %0(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: test_3
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_3
+ ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s64) = G_READ_VLENB
+ ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:gprb(s64) = G_LSHR [[READ_VLENB]], [[C]](s64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[LSHR]](s64)
+ ; CHECK-NEXT: $x11 = COPY [[C1]](s64)
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+ ; CHECK-NEXT: $x10 = COPY [[COPY]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %1:_(s64) = G_READ_VLENB
+ %2:_(s64) = G_CONSTANT i64 3
+ %3:_(s64) = G_LSHR %1, %2(s64)
+ %4:_(s64) = G_CONSTANT i64 3
+ ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ $x10 = COPY %3(s64)
+ $x11 = COPY %4(s64)
+ PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ %0:_(s64) = COPY $x10
+ $x10 = COPY %0(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: test_4
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_4
+ ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s64) = G_READ_VLENB
+ ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:gprb(s64) = G_LSHR [[READ_VLENB]], [[C]](s64)
+ ; CHECK-NEXT: $x10 = COPY [[LSHR]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %1:_(s64) = G_READ_VLENB
+ %2:_(s64) = G_CONSTANT i64 1
+ %0:_(s64) = G_LSHR %1, %2(s64)
+ $x10 = COPY %0(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: test_8
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_8
+ ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s64) = G_READ_VLENB
+ ; CHECK-NEXT: $x10 = COPY [[READ_VLENB]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = G_READ_VLENB
+ $x10 = COPY %0(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: test_16
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_16
+ ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s64) = G_READ_VLENB
+ ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:gprb(s64) = G_SHL [[READ_VLENB]], [[C]](s64)
+ ; CHECK-NEXT: $x10 = COPY [[SHL]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %1:_(s64) = G_READ_VLENB
+ %2:_(s64) = G_CONSTANT i64 1
+ %0:_(s64) = G_SHL %1, %2(s64)
+ $x10 = COPY %0(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: test_40
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_40
+ ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s64) = G_READ_VLENB
+ ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 5
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[READ_VLENB]](s64)
+ ; CHECK-NEXT: $x11 = COPY [[C]](s64)
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+ ; CHECK-NEXT: $x10 = COPY [[COPY]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %1:_(s64) = G_READ_VLENB
+ %2:_(s64) = G_CONSTANT i64 5
+ ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ $x10 = COPY %1(s64)
+ $x11 = COPY %2(s64)
+ PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ %0:_(s64) = COPY $x10
+ $x10 = COPY %0(s64)
+ PseudoRET implicit $x10
+
+...
>From e0409ab929e9b74f2aa881f791a53972c6f612b7 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Thu, 21 Mar 2024 09:27:33 -0700
Subject: [PATCH 4/8] [RISCV][GISEL] Add instruction select tests for G_VSCALE
---
.../instruction-select/rvv/vscale32.mir | 412 ++++++++++++++++++
.../instruction-select/rvv/vscale64.mir | 140 ++++++
2 files changed, 552 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vscale32.mir
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vscale64.mir
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vscale32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vscale32.mir
new file mode 100644
index 00000000000000..084d5531c4597b
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vscale32.mir
@@ -0,0 +1,412 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=instruction-select \
+# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: test_1_s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_1_s32
+ ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
+ ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3
+ ; CHECK-NEXT: $x10 = COPY [[SRLI]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:gprb(s32) = G_READ_VLENB
+ %1:gprb(s32) = G_CONSTANT i32 3
+ %2:gprb(s32) = G_LSHR %0, %1(s32)
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: test_2_s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_2_s32
+ ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
+ ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 2
+ ; CHECK-NEXT: $x10 = COPY [[SRLI]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:gprb(s32) = G_READ_VLENB
+ %1:gprb(s32) = G_CONSTANT i32 2
+ %2:gprb(s32) = G_LSHR %0, %1(s32)
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: test_3_s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_3_s32
+ ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
+ ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3
+ ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 3
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[SRLI]]
+ ; CHECK-NEXT: $x11 = COPY [[ADDI]]
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; CHECK-NEXT: $x10 = COPY [[COPY]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:gprb(s32) = G_READ_VLENB
+ %1:gprb(s32) = G_CONSTANT i32 3
+ %2:gprb(s32) = G_LSHR %0, %1(s32)
+ %3:gprb(s32) = G_CONSTANT i32 3
+ ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ $x10 = COPY %2(s32)
+ $x11 = COPY %3(s32)
+ PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ %4:gprb(s32) = COPY $x10
+ $x10 = COPY %4(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: test_4_s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_4_s32
+ ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
+ ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 1
+ ; CHECK-NEXT: $x10 = COPY [[SRLI]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:gprb(s32) = G_READ_VLENB
+ %1:gprb(s32) = G_CONSTANT i32 1
+ %2:gprb(s32) = G_LSHR %0, %1(s32)
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: test_8_s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_8_s32
+ ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
+ ; CHECK-NEXT: $x10 = COPY [[PseudoReadVLENB]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:gprb(s32) = G_READ_VLENB
+ $x10 = COPY %0(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: test_16_s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_16_s32
+ ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
+ ; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[PseudoReadVLENB]], 1
+ ; CHECK-NEXT: $x10 = COPY [[SLLI]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:gprb(s32) = G_READ_VLENB
+ %1:gprb(s32) = G_CONSTANT i32 1
+ %2:gprb(s32) = G_SHL %0, %1(s32)
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: test_40_s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_40_s32
+ ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
+ ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 5
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[PseudoReadVLENB]]
+ ; CHECK-NEXT: $x11 = COPY [[ADDI]]
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; CHECK-NEXT: $x10 = COPY [[COPY]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:gprb(s32) = G_READ_VLENB
+ %1:gprb(s32) = G_CONSTANT i32 5
+ ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ $x10 = COPY %0(s32)
+ $x11 = COPY %1(s32)
+ PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ %2:gprb(s32) = COPY $x10
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: test_1_s64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_1_s64
+ ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
+ ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3
+ ; CHECK-NEXT: [[PseudoReadVLENB1:%[0-9]+]]:gpr = PseudoReadVLENB
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[PseudoReadVLENB1]]
+ ; CHECK-NEXT: $x11 = COPY [[COPY]]
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[SRLI]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:gprb(s32) = G_READ_VLENB
+ %1:gprb(s32) = G_CONSTANT i32 3
+ %2:gprb(s32) = G_LSHR %0, %1(s32)
+ %3:gprb(s32) = G_READ_VLENB
+ %4:gprb(s32) = G_CONSTANT i32 0
+ ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ $x10 = COPY %3(s32)
+ $x11 = COPY %4(s32)
+ PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: test_2_s64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_2_s64
+ ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
+ ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 2
+ ; CHECK-NEXT: [[PseudoReadVLENB1:%[0-9]+]]:gpr = PseudoReadVLENB
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[PseudoReadVLENB1]]
+ ; CHECK-NEXT: $x11 = COPY [[COPY]]
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[SRLI]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:gprb(s32) = G_READ_VLENB
+ %1:gprb(s32) = G_CONSTANT i32 2
+ %2:gprb(s32) = G_LSHR %0, %1(s32)
+ %3:gprb(s32) = G_READ_VLENB
+ %4:gprb(s32) = G_CONSTANT i32 0
+ ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ $x10 = COPY %3(s32)
+ $x11 = COPY %4(s32)
+ PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: test_3_s64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_3_s64
+ ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
+ ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3
+ ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 3
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[SRLI]]
+ ; CHECK-NEXT: $x11 = COPY [[ADDI]]
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; CHECK-NEXT: [[PseudoReadVLENB1:%[0-9]+]]:gpr = PseudoReadVLENB
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[PseudoReadVLENB1]]
+ ; CHECK-NEXT: $x11 = COPY [[COPY1]]
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[COPY]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:gprb(s32) = G_READ_VLENB
+ %1:gprb(s32) = G_CONSTANT i32 3
+ %2:gprb(s32) = G_LSHR %0, %1(s32)
+ %3:gprb(s32) = G_CONSTANT i32 3
+ ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ $x10 = COPY %2(s32)
+ $x11 = COPY %3(s32)
+ PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ %4:gprb(s32) = COPY $x10
+ %5:gprb(s32) = G_READ_VLENB
+ %6:gprb(s32) = G_CONSTANT i32 0
+ ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ $x10 = COPY %5(s32)
+ $x11 = COPY %6(s32)
+ PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ $x10 = COPY %4(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: test_4_s64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_4_s64
+ ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
+ ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 1
+ ; CHECK-NEXT: [[PseudoReadVLENB1:%[0-9]+]]:gpr = PseudoReadVLENB
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[PseudoReadVLENB1]]
+ ; CHECK-NEXT: $x11 = COPY [[COPY]]
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[SRLI]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:gprb(s32) = G_READ_VLENB
+ %1:gprb(s32) = G_CONSTANT i32 1
+ %2:gprb(s32) = G_LSHR %0, %1(s32)
+ %3:gprb(s32) = G_READ_VLENB
+ %4:gprb(s32) = G_CONSTANT i32 0
+ ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ $x10 = COPY %3(s32)
+ $x11 = COPY %4(s32)
+ PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: test_8_s64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_8_s64
+ ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
+ ; CHECK-NEXT: [[PseudoReadVLENB1:%[0-9]+]]:gpr = PseudoReadVLENB
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[PseudoReadVLENB1]]
+ ; CHECK-NEXT: $x11 = COPY [[COPY]]
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[PseudoReadVLENB]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:gprb(s32) = G_READ_VLENB
+ %1:gprb(s32) = G_READ_VLENB
+ %2:gprb(s32) = G_CONSTANT i32 0
+ ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ $x10 = COPY %1(s32)
+ $x11 = COPY %2(s32)
+ PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ $x10 = COPY %0(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: test_16_s64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_16_s64
+ ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
+ ; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[PseudoReadVLENB]], 1
+ ; CHECK-NEXT: [[PseudoReadVLENB1:%[0-9]+]]:gpr = PseudoReadVLENB
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[PseudoReadVLENB1]]
+ ; CHECK-NEXT: $x11 = COPY [[COPY]]
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[SLLI]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:gprb(s32) = G_READ_VLENB
+ %1:gprb(s32) = G_CONSTANT i32 1
+ %2:gprb(s32) = G_SHL %0, %1(s32)
+ %3:gprb(s32) = G_READ_VLENB
+ %4:gprb(s32) = G_CONSTANT i32 0
+ ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ $x10 = COPY %3(s32)
+ $x11 = COPY %4(s32)
+ PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: test_40_s64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_40_s64
+ ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
+ ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 5
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[PseudoReadVLENB]]
+ ; CHECK-NEXT: $x11 = COPY [[ADDI]]
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; CHECK-NEXT: [[PseudoReadVLENB1:%[0-9]+]]:gpr = PseudoReadVLENB
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[PseudoReadVLENB1]]
+ ; CHECK-NEXT: $x11 = COPY [[COPY1]]
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[COPY]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:gprb(s32) = G_READ_VLENB
+ %1:gprb(s32) = G_CONSTANT i32 5
+ ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ $x10 = COPY %0(s32)
+ $x11 = COPY %1(s32)
+ PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ %2:gprb(s32) = COPY $x10
+ %3:gprb(s32) = G_READ_VLENB
+ %4:gprb(s32) = G_CONSTANT i32 0
+ ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ $x10 = COPY %3(s32)
+ $x11 = COPY %4(s32)
+ PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vscale64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vscale64.mir
new file mode 100644
index 00000000000000..3e480e5b8d732a
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vscale64.mir
@@ -0,0 +1,140 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=instruction-select \
+# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: test_1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_1
+ ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
+ ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 2
+ ; CHECK-NEXT: $x10 = COPY [[SRLI]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:gprb(s64) = G_READ_VLENB
+ %1:gprb(s64) = G_CONSTANT i64 2
+ %2:gprb(s64) = G_LSHR %0, %1(s64)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: test_3
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_3
+ ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
+ ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3
+ ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 3
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[SRLI]]
+ ; CHECK-NEXT: $x11 = COPY [[ADDI]]
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; CHECK-NEXT: $x10 = COPY [[COPY]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:gprb(s64) = G_READ_VLENB
+ %1:gprb(s64) = G_CONSTANT i64 3
+ %2:gprb(s64) = G_LSHR %0, %1(s64)
+ %3:gprb(s64) = G_CONSTANT i64 3
+ ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ $x10 = COPY %2(s64)
+ $x11 = COPY %3(s64)
+ PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ %4:gprb(s64) = COPY $x10
+ $x10 = COPY %4(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: test_4
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_4
+ ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
+ ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 1
+ ; CHECK-NEXT: $x10 = COPY [[SRLI]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:gprb(s64) = G_READ_VLENB
+ %1:gprb(s64) = G_CONSTANT i64 1
+ %2:gprb(s64) = G_LSHR %0, %1(s64)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: test_8
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_8
+ ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
+ ; CHECK-NEXT: $x10 = COPY [[PseudoReadVLENB]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:gprb(s64) = G_READ_VLENB
+ $x10 = COPY %0(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: test_16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_16
+ ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
+ ; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[PseudoReadVLENB]], 1
+ ; CHECK-NEXT: $x10 = COPY [[SLLI]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:gprb(s64) = G_READ_VLENB
+ %1:gprb(s64) = G_CONSTANT i64 1
+ %2:gprb(s64) = G_SHL %0, %1(s64)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: test_40
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_40
+ ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
+ ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 5
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: $x10 = COPY [[PseudoReadVLENB]]
+ ; CHECK-NEXT: $x11 = COPY [[ADDI]]
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; CHECK-NEXT: $x10 = COPY [[COPY]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:gprb(s64) = G_READ_VLENB
+ %1:gprb(s64) = G_CONSTANT i64 5
+ ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ $x10 = COPY %0(s64)
+ $x11 = COPY %1(s64)
+ PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ %2:gprb(s64) = COPY $x10
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
>From 08973996fe4f1ce9e8a1fcdaeb1c905b97758c2f Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Mon, 25 Mar 2024 11:54:14 -0700
Subject: [PATCH 5/8] fixup! the imm is always a signed value
---
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 10 ++--------
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index 41de4d94ab4a02..5f1c498c008c7a 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -3013,15 +3013,9 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
case TargetOpcode::G_VSCALE: {
MachineOperand &SrcMO = MI.getOperand(1);
LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
- unsigned ExtOpc = LI.getExtOpcodeForWideningConstant(
- MRI.getType(MI.getOperand(0).getReg()));
- assert((ExtOpc == TargetOpcode::G_ZEXT || ExtOpc == TargetOpcode::G_SEXT ||
- ExtOpc == TargetOpcode::G_ANYEXT) &&
- "Illegal Extend");
const APInt &SrcVal = SrcMO.getCImm()->getValue();
- const APInt &Val = (ExtOpc == TargetOpcode::G_SEXT)
- ? SrcVal.sext(WideTy.getSizeInBits())
- : SrcVal.zext(WideTy.getSizeInBits());
+ // The CImm is always a signed value
+ const APInt &Val = SrcVal.sext(WideTy.getSizeInBits());
Observer.changingInstr(MI);
SrcMO.setCImm(ConstantInt::get(Ctx, Val));
widenScalarDst(MI, WideTy);
>From eb80e74fdc6d2f4f0dadddbaea277bd91ecdf552 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Mon, 25 Mar 2024 13:45:22 -0700
Subject: [PATCH 6/8] fixup! narrow G_VSCALE as G_MUL
---
.../CodeGen/GlobalISel/LegalizerHelper.cpp | 35 ++----
.../legalizer/rvv/legalize-vscale-rv32.mir | 108 ++++++++++--------
2 files changed, 73 insertions(+), 70 deletions(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index 5f1c498c008c7a..f116d7e5739a32 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -1700,31 +1700,16 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
case TargetOpcode::G_STRICT_FLDEXP:
return narrowScalarFLDEXP(MI, TypeIdx, NarrowTy);
case TargetOpcode::G_VSCALE: {
- LLT Ty = MRI.getType(MI.getOperand(0).getReg());
- const APInt &Val = MI.getOperand(1).getCImm()->getValue();
- unsigned TotalSize = Ty.getSizeInBits();
- unsigned NarrowSize = NarrowTy.getSizeInBits();
- int NumParts = TotalSize / NarrowSize;
-
- SmallVector<Register, 4> PartRegs;
- for (int I = 0; I != NumParts; ++I) {
- unsigned Offset = I * NarrowSize;
- auto K =
- MIRBuilder.buildVScale(NarrowTy, Val.lshr(Offset).trunc(NarrowSize));
- PartRegs.push_back(K.getReg(0));
- }
- LLT LeftoverTy;
- unsigned LeftoverBits = TotalSize - NumParts * NarrowSize;
- SmallVector<Register, 1> LeftoverRegs;
- if (LeftoverBits != 0) {
- LeftoverTy = LLT::scalar(LeftoverBits);
- auto K = MIRBuilder.buildVScale(
- LeftoverTy, Val.lshr(NumParts * NarrowSize).trunc(LeftoverBits));
- LeftoverRegs.push_back(K.getReg(0));
- }
-
- insertParts(MI.getOperand(0).getReg(), Ty, NarrowTy, PartRegs, LeftoverTy,
- LeftoverRegs);
+ Register Dst = MI.getOperand(0).getReg();
+ LLT Ty = MRI.getType(Dst);
+ LLT HalfTy = Ty.divide(2);
+
+ // Assume VSCALE(1) fits into a legal integer
+ const APInt One(HalfTy.getSizeInBits(), 1);
+ auto VScaleBase = MIRBuilder.buildVScale(HalfTy, One);
+ auto ZExt = MIRBuilder.buildZExt(Ty, VScaleBase);
+ auto C = MIRBuilder.buildConstant(Ty, *MI.getOperand(1).getCImm());
+ auto Res = MIRBuilder.buildMul(Dst, ZExt, C);
MI.eraseFromParent();
return Legalized;
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-vscale-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-vscale-rv32.mir
index 39634954223622..8ed90439803152 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-vscale-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-vscale-rv32.mir
@@ -125,14 +125,18 @@ body: |
; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
- ; CHECK-NEXT: [[READ_VLENB1:%[0-9]+]]:_(s32) = G_READ_VLENB
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[READ_VLENB1]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
; CHECK-NEXT: $x11 = COPY [[C1]](s32)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: $x12 = COPY [[C2]](s32)
+ ; CHECK-NEXT: $x13 = COPY [[C3]](s32)
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: $x10 = COPY [[COPY]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = G_VSCALE i64 1
%1:_(s32) = G_TRUNC %0
@@ -145,16 +149,20 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: test_2_s64
; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
- ; CHECK-NEXT: [[READ_VLENB1:%[0-9]+]]:_(s32) = G_READ_VLENB
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[READ_VLENB1]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
; CHECK-NEXT: $x11 = COPY [[C1]](s32)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: $x12 = COPY [[C2]](s32)
+ ; CHECK-NEXT: $x13 = COPY [[C3]](s32)
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: $x10 = COPY [[COPY]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = G_VSCALE i64 2
%1:_(s32) = G_TRUNC %0
@@ -169,20 +177,17 @@ body: |
; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
; CHECK-NEXT: $x11 = COPY [[C1]](s32)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: $x12 = COPY [[C2]](s32)
+ ; CHECK-NEXT: $x13 = COPY [[C3]](s32)
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
- ; CHECK-NEXT: [[READ_VLENB1:%[0-9]+]]:_(s32) = G_READ_VLENB
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[READ_VLENB1]](s32)
- ; CHECK-NEXT: $x11 = COPY [[C2]](s32)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
; CHECK-NEXT: $x10 = COPY [[COPY]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = G_VSCALE i64 3
@@ -196,16 +201,20 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: test_4_s64
; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
- ; CHECK-NEXT: [[READ_VLENB1:%[0-9]+]]:_(s32) = G_READ_VLENB
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[READ_VLENB1]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
; CHECK-NEXT: $x11 = COPY [[C1]](s32)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: $x12 = COPY [[C2]](s32)
+ ; CHECK-NEXT: $x13 = COPY [[C3]](s32)
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: $x10 = COPY [[COPY]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = G_VSCALE i64 4
%1:_(s32) = G_TRUNC %0
@@ -218,14 +227,20 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: test_8_s64
; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
- ; CHECK-NEXT: [[READ_VLENB1:%[0-9]+]]:_(s32) = G_READ_VLENB
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[READ_VLENB1]](s32)
- ; CHECK-NEXT: $x11 = COPY [[C]](s32)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
+ ; CHECK-NEXT: $x11 = COPY [[C1]](s32)
+ ; CHECK-NEXT: $x12 = COPY [[C2]](s32)
+ ; CHECK-NEXT: $x13 = COPY [[C3]](s32)
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[READ_VLENB]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: $x10 = COPY [[COPY]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = G_VSCALE i64 8
%1:_(s32) = G_TRUNC %0
@@ -238,16 +253,20 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: test_16_s64
; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[READ_VLENB]], [[C]](s32)
- ; CHECK-NEXT: [[READ_VLENB1:%[0-9]+]]:_(s32) = G_READ_VLENB
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[READ_VLENB1]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
; CHECK-NEXT: $x11 = COPY [[C1]](s32)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: $x12 = COPY [[C2]](s32)
+ ; CHECK-NEXT: $x13 = COPY [[C3]](s32)
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[SHL]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: $x10 = COPY [[COPY]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = G_VSCALE i64 16
%1:_(s32) = G_TRUNC %0
@@ -260,20 +279,19 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: test_40_s64
; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[READ_VLENB]](s32)
- ; CHECK-NEXT: $x11 = COPY [[C]](s32)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
- ; CHECK-NEXT: [[READ_VLENB1:%[0-9]+]]:_(s32) = G_READ_VLENB
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 40
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[READ_VLENB1]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
; CHECK-NEXT: $x11 = COPY [[C1]](s32)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+ ; CHECK-NEXT: $x12 = COPY [[C2]](s32)
+ ; CHECK-NEXT: $x13 = COPY [[C3]](s32)
+ ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: $x10 = COPY [[COPY]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = G_VSCALE i64 40
>From 2cb104ff80964111728c0825e2983ec8f6f3d54a Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Tue, 26 Mar 2024 06:36:59 -0700
Subject: [PATCH 7/8] fixup! use narrow ty
---
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index f116d7e5739a32..2e822a7325aebc 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -1702,14 +1702,13 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
case TargetOpcode::G_VSCALE: {
Register Dst = MI.getOperand(0).getReg();
LLT Ty = MRI.getType(Dst);
- LLT HalfTy = Ty.divide(2);
// Assume VSCALE(1) fits into a legal integer
- const APInt One(HalfTy.getSizeInBits(), 1);
- auto VScaleBase = MIRBuilder.buildVScale(HalfTy, One);
+ const APInt One(NarrowTy.getSizeInBits(), 1);
+ auto VScaleBase = MIRBuilder.buildVScale(NarrowTy, One);
auto ZExt = MIRBuilder.buildZExt(Ty, VScaleBase);
auto C = MIRBuilder.buildConstant(Ty, *MI.getOperand(1).getCImm());
- auto Res = MIRBuilder.buildMul(Dst, ZExt, C);
+ MIRBuilder.buildMul(Dst, ZExt, C);
MI.eraseFromParent();
return Legalized;
>From 7d26de3d3761d53eaae76c58411973f329be3669 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Tue, 26 Mar 2024 10:28:06 -0700
Subject: [PATCH 8/8] cleanup tests and respond to comment
---
.../CodeGen/GlobalISel/LegalizerHelper.cpp | 2 +-
.../instruction-select/rvv/vscale32.mir | 306 +++++---------
.../instruction-select/rvv/vscale64.mir | 53 ++-
.../legalizer/rvv/legalize-vscale-rv32.mir | 125 ++----
.../legalizer/rvv/legalize-vscale-rv64.mir | 20 +-
.../regbankselect/rvv/vscale-rv32.mir | 389 +-----------------
.../regbankselect/rvv/vscale-rv64.mir | 137 +-----
7 files changed, 171 insertions(+), 861 deletions(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index 2e822a7325aebc..5851f846674ab6 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -2999,7 +2999,7 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
const APInt &SrcVal = SrcMO.getCImm()->getValue();
// The CImm is always a signed value
- const APInt &Val = SrcVal.sext(WideTy.getSizeInBits());
+ const APInt Val = SrcVal.sext(WideTy.getSizeInBits());
Observer.changingInstr(MI);
SrcMO.setCImm(ConstantInt::get(Ctx, Val));
widenScalarDst(MI, WideTy);
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vscale32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vscale32.mir
index 084d5531c4597b..27dfb3fdda9db7 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vscale32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vscale32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=instruction-select \
+# RUN: llc -mtriple=riscv32 -mattr=+v,+m -run-pass=instruction-select \
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
---
@@ -14,10 +14,10 @@ body: |
; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3
; CHECK-NEXT: $x10 = COPY [[SRLI]]
; CHECK-NEXT: PseudoRET implicit $x10
- %0:gprb(s32) = G_READ_VLENB
- %1:gprb(s32) = G_CONSTANT i32 3
- %2:gprb(s32) = G_LSHR %0, %1(s32)
- $x10 = COPY %2(s32)
+ %1:gprb(s32) = G_READ_VLENB
+ %2:gprb(s32) = G_CONSTANT i32 3
+ %0:gprb(s32) = G_LSHR %1, %2(s32)
+ $x10 = COPY %0(s32)
PseudoRET implicit $x10
...
@@ -33,10 +33,10 @@ body: |
; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 2
; CHECK-NEXT: $x10 = COPY [[SRLI]]
; CHECK-NEXT: PseudoRET implicit $x10
- %0:gprb(s32) = G_READ_VLENB
- %1:gprb(s32) = G_CONSTANT i32 2
- %2:gprb(s32) = G_LSHR %0, %1(s32)
- $x10 = COPY %2(s32)
+ %1:gprb(s32) = G_READ_VLENB
+ %2:gprb(s32) = G_CONSTANT i32 2
+ %0:gprb(s32) = G_LSHR %1, %2(s32)
+ $x10 = COPY %0(s32)
PseudoRET implicit $x10
...
@@ -51,25 +51,15 @@ body: |
; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 3
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[SRLI]]
- ; CHECK-NEXT: $x11 = COPY [[ADDI]]
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
- ; CHECK-NEXT: $x10 = COPY [[COPY]]
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[SRLI]], [[ADDI]]
+ ; CHECK-NEXT: $x10 = COPY [[MUL]]
; CHECK-NEXT: PseudoRET implicit $x10
- %0:gprb(s32) = G_READ_VLENB
- %1:gprb(s32) = G_CONSTANT i32 3
- %2:gprb(s32) = G_LSHR %0, %1(s32)
- %3:gprb(s32) = G_CONSTANT i32 3
- ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %2(s32)
- $x11 = COPY %3(s32)
- PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- %4:gprb(s32) = COPY $x10
- $x10 = COPY %4(s32)
+ %1:gprb(s32) = G_READ_VLENB
+ %2:gprb(s32) = G_CONSTANT i32 3
+ %3:gprb(s32) = G_LSHR %1, %2(s32)
+ %4:gprb(s32) = G_CONSTANT i32 3
+ %0:gprb(s32) = G_MUL %3, %4
+ $x10 = COPY %0(s32)
PseudoRET implicit $x10
...
@@ -85,10 +75,10 @@ body: |
; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 1
; CHECK-NEXT: $x10 = COPY [[SRLI]]
; CHECK-NEXT: PseudoRET implicit $x10
- %0:gprb(s32) = G_READ_VLENB
- %1:gprb(s32) = G_CONSTANT i32 1
- %2:gprb(s32) = G_LSHR %0, %1(s32)
- $x10 = COPY %2(s32)
+ %1:gprb(s32) = G_READ_VLENB
+ %2:gprb(s32) = G_CONSTANT i32 1
+ %0:gprb(s32) = G_LSHR %1, %2(s32)
+ $x10 = COPY %0(s32)
PseudoRET implicit $x10
...
@@ -120,10 +110,10 @@ body: |
; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[PseudoReadVLENB]], 1
; CHECK-NEXT: $x10 = COPY [[SLLI]]
; CHECK-NEXT: PseudoRET implicit $x10
- %0:gprb(s32) = G_READ_VLENB
- %1:gprb(s32) = G_CONSTANT i32 1
- %2:gprb(s32) = G_SHL %0, %1(s32)
- $x10 = COPY %2(s32)
+ %1:gprb(s32) = G_READ_VLENB
+ %2:gprb(s32) = G_CONSTANT i32 1
+ %0:gprb(s32) = G_SHL %1, %2(s32)
+ $x10 = COPY %0(s32)
PseudoRET implicit $x10
...
@@ -137,23 +127,13 @@ body: |
; CHECK-LABEL: name: test_40_s32
; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 5
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[PseudoReadVLENB]]
- ; CHECK-NEXT: $x11 = COPY [[ADDI]]
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
- ; CHECK-NEXT: $x10 = COPY [[COPY]]
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[PseudoReadVLENB]], [[ADDI]]
+ ; CHECK-NEXT: $x10 = COPY [[MUL]]
; CHECK-NEXT: PseudoRET implicit $x10
- %0:gprb(s32) = G_READ_VLENB
- %1:gprb(s32) = G_CONSTANT i32 5
- ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+ %1:gprb(s32) = G_READ_VLENB
+ %2:gprb(s32) = G_CONSTANT i32 5
+ %0:gprb(s32) = G_MUL %1, %2
$x10 = COPY %0(s32)
- $x11 = COPY %1(s32)
- PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- %2:gprb(s32) = COPY $x10
- $x10 = COPY %2(s32)
PseudoRET implicit $x10
...
@@ -167,26 +147,16 @@ body: |
; CHECK-LABEL: name: test_1_s64
; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3
- ; CHECK-NEXT: [[PseudoReadVLENB1:%[0-9]+]]:gpr = PseudoReadVLENB
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[PseudoReadVLENB1]]
- ; CHECK-NEXT: $x11 = COPY [[COPY]]
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[SRLI]]
+ ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[SRLI]], [[ADDI]]
+ ; CHECK-NEXT: $x10 = COPY [[MUL]]
; CHECK-NEXT: PseudoRET implicit $x10
- %0:gprb(s32) = G_READ_VLENB
- %1:gprb(s32) = G_CONSTANT i32 3
- %2:gprb(s32) = G_LSHR %0, %1(s32)
- %3:gprb(s32) = G_READ_VLENB
- %4:gprb(s32) = G_CONSTANT i32 0
- ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %3(s32)
- $x11 = COPY %4(s32)
- PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %2(s32)
+ %17:gprb(s32) = G_READ_VLENB
+ %18:gprb(s32) = G_CONSTANT i32 3
+ %2:gprb(s32) = G_LSHR %17, %18(s32)
+ %15:gprb(s32) = G_CONSTANT i32 1
+ %9:gprb(s32) = G_MUL %2, %15
+ $x10 = COPY %9(s32)
PseudoRET implicit $x10
...
@@ -199,27 +169,17 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: test_2_s64
; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
- ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 2
- ; CHECK-NEXT: [[PseudoReadVLENB1:%[0-9]+]]:gpr = PseudoReadVLENB
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[PseudoReadVLENB1]]
- ; CHECK-NEXT: $x11 = COPY [[COPY]]
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[SRLI]]
+ ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3
+ ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 2
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[SRLI]], [[ADDI]]
+ ; CHECK-NEXT: $x10 = COPY [[MUL]]
; CHECK-NEXT: PseudoRET implicit $x10
- %0:gprb(s32) = G_READ_VLENB
- %1:gprb(s32) = G_CONSTANT i32 2
- %2:gprb(s32) = G_LSHR %0, %1(s32)
- %3:gprb(s32) = G_READ_VLENB
- %4:gprb(s32) = G_CONSTANT i32 0
- ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %3(s32)
- $x11 = COPY %4(s32)
- PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %2(s32)
+ %17:gprb(s32) = G_READ_VLENB
+ %18:gprb(s32) = G_CONSTANT i32 3
+ %2:gprb(s32) = G_LSHR %17, %18(s32)
+ %15:gprb(s32) = G_CONSTANT i32 2
+ %9:gprb(s32) = G_MUL %2, %15
+ $x10 = COPY %9(s32)
PseudoRET implicit $x10
...
@@ -234,39 +194,15 @@ body: |
; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 3
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[SRLI]]
- ; CHECK-NEXT: $x11 = COPY [[ADDI]]
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
- ; CHECK-NEXT: [[PseudoReadVLENB1:%[0-9]+]]:gpr = PseudoReadVLENB
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[PseudoReadVLENB1]]
- ; CHECK-NEXT: $x11 = COPY [[COPY1]]
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[COPY]]
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[SRLI]], [[ADDI]]
+ ; CHECK-NEXT: $x10 = COPY [[MUL]]
; CHECK-NEXT: PseudoRET implicit $x10
- %0:gprb(s32) = G_READ_VLENB
- %1:gprb(s32) = G_CONSTANT i32 3
- %2:gprb(s32) = G_LSHR %0, %1(s32)
- %3:gprb(s32) = G_CONSTANT i32 3
- ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %2(s32)
- $x11 = COPY %3(s32)
- PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- %4:gprb(s32) = COPY $x10
- %5:gprb(s32) = G_READ_VLENB
- %6:gprb(s32) = G_CONSTANT i32 0
- ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %5(s32)
- $x11 = COPY %6(s32)
- PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %4(s32)
+ %17:gprb(s32) = G_READ_VLENB
+ %18:gprb(s32) = G_CONSTANT i32 3
+ %2:gprb(s32) = G_LSHR %17, %18(s32)
+ %15:gprb(s32) = G_CONSTANT i32 3
+ %9:gprb(s32) = G_MUL %2, %15
+ $x10 = COPY %9(s32)
PseudoRET implicit $x10
...
@@ -279,27 +215,17 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: test_4_s64
; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
- ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 1
- ; CHECK-NEXT: [[PseudoReadVLENB1:%[0-9]+]]:gpr = PseudoReadVLENB
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[PseudoReadVLENB1]]
- ; CHECK-NEXT: $x11 = COPY [[COPY]]
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[SRLI]]
+ ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3
+ ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 4
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[SRLI]], [[ADDI]]
+ ; CHECK-NEXT: $x10 = COPY [[MUL]]
; CHECK-NEXT: PseudoRET implicit $x10
- %0:gprb(s32) = G_READ_VLENB
- %1:gprb(s32) = G_CONSTANT i32 1
- %2:gprb(s32) = G_LSHR %0, %1(s32)
- %3:gprb(s32) = G_READ_VLENB
- %4:gprb(s32) = G_CONSTANT i32 0
- ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %3(s32)
- $x11 = COPY %4(s32)
- PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %2(s32)
+ %17:gprb(s32) = G_READ_VLENB
+ %18:gprb(s32) = G_CONSTANT i32 3
+ %2:gprb(s32) = G_LSHR %17, %18(s32)
+ %15:gprb(s32) = G_CONSTANT i32 4
+ %9:gprb(s32) = G_MUL %2, %15
+ $x10 = COPY %9(s32)
PseudoRET implicit $x10
...
@@ -312,24 +238,17 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: test_8_s64
; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
- ; CHECK-NEXT: [[PseudoReadVLENB1:%[0-9]+]]:gpr = PseudoReadVLENB
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[PseudoReadVLENB1]]
- ; CHECK-NEXT: $x11 = COPY [[COPY]]
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[PseudoReadVLENB]]
+ ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3
+ ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[SRLI]], [[ADDI]]
+ ; CHECK-NEXT: $x10 = COPY [[MUL]]
; CHECK-NEXT: PseudoRET implicit $x10
- %0:gprb(s32) = G_READ_VLENB
- %1:gprb(s32) = G_READ_VLENB
- %2:gprb(s32) = G_CONSTANT i32 0
- ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %1(s32)
- $x11 = COPY %2(s32)
- PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %0(s32)
+ %17:gprb(s32) = G_READ_VLENB
+ %18:gprb(s32) = G_CONSTANT i32 3
+ %2:gprb(s32) = G_LSHR %17, %18(s32)
+ %15:gprb(s32) = G_CONSTANT i32 8
+ %9:gprb(s32) = G_MUL %2, %15
+ $x10 = COPY %9(s32)
PseudoRET implicit $x10
...
@@ -342,27 +261,17 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: test_16_s64
; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
- ; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[PseudoReadVLENB]], 1
- ; CHECK-NEXT: [[PseudoReadVLENB1:%[0-9]+]]:gpr = PseudoReadVLENB
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[PseudoReadVLENB1]]
- ; CHECK-NEXT: $x11 = COPY [[COPY]]
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[SLLI]]
+ ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3
+ ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 16
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[SRLI]], [[ADDI]]
+ ; CHECK-NEXT: $x10 = COPY [[MUL]]
; CHECK-NEXT: PseudoRET implicit $x10
- %0:gprb(s32) = G_READ_VLENB
- %1:gprb(s32) = G_CONSTANT i32 1
- %2:gprb(s32) = G_SHL %0, %1(s32)
- %3:gprb(s32) = G_READ_VLENB
- %4:gprb(s32) = G_CONSTANT i32 0
- ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %3(s32)
- $x11 = COPY %4(s32)
- PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %2(s32)
+ %17:gprb(s32) = G_READ_VLENB
+ %18:gprb(s32) = G_CONSTANT i32 3
+ %2:gprb(s32) = G_LSHR %17, %18(s32)
+ %15:gprb(s32) = G_CONSTANT i32 16
+ %9:gprb(s32) = G_MUL %2, %15
+ $x10 = COPY %9(s32)
PseudoRET implicit $x10
...
@@ -375,38 +284,17 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: test_40_s64
; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
- ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 5
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[PseudoReadVLENB]]
- ; CHECK-NEXT: $x11 = COPY [[ADDI]]
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
- ; CHECK-NEXT: [[PseudoReadVLENB1:%[0-9]+]]:gpr = PseudoReadVLENB
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[PseudoReadVLENB1]]
- ; CHECK-NEXT: $x11 = COPY [[COPY1]]
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[COPY]]
+ ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3
+ ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 40
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[SRLI]], [[ADDI]]
+ ; CHECK-NEXT: $x10 = COPY [[MUL]]
; CHECK-NEXT: PseudoRET implicit $x10
- %0:gprb(s32) = G_READ_VLENB
- %1:gprb(s32) = G_CONSTANT i32 5
- ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %0(s32)
- $x11 = COPY %1(s32)
- PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- %2:gprb(s32) = COPY $x10
- %3:gprb(s32) = G_READ_VLENB
- %4:gprb(s32) = G_CONSTANT i32 0
- ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %3(s32)
- $x11 = COPY %4(s32)
- PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %2(s32)
+ %17:gprb(s32) = G_READ_VLENB
+ %18:gprb(s32) = G_CONSTANT i32 3
+ %2:gprb(s32) = G_LSHR %17, %18(s32)
+ %15:gprb(s32) = G_CONSTANT i32 40
+ %9:gprb(s32) = G_MUL %2, %15
+ $x10 = COPY %9(s32)
PseudoRET implicit $x10
...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vscale64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vscale64.mir
index 3e480e5b8d732a..4a96be2471f8bf 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vscale64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vscale64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=instruction-select \
+# RUN: llc -mtriple=riscv64 -mattr=+v,+m -run-pass=instruction-select \
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
---
@@ -11,6 +11,25 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: test_1
; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
+ ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3
+ ; CHECK-NEXT: $x10 = COPY [[SRLI]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:gprb(s64) = G_READ_VLENB
+ %1:gprb(s64) = G_CONSTANT i64 3
+ %2:gprb(s64) = G_LSHR %0, %1(s64)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: test_2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: test_2
+ ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 2
; CHECK-NEXT: $x10 = COPY [[SRLI]]
; CHECK-NEXT: PseudoRET implicit $x10
@@ -32,24 +51,14 @@ body: |
; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 3
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[SRLI]]
- ; CHECK-NEXT: $x11 = COPY [[ADDI]]
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
- ; CHECK-NEXT: $x10 = COPY [[COPY]]
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[SRLI]], [[ADDI]]
+ ; CHECK-NEXT: $x10 = COPY [[MUL]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:gprb(s64) = G_READ_VLENB
%1:gprb(s64) = G_CONSTANT i64 3
%2:gprb(s64) = G_LSHR %0, %1(s64)
%3:gprb(s64) = G_CONSTANT i64 3
- ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %2(s64)
- $x11 = COPY %3(s64)
- PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- %4:gprb(s64) = COPY $x10
+ %4:gprb(s64) = G_MUL %2, %3
$x10 = COPY %4(s64)
PseudoRET implicit $x10
@@ -118,22 +127,12 @@ body: |
; CHECK-LABEL: name: test_40
; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 5
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[PseudoReadVLENB]]
- ; CHECK-NEXT: $x11 = COPY [[ADDI]]
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
- ; CHECK-NEXT: $x10 = COPY [[COPY]]
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[PseudoReadVLENB]], [[ADDI]]
+ ; CHECK-NEXT: $x10 = COPY [[MUL]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:gprb(s64) = G_READ_VLENB
%1:gprb(s64) = G_CONSTANT i64 5
- ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %0(s64)
- $x11 = COPY %1(s64)
- PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- %2:gprb(s64) = COPY $x10
+ %2:gprb(s64) = G_MUL %0, %1
$x10 = COPY %2(s64)
PseudoRET implicit $x10
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-vscale-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-vscale-rv32.mir
index 8ed90439803152..899f7955a27302 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-vscale-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-vscale-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s
+# RUN: llc -mtriple=riscv32 -mattr=+v,+m -run-pass=legalizer %s -o - | FileCheck %s
---
name: test_1_s32
@@ -41,13 +41,8 @@ body: |
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
- ; CHECK-NEXT: $x11 = COPY [[C1]](s32)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
- ; CHECK-NEXT: $x10 = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[LSHR]], [[C1]]
+ ; CHECK-NEXT: $x10 = COPY [[MUL]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s32) = G_VSCALE i32 3
$x10 = COPY %0
@@ -104,13 +99,8 @@ body: |
; CHECK-LABEL: name: test_40_s32
; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[READ_VLENB]](s32)
- ; CHECK-NEXT: $x11 = COPY [[C]](s32)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
- ; CHECK-NEXT: $x10 = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[READ_VLENB]], [[C]]
+ ; CHECK-NEXT: $x10 = COPY [[MUL]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s32) = G_VSCALE i32 40
$x10 = COPY %0
@@ -125,18 +115,9 @@ body: |
; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
- ; CHECK-NEXT: $x11 = COPY [[C1]](s32)
- ; CHECK-NEXT: $x12 = COPY [[C2]](s32)
- ; CHECK-NEXT: $x13 = COPY [[C3]](s32)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
- ; CHECK-NEXT: $x10 = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[LSHR]], [[C1]]
+ ; CHECK-NEXT: $x10 = COPY [[MUL]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = G_VSCALE i64 1
%1:_(s32) = G_TRUNC %0
@@ -151,18 +132,9 @@ body: |
; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
- ; CHECK-NEXT: $x11 = COPY [[C1]](s32)
- ; CHECK-NEXT: $x12 = COPY [[C2]](s32)
- ; CHECK-NEXT: $x13 = COPY [[C3]](s32)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
- ; CHECK-NEXT: $x10 = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[LSHR]], [[C1]]
+ ; CHECK-NEXT: $x10 = COPY [[MUL]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = G_VSCALE i64 2
%1:_(s32) = G_TRUNC %0
@@ -177,18 +149,9 @@ body: |
; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
- ; CHECK-NEXT: $x11 = COPY [[C1]](s32)
- ; CHECK-NEXT: $x12 = COPY [[C2]](s32)
- ; CHECK-NEXT: $x13 = COPY [[C3]](s32)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
- ; CHECK-NEXT: $x10 = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[LSHR]], [[C1]]
+ ; CHECK-NEXT: $x10 = COPY [[MUL]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = G_VSCALE i64 3
%1:_(s32) = G_TRUNC %0
@@ -203,18 +166,9 @@ body: |
; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
- ; CHECK-NEXT: $x11 = COPY [[C1]](s32)
- ; CHECK-NEXT: $x12 = COPY [[C2]](s32)
- ; CHECK-NEXT: $x13 = COPY [[C3]](s32)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
- ; CHECK-NEXT: $x10 = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[LSHR]], [[C1]]
+ ; CHECK-NEXT: $x10 = COPY [[MUL]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = G_VSCALE i64 4
%1:_(s32) = G_TRUNC %0
@@ -229,18 +183,9 @@ body: |
; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
- ; CHECK-NEXT: $x11 = COPY [[C1]](s32)
- ; CHECK-NEXT: $x12 = COPY [[C2]](s32)
- ; CHECK-NEXT: $x13 = COPY [[C3]](s32)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
- ; CHECK-NEXT: $x10 = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[LSHR]], [[C1]]
+ ; CHECK-NEXT: $x10 = COPY [[MUL]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = G_VSCALE i64 8
%1:_(s32) = G_TRUNC %0
@@ -255,18 +200,9 @@ body: |
; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
- ; CHECK-NEXT: $x11 = COPY [[C1]](s32)
- ; CHECK-NEXT: $x12 = COPY [[C2]](s32)
- ; CHECK-NEXT: $x13 = COPY [[C3]](s32)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
- ; CHECK-NEXT: $x10 = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[LSHR]], [[C1]]
+ ; CHECK-NEXT: $x10 = COPY [[MUL]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = G_VSCALE i64 16
%1:_(s32) = G_TRUNC %0
@@ -281,18 +217,9 @@ body: |
; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 40
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
- ; CHECK-NEXT: $x11 = COPY [[C1]](s32)
- ; CHECK-NEXT: $x12 = COPY [[C2]](s32)
- ; CHECK-NEXT: $x13 = COPY [[C3]](s32)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
- ; CHECK-NEXT: $x10 = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 40
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[LSHR]], [[C1]]
+ ; CHECK-NEXT: $x10 = COPY [[MUL]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = G_VSCALE i64 40
%1:_(s32) = G_TRUNC %0
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-vscale-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-vscale-rv64.mir
index 3e140a5ef72a84..c0453a04a18158 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-vscale-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-vscale-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s
+# RUN: llc -mtriple=riscv64 -mattr=+v,+m -run-pass=legalizer %s -o - | FileCheck %s
---
name: test_1
@@ -41,13 +41,8 @@ body: |
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[READ_VLENB]], [[C]](s64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[LSHR]](s64)
- ; CHECK-NEXT: $x11 = COPY [[C1]](s64)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; CHECK-NEXT: $x10 = COPY [[COPY]](s64)
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[LSHR]], [[C1]]
+ ; CHECK-NEXT: $x10 = COPY [[MUL]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = G_VSCALE i64 3
$x10 = COPY %0
@@ -104,13 +99,8 @@ body: |
; CHECK-LABEL: name: test_40
; CHECK: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[READ_VLENB]](s64)
- ; CHECK-NEXT: $x11 = COPY [[C]](s64)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
- ; CHECK-NEXT: $x10 = COPY [[COPY]](s64)
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[READ_VLENB]], [[C]]
+ ; CHECK-NEXT: $x10 = COPY [[MUL]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = G_VSCALE i64 40
$x10 = COPY %0
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv32.mir
index 2bc33f94978ce6..ae3bb0a18020d3 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv32.mir
@@ -1,15 +1,15 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \
# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck %s
---
-name: test_1_s32
+name: test_s32
legalized: true
tracksRegLiveness: true
body: |
bb.0.entry:
- ; CHECK-LABEL: name: test_1_s32
+ ; CHECK-LABEL: name: test_s32
; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s32) = G_READ_VLENB
; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 3
; CHECK-NEXT: [[LSHR:%[0-9]+]]:gprb(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
@@ -23,387 +23,26 @@ body: |
...
---
-name: test_2_s32
+name: test_s64
legalized: true
tracksRegLiveness: true
body: |
bb.0.entry:
- ; CHECK-LABEL: name: test_2_s32
- ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s32) = G_READ_VLENB
- ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 2
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:gprb(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
- ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
- ; CHECK-NEXT: PseudoRET implicit $x10
- %1:_(s32) = G_READ_VLENB
- %2:_(s32) = G_CONSTANT i32 2
- %0:_(s32) = G_LSHR %1, %2(s32)
- $x10 = COPY %0(s32)
- PseudoRET implicit $x10
-
-...
----
-name: test_3_s32
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- ; CHECK-LABEL: name: test_3_s32
- ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s32) = G_READ_VLENB
- ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 3
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:gprb(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 3
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
- ; CHECK-NEXT: $x11 = COPY [[C1]](s32)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
- ; CHECK-NEXT: $x10 = COPY [[COPY]](s32)
- ; CHECK-NEXT: PseudoRET implicit $x10
- %1:_(s32) = G_READ_VLENB
- %2:_(s32) = G_CONSTANT i32 3
- %3:_(s32) = G_LSHR %1, %2(s32)
- %4:_(s32) = G_CONSTANT i32 3
- ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %3(s32)
- $x11 = COPY %4(s32)
- PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- %0:_(s32) = COPY $x10
- $x10 = COPY %0(s32)
- PseudoRET implicit $x10
-
-...
----
-name: test_4_s32
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- ; CHECK-LABEL: name: test_4_s32
- ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s32) = G_READ_VLENB
- ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:gprb(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
- ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
- ; CHECK-NEXT: PseudoRET implicit $x10
- %1:_(s32) = G_READ_VLENB
- %2:_(s32) = G_CONSTANT i32 1
- %0:_(s32) = G_LSHR %1, %2(s32)
- $x10 = COPY %0(s32)
- PseudoRET implicit $x10
-
-...
----
-name: test_8_s32
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- ; CHECK-LABEL: name: test_8_s32
- ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s32) = G_READ_VLENB
- ; CHECK-NEXT: $x10 = COPY [[READ_VLENB]](s32)
- ; CHECK-NEXT: PseudoRET implicit $x10
- %0:_(s32) = G_READ_VLENB
- $x10 = COPY %0(s32)
- PseudoRET implicit $x10
-
-...
----
-name: test_16_s32
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- ; CHECK-LABEL: name: test_16_s32
- ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s32) = G_READ_VLENB
- ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:gprb(s32) = G_SHL [[READ_VLENB]], [[C]](s32)
- ; CHECK-NEXT: $x10 = COPY [[SHL]](s32)
- ; CHECK-NEXT: PseudoRET implicit $x10
- %1:_(s32) = G_READ_VLENB
- %2:_(s32) = G_CONSTANT i32 1
- %0:_(s32) = G_SHL %1, %2(s32)
- $x10 = COPY %0(s32)
- PseudoRET implicit $x10
-
-...
----
-name: test_40_s32
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- ; CHECK-LABEL: name: test_40_s32
- ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s32) = G_READ_VLENB
- ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 5
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[READ_VLENB]](s32)
- ; CHECK-NEXT: $x11 = COPY [[C]](s32)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
- ; CHECK-NEXT: $x10 = COPY [[COPY]](s32)
- ; CHECK-NEXT: PseudoRET implicit $x10
- %1:_(s32) = G_READ_VLENB
- %2:_(s32) = G_CONSTANT i32 5
- ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %1(s32)
- $x11 = COPY %2(s32)
- PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- %0:_(s32) = COPY $x10
- $x10 = COPY %0(s32)
- PseudoRET implicit $x10
-
-...
----
-name: test_1_s64
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- ; CHECK-LABEL: name: test_1_s64
+ ; CHECK-LABEL: name: test_s64
; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s32) = G_READ_VLENB
; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 3
; CHECK-NEXT: [[LSHR:%[0-9]+]]:gprb(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
- ; CHECK-NEXT: [[READ_VLENB1:%[0-9]+]]:gprb(s32) = G_READ_VLENB
- ; CHECK-NEXT: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[READ_VLENB1]](s32)
- ; CHECK-NEXT: $x11 = COPY [[C1]](s32)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
- ; CHECK-NEXT: PseudoRET implicit $x10
- %6:_(s32) = G_READ_VLENB
- %7:_(s32) = G_CONSTANT i32 3
- %2:_(s32) = G_LSHR %6, %7(s32)
- %4:_(s32) = G_READ_VLENB
- %5:_(s32) = G_CONSTANT i32 0
- ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %4(s32)
- $x11 = COPY %5(s32)
- PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %2(s32)
- PseudoRET implicit $x10
-
-...
----
-name: test_2_s64
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- ; CHECK-LABEL: name: test_2_s64
- ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s32) = G_READ_VLENB
- ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 2
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:gprb(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
- ; CHECK-NEXT: [[READ_VLENB1:%[0-9]+]]:gprb(s32) = G_READ_VLENB
- ; CHECK-NEXT: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[READ_VLENB1]](s32)
- ; CHECK-NEXT: $x11 = COPY [[C1]](s32)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
- ; CHECK-NEXT: PseudoRET implicit $x10
- %6:_(s32) = G_READ_VLENB
- %7:_(s32) = G_CONSTANT i32 2
- %2:_(s32) = G_LSHR %6, %7(s32)
- %4:_(s32) = G_READ_VLENB
- %5:_(s32) = G_CONSTANT i32 0
- ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %4(s32)
- $x11 = COPY %5(s32)
- PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %2(s32)
- PseudoRET implicit $x10
-
-...
----
-name: test_3_s64
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- ; CHECK-LABEL: name: test_3_s64
- ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s32) = G_READ_VLENB
- ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 3
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:gprb(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 3
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
- ; CHECK-NEXT: $x11 = COPY [[C1]](s32)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
- ; CHECK-NEXT: [[READ_VLENB1:%[0-9]+]]:gprb(s32) = G_READ_VLENB
- ; CHECK-NEXT: [[C2:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[READ_VLENB1]](s32)
- ; CHECK-NEXT: $x11 = COPY [[C2]](s32)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[COPY]](s32)
- ; CHECK-NEXT: PseudoRET implicit $x10
- %6:_(s32) = G_READ_VLENB
- %7:_(s32) = G_CONSTANT i32 3
- %8:_(s32) = G_LSHR %6, %7(s32)
- %9:_(s32) = G_CONSTANT i32 3
- ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %8(s32)
- $x11 = COPY %9(s32)
- PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- %2:_(s32) = COPY $x10
- %4:_(s32) = G_READ_VLENB
- %5:_(s32) = G_CONSTANT i32 0
- ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %4(s32)
- $x11 = COPY %5(s32)
- PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %2(s32)
- PseudoRET implicit $x10
-
-...
----
-name: test_4_s64
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- ; CHECK-LABEL: name: test_4_s64
- ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s32) = G_READ_VLENB
- ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:gprb(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
- ; CHECK-NEXT: [[READ_VLENB1:%[0-9]+]]:gprb(s32) = G_READ_VLENB
- ; CHECK-NEXT: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[READ_VLENB1]](s32)
- ; CHECK-NEXT: $x11 = COPY [[C1]](s32)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:gprb(s32) = G_MUL [[LSHR]], [[C1]]
+ ; CHECK-NEXT: $x10 = COPY [[MUL]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
- %6:_(s32) = G_READ_VLENB
- %7:_(s32) = G_CONSTANT i32 1
- %2:_(s32) = G_LSHR %6, %7(s32)
- %4:_(s32) = G_READ_VLENB
- %5:_(s32) = G_CONSTANT i32 0
- ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %4(s32)
- $x11 = COPY %5(s32)
- PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %2(s32)
+ %17:_(s32) = G_READ_VLENB
+ %18:_(s32) = G_CONSTANT i32 3
+ %2:_(s32) = G_LSHR %17, %18(s32)
+ %15:_(s32) = G_CONSTANT i32 1
+ %9:_(s32) = G_MUL %2, %15
+ $x10 = COPY %9(s32)
PseudoRET implicit $x10
...
----
-name: test_8_s64
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- ; CHECK-LABEL: name: test_8_s64
- ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s32) = G_READ_VLENB
- ; CHECK-NEXT: [[READ_VLENB1:%[0-9]+]]:gprb(s32) = G_READ_VLENB
- ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[READ_VLENB1]](s32)
- ; CHECK-NEXT: $x11 = COPY [[C]](s32)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[READ_VLENB]](s32)
- ; CHECK-NEXT: PseudoRET implicit $x10
- %2:_(s32) = G_READ_VLENB
- %4:_(s32) = G_READ_VLENB
- %5:_(s32) = G_CONSTANT i32 0
- ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %4(s32)
- $x11 = COPY %5(s32)
- PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %2(s32)
- PseudoRET implicit $x10
-...
----
-name: test_16_s64
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- ; CHECK-LABEL: name: test_16_s64
- ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s32) = G_READ_VLENB
- ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:gprb(s32) = G_SHL [[READ_VLENB]], [[C]](s32)
- ; CHECK-NEXT: [[READ_VLENB1:%[0-9]+]]:gprb(s32) = G_READ_VLENB
- ; CHECK-NEXT: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[READ_VLENB1]](s32)
- ; CHECK-NEXT: $x11 = COPY [[C1]](s32)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[SHL]](s32)
- ; CHECK-NEXT: PseudoRET implicit $x10
- %6:_(s32) = G_READ_VLENB
- %7:_(s32) = G_CONSTANT i32 1
- %2:_(s32) = G_SHL %6, %7(s32)
- %4:_(s32) = G_READ_VLENB
- %5:_(s32) = G_CONSTANT i32 0
- ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %4(s32)
- $x11 = COPY %5(s32)
- PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %2(s32)
- PseudoRET implicit $x10
-
-...
----
-name: test_40_s64
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- ; CHECK-LABEL: name: test_40_s64
- ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s32) = G_READ_VLENB
- ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 5
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[READ_VLENB]](s32)
- ; CHECK-NEXT: $x11 = COPY [[C]](s32)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
- ; CHECK-NEXT: [[READ_VLENB1:%[0-9]+]]:gprb(s32) = G_READ_VLENB
- ; CHECK-NEXT: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[READ_VLENB1]](s32)
- ; CHECK-NEXT: $x11 = COPY [[C1]](s32)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[COPY]](s32)
- ; CHECK-NEXT: PseudoRET implicit $x10
- %6:_(s32) = G_READ_VLENB
- %7:_(s32) = G_CONSTANT i32 5
- ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %6(s32)
- $x11 = COPY %7(s32)
- PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- %2:_(s32) = COPY $x10
- %4:_(s32) = G_READ_VLENB
- %5:_(s32) = G_CONSTANT i32 0
- ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %4(s32)
- $x11 = COPY %5(s32)
- PseudoCALL target-flags(riscv-call) &__mulsi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %2(s32)
- PseudoRET implicit $x10
-
-...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv64.mir
index 45a5a1d84646eb..a7446d976f2574 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv64.mir
@@ -4,12 +4,12 @@
# RUN: -o - | FileCheck %s
---
-name: test_1
+name: test
legalized: true
tracksRegLiveness: true
body: |
bb.0.entry:
- ; CHECK-LABEL: name: test_1
+ ; CHECK-LABEL: name: test
; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s64) = G_READ_VLENB
; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 3
; CHECK-NEXT: [[LSHR:%[0-9]+]]:gprb(s64) = G_LSHR [[READ_VLENB]], [[C]](s64)
@@ -22,137 +22,4 @@ body: |
PseudoRET implicit $x10
...
----
-name: test_2
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- ; CHECK-LABEL: name: test_2
- ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s64) = G_READ_VLENB
- ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:gprb(s64) = G_LSHR [[READ_VLENB]], [[C]](s64)
- ; CHECK-NEXT: $x10 = COPY [[LSHR]](s64)
- ; CHECK-NEXT: PseudoRET implicit $x10
- %1:_(s64) = G_READ_VLENB
- %2:_(s64) = G_CONSTANT i64 2
- %0:_(s64) = G_LSHR %1, %2(s64)
- $x10 = COPY %0(s64)
- PseudoRET implicit $x10
-
-...
----
-name: test_3
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- ; CHECK-LABEL: name: test_3
- ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s64) = G_READ_VLENB
- ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 3
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:gprb(s64) = G_LSHR [[READ_VLENB]], [[C]](s64)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 3
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[LSHR]](s64)
- ; CHECK-NEXT: $x11 = COPY [[C1]](s64)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
- ; CHECK-NEXT: $x10 = COPY [[COPY]](s64)
- ; CHECK-NEXT: PseudoRET implicit $x10
- %1:_(s64) = G_READ_VLENB
- %2:_(s64) = G_CONSTANT i64 3
- %3:_(s64) = G_LSHR %1, %2(s64)
- %4:_(s64) = G_CONSTANT i64 3
- ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %3(s64)
- $x11 = COPY %4(s64)
- PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- %0:_(s64) = COPY $x10
- $x10 = COPY %0(s64)
- PseudoRET implicit $x10
-
-...
----
-name: test_4
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- ; CHECK-LABEL: name: test_4
- ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s64) = G_READ_VLENB
- ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:gprb(s64) = G_LSHR [[READ_VLENB]], [[C]](s64)
- ; CHECK-NEXT: $x10 = COPY [[LSHR]](s64)
- ; CHECK-NEXT: PseudoRET implicit $x10
- %1:_(s64) = G_READ_VLENB
- %2:_(s64) = G_CONSTANT i64 1
- %0:_(s64) = G_LSHR %1, %2(s64)
- $x10 = COPY %0(s64)
- PseudoRET implicit $x10
-
-...
----
-name: test_8
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- ; CHECK-LABEL: name: test_8
- ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s64) = G_READ_VLENB
- ; CHECK-NEXT: $x10 = COPY [[READ_VLENB]](s64)
- ; CHECK-NEXT: PseudoRET implicit $x10
- %0:_(s64) = G_READ_VLENB
- $x10 = COPY %0(s64)
- PseudoRET implicit $x10
-
-...
----
-name: test_16
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- ; CHECK-LABEL: name: test_16
- ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s64) = G_READ_VLENB
- ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:gprb(s64) = G_SHL [[READ_VLENB]], [[C]](s64)
- ; CHECK-NEXT: $x10 = COPY [[SHL]](s64)
- ; CHECK-NEXT: PseudoRET implicit $x10
- %1:_(s64) = G_READ_VLENB
- %2:_(s64) = G_CONSTANT i64 1
- %0:_(s64) = G_SHL %1, %2(s64)
- $x10 = COPY %0(s64)
- PseudoRET implicit $x10
-
-...
----
-name: test_40
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- ; CHECK-LABEL: name: test_40
- ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s64) = G_READ_VLENB
- ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 5
- ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: $x10 = COPY [[READ_VLENB]](s64)
- ; CHECK-NEXT: $x11 = COPY [[C]](s64)
- ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
- ; CHECK-NEXT: $x10 = COPY [[COPY]](s64)
- ; CHECK-NEXT: PseudoRET implicit $x10
- %1:_(s64) = G_READ_VLENB
- %2:_(s64) = G_CONSTANT i64 5
- ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
- $x10 = COPY %1(s64)
- $x11 = COPY %2(s64)
- PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
- ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
- %0:_(s64) = COPY $x10
- $x10 = COPY %0(s64)
- PseudoRET implicit $x10
-...
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