[llvm] {RISCV][GISEL] IRTranslator for Scalable Vector Store (PR #86699)
Jiahan Xie via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 26 10:18:26 PDT 2024
https://github.com/jiahanxie353 created https://github.com/llvm/llvm-project/pull/86699
This patch works on IR translating scalable vector store
>From 9b8dda0de9f75cd6a26e63e6553cbd9263e7fab7 Mon Sep 17 00:00:00 2001
From: jiahanxie353 <jx353 at cornell.edu>
Date: Tue, 26 Mar 2024 13:15:35 -0400
Subject: [PATCH] irtranslate scalable vector load
---
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 2 +-
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 3 +-
.../GlobalISel/irtranslator/vec-store.ll | 488 ++++++++++++++++++
3 files changed, 491 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-store.ll
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index ef95ceec18a171..3e62bf88739c04 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -1413,7 +1413,7 @@ bool IRTranslator::translateLoad(const User &U, MachineIRBuilder &MIRBuilder) {
bool IRTranslator::translateStore(const User &U, MachineIRBuilder &MIRBuilder) {
const StoreInst &SI = cast<StoreInst>(U);
- if (DL->getTypeStoreSize(SI.getValueOperand()->getType()) == 0)
+ if (DL->getTypeStoreSize(SI.getValueOperand()->getType()).isZero())
return true;
ArrayRef<Register> Vals = getOrCreateVRegs(*SI.getValueOperand());
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index ca78648c6aa9d8..fd8b9d64bd6363 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -21005,7 +21005,8 @@ bool RISCVTargetLowering::fallBackToDAGISel(const Instruction &Inst) const {
if (Op == Instruction::Add || Op == Instruction::Sub ||
Op == Instruction::And || Op == Instruction::Or ||
Op == Instruction::Xor || Op == Instruction::InsertElement ||
- Op == Instruction::ShuffleVector || Op == Instruction::Load)
+ Op == Instruction::ShuffleVector || Op == Instruction::Load ||
+ Op == Instruction::Store)
return false;
if (Inst.getType()->isScalableTy())
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-store.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-store.ll
new file mode 100644
index 00000000000000..0c9b9fb485f745
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-store.ll
@@ -0,0 +1,488 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+v -global-isel -stop-after=irtranslator -verify-machineinstrs < %s | FileCheck -check-prefixes=RV32 %s
+; RUN: llc -mtriple=riscv64 -mattr=+v -global-isel -stop-after=irtranslator -verify-machineinstrs < %s | FileCheck -check-prefixes=RV64 %s
+
+define void @vstore_nx1i8(ptr %pa, <vscale x 1 x i8> %b) {
+ ; RV32-LABEL: name: vstore_nx1i8
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $v8, $x10
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 1 x s8>) = COPY $v8
+ ; RV32-NEXT: G_STORE [[COPY1]](<vscale x 1 x s8>), [[COPY]](p0) :: (store (<vscale x 1 x s8>) into %ir.pa)
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: vstore_nx1i8
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $v8, $x10
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 1 x s8>) = COPY $v8
+ ; RV64-NEXT: G_STORE [[COPY1]](<vscale x 1 x s8>), [[COPY]](p0) :: (store (<vscale x 1 x s8>) into %ir.pa)
+ ; RV64-NEXT: PseudoRET
+ store <vscale x 1 x i8> %b, ptr %pa
+ ret void
+}
+
+define void @vstore_nx2i8(ptr %pa, <vscale x 2 x i8> %b) {
+ ; RV32-LABEL: name: vstore_nx2i8
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $v8, $x10
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s8>) = COPY $v8
+ ; RV32-NEXT: G_STORE [[COPY1]](<vscale x 2 x s8>), [[COPY]](p0) :: (store (<vscale x 2 x s8>) into %ir.pa)
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: vstore_nx2i8
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $v8, $x10
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s8>) = COPY $v8
+ ; RV64-NEXT: G_STORE [[COPY1]](<vscale x 2 x s8>), [[COPY]](p0) :: (store (<vscale x 2 x s8>) into %ir.pa)
+ ; RV64-NEXT: PseudoRET
+ store <vscale x 2 x i8> %b, ptr %pa
+ ret void
+}
+
+define void @vstore_nx4i8(ptr %pa, <vscale x 4 x i8> %b) {
+ ; RV32-LABEL: name: vstore_nx4i8
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $v8, $x10
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s8>) = COPY $v8
+ ; RV32-NEXT: G_STORE [[COPY1]](<vscale x 4 x s8>), [[COPY]](p0) :: (store (<vscale x 4 x s8>) into %ir.pa)
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: vstore_nx4i8
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $v8, $x10
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s8>) = COPY $v8
+ ; RV64-NEXT: G_STORE [[COPY1]](<vscale x 4 x s8>), [[COPY]](p0) :: (store (<vscale x 4 x s8>) into %ir.pa)
+ ; RV64-NEXT: PseudoRET
+ store <vscale x 4 x i8> %b, ptr %pa
+ ret void
+}
+
+define void @vstore_nx8i8(ptr %pa, <vscale x 8 x i8> %b) {
+ ; RV32-LABEL: name: vstore_nx8i8
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $v8, $x10
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x s8>) = COPY $v8
+ ; RV32-NEXT: G_STORE [[COPY1]](<vscale x 8 x s8>), [[COPY]](p0) :: (store (<vscale x 8 x s8>) into %ir.pa)
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: vstore_nx8i8
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $v8, $x10
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x s8>) = COPY $v8
+ ; RV64-NEXT: G_STORE [[COPY1]](<vscale x 8 x s8>), [[COPY]](p0) :: (store (<vscale x 8 x s8>) into %ir.pa)
+ ; RV64-NEXT: PseudoRET
+ store <vscale x 8 x i8> %b, ptr %pa
+ ret void
+}
+
+define void @vstore_nx16i8(ptr %pa, <vscale x 16 x i8> %b) {
+ ; RV32-LABEL: name: vstore_nx16i8
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $x10, $v8m2
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $v8m2
+ ; RV32-NEXT: G_STORE [[COPY1]](<vscale x 16 x s8>), [[COPY]](p0) :: (store (<vscale x 16 x s8>) into %ir.pa)
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: vstore_nx16i8
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $x10, $v8m2
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $v8m2
+ ; RV64-NEXT: G_STORE [[COPY1]](<vscale x 16 x s8>), [[COPY]](p0) :: (store (<vscale x 16 x s8>) into %ir.pa)
+ ; RV64-NEXT: PseudoRET
+ store <vscale x 16 x i8> %b, ptr %pa
+ ret void
+}
+
+define void @vstore_nx32i8(ptr %pa, <vscale x 32 x i8> %b) {
+ ; RV32-LABEL: name: vstore_nx32i8
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $x10, $v8m4
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 32 x s8>) = COPY $v8m4
+ ; RV32-NEXT: G_STORE [[COPY1]](<vscale x 32 x s8>), [[COPY]](p0) :: (store (<vscale x 32 x s8>) into %ir.pa)
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: vstore_nx32i8
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $x10, $v8m4
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 32 x s8>) = COPY $v8m4
+ ; RV64-NEXT: G_STORE [[COPY1]](<vscale x 32 x s8>), [[COPY]](p0) :: (store (<vscale x 32 x s8>) into %ir.pa)
+ ; RV64-NEXT: PseudoRET
+ store <vscale x 32 x i8> %b, ptr %pa
+ ret void
+}
+
+define void @vstore_nx64i8(ptr %pa, <vscale x 64 x i8> %b) {
+ ; RV32-LABEL: name: vstore_nx64i8
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $x10, $v8m8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 64 x s8>) = COPY $v8m8
+ ; RV32-NEXT: G_STORE [[COPY1]](<vscale x 64 x s8>), [[COPY]](p0) :: (store (<vscale x 64 x s8>) into %ir.pa)
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: vstore_nx64i8
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $x10, $v8m8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 64 x s8>) = COPY $v8m8
+ ; RV64-NEXT: G_STORE [[COPY1]](<vscale x 64 x s8>), [[COPY]](p0) :: (store (<vscale x 64 x s8>) into %ir.pa)
+ ; RV64-NEXT: PseudoRET
+ store <vscale x 64 x i8> %b, ptr %pa
+ ret void
+}
+
+define void @vstore_nx1i16(ptr %pa, <vscale x 1 x i16> %b) {
+ ; RV32-LABEL: name: vstore_nx1i16
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $v8, $x10
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 1 x s16>) = COPY $v8
+ ; RV32-NEXT: G_STORE [[COPY1]](<vscale x 1 x s16>), [[COPY]](p0) :: (store (<vscale x 1 x s16>) into %ir.pa)
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: vstore_nx1i16
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $v8, $x10
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 1 x s16>) = COPY $v8
+ ; RV64-NEXT: G_STORE [[COPY1]](<vscale x 1 x s16>), [[COPY]](p0) :: (store (<vscale x 1 x s16>) into %ir.pa)
+ ; RV64-NEXT: PseudoRET
+ store <vscale x 1 x i16> %b, ptr %pa
+ ret void
+}
+
+define void @vstore_nx2i16(ptr %pa, <vscale x 2 x i16> %b) {
+ ; RV32-LABEL: name: vstore_nx2i16
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $v8, $x10
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s16>) = COPY $v8
+ ; RV32-NEXT: G_STORE [[COPY1]](<vscale x 2 x s16>), [[COPY]](p0) :: (store (<vscale x 2 x s16>) into %ir.pa)
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: vstore_nx2i16
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $v8, $x10
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s16>) = COPY $v8
+ ; RV64-NEXT: G_STORE [[COPY1]](<vscale x 2 x s16>), [[COPY]](p0) :: (store (<vscale x 2 x s16>) into %ir.pa)
+ ; RV64-NEXT: PseudoRET
+ store <vscale x 2 x i16> %b, ptr %pa
+ ret void
+}
+
+define void @vstore_nx4i16(ptr %pa, <vscale x 4 x i16> %b) {
+ ; RV32-LABEL: name: vstore_nx4i16
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $v8, $x10
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v8
+ ; RV32-NEXT: G_STORE [[COPY1]](<vscale x 4 x s16>), [[COPY]](p0) :: (store (<vscale x 4 x s16>) into %ir.pa)
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: vstore_nx4i16
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $v8, $x10
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v8
+ ; RV64-NEXT: G_STORE [[COPY1]](<vscale x 4 x s16>), [[COPY]](p0) :: (store (<vscale x 4 x s16>) into %ir.pa)
+ ; RV64-NEXT: PseudoRET
+ store <vscale x 4 x i16> %b, ptr %pa
+ ret void
+}
+
+define void @vstore_nx8i16(ptr %pa, <vscale x 8 x i16> %b) {
+ ; RV32-LABEL: name: vstore_nx8i16
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $x10, $v8m2
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $v8m2
+ ; RV32-NEXT: G_STORE [[COPY1]](<vscale x 8 x s16>), [[COPY]](p0) :: (store (<vscale x 8 x s16>) into %ir.pa)
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: vstore_nx8i16
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $x10, $v8m2
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $v8m2
+ ; RV64-NEXT: G_STORE [[COPY1]](<vscale x 8 x s16>), [[COPY]](p0) :: (store (<vscale x 8 x s16>) into %ir.pa)
+ ; RV64-NEXT: PseudoRET
+ store <vscale x 8 x i16> %b, ptr %pa
+ ret void
+}
+
+define void @vstore_nx16i16(ptr %pa, <vscale x 16 x i16> %b) {
+ ; RV32-LABEL: name: vstore_nx16i16
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $x10, $v8m4
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 16 x s16>) = COPY $v8m4
+ ; RV32-NEXT: G_STORE [[COPY1]](<vscale x 16 x s16>), [[COPY]](p0) :: (store (<vscale x 16 x s16>) into %ir.pa)
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: vstore_nx16i16
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $x10, $v8m4
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 16 x s16>) = COPY $v8m4
+ ; RV64-NEXT: G_STORE [[COPY1]](<vscale x 16 x s16>), [[COPY]](p0) :: (store (<vscale x 16 x s16>) into %ir.pa)
+ ; RV64-NEXT: PseudoRET
+ store <vscale x 16 x i16> %b, ptr %pa
+ ret void
+}
+
+define void @vstore_nx32i16(ptr %pa, <vscale x 32 x i16> %b) {
+ ; RV32-LABEL: name: vstore_nx32i16
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $x10, $v8m8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 32 x s16>) = COPY $v8m8
+ ; RV32-NEXT: G_STORE [[COPY1]](<vscale x 32 x s16>), [[COPY]](p0) :: (store (<vscale x 32 x s16>) into %ir.pa)
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: vstore_nx32i16
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $x10, $v8m8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 32 x s16>) = COPY $v8m8
+ ; RV64-NEXT: G_STORE [[COPY1]](<vscale x 32 x s16>), [[COPY]](p0) :: (store (<vscale x 32 x s16>) into %ir.pa)
+ ; RV64-NEXT: PseudoRET
+ store <vscale x 32 x i16> %b, ptr %pa
+ ret void
+}
+
+define void @vstore_nx1i32(ptr %pa, <vscale x 1 x i32> %b) {
+ ; RV32-LABEL: name: vstore_nx1i32
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $v8, $x10
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 1 x s32>) = COPY $v8
+ ; RV32-NEXT: G_STORE [[COPY1]](<vscale x 1 x s32>), [[COPY]](p0) :: (store (<vscale x 1 x s32>) into %ir.pa)
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: vstore_nx1i32
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $v8, $x10
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 1 x s32>) = COPY $v8
+ ; RV64-NEXT: G_STORE [[COPY1]](<vscale x 1 x s32>), [[COPY]](p0) :: (store (<vscale x 1 x s32>) into %ir.pa)
+ ; RV64-NEXT: PseudoRET
+ store <vscale x 1 x i32> %b, ptr %pa
+ ret void
+}
+
+define void @vstore_nx2i32(ptr %pa, <vscale x 2 x i32> %b) {
+ ; RV32-LABEL: name: vstore_nx2i32
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $v8, $x10
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s32>) = COPY $v8
+ ; RV32-NEXT: G_STORE [[COPY1]](<vscale x 2 x s32>), [[COPY]](p0) :: (store (<vscale x 2 x s32>) into %ir.pa)
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: vstore_nx2i32
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $v8, $x10
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s32>) = COPY $v8
+ ; RV64-NEXT: G_STORE [[COPY1]](<vscale x 2 x s32>), [[COPY]](p0) :: (store (<vscale x 2 x s32>) into %ir.pa)
+ ; RV64-NEXT: PseudoRET
+ store <vscale x 2 x i32> %b, ptr %pa
+ ret void
+}
+
+define void @vstore_nx4i32(ptr %pa, <vscale x 4 x i32> %b) {
+ ; RV32-LABEL: name: vstore_nx4i32
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $x10, $v8m2
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $v8m2
+ ; RV32-NEXT: G_STORE [[COPY1]](<vscale x 4 x s32>), [[COPY]](p0) :: (store (<vscale x 4 x s32>) into %ir.pa)
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: vstore_nx4i32
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $x10, $v8m2
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $v8m2
+ ; RV64-NEXT: G_STORE [[COPY1]](<vscale x 4 x s32>), [[COPY]](p0) :: (store (<vscale x 4 x s32>) into %ir.pa)
+ ; RV64-NEXT: PseudoRET
+ store <vscale x 4 x i32> %b, ptr %pa
+ ret void
+}
+
+define void @vstore_nx8i32(ptr %pa, <vscale x 8 x i32> %b) {
+ ; RV32-LABEL: name: vstore_nx8i32
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $x10, $v8m4
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x s32>) = COPY $v8m4
+ ; RV32-NEXT: G_STORE [[COPY1]](<vscale x 8 x s32>), [[COPY]](p0) :: (store (<vscale x 8 x s32>) into %ir.pa)
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: vstore_nx8i32
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $x10, $v8m4
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x s32>) = COPY $v8m4
+ ; RV64-NEXT: G_STORE [[COPY1]](<vscale x 8 x s32>), [[COPY]](p0) :: (store (<vscale x 8 x s32>) into %ir.pa)
+ ; RV64-NEXT: PseudoRET
+ store <vscale x 8 x i32> %b, ptr %pa
+ ret void
+}
+
+define void @vstore_nx16i32(ptr %pa, <vscale x 16 x i32> %b) {
+ ; RV32-LABEL: name: vstore_nx16i32
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $x10, $v8m8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 16 x s32>) = COPY $v8m8
+ ; RV32-NEXT: G_STORE [[COPY1]](<vscale x 16 x s32>), [[COPY]](p0) :: (store (<vscale x 16 x s32>) into %ir.pa)
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: vstore_nx16i32
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $x10, $v8m8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 16 x s32>) = COPY $v8m8
+ ; RV64-NEXT: G_STORE [[COPY1]](<vscale x 16 x s32>), [[COPY]](p0) :: (store (<vscale x 16 x s32>) into %ir.pa)
+ ; RV64-NEXT: PseudoRET
+ store <vscale x 16 x i32> %b, ptr %pa
+ ret void
+}
+
+define void @vstore_nx1i64(ptr %pa, <vscale x 1 x i64> %b) {
+ ; RV32-LABEL: name: vstore_nx1i64
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $v8, $x10
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 1 x s64>) = COPY $v8
+ ; RV32-NEXT: G_STORE [[COPY1]](<vscale x 1 x s64>), [[COPY]](p0) :: (store (<vscale x 1 x s64>) into %ir.pa)
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: vstore_nx1i64
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $v8, $x10
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 1 x s64>) = COPY $v8
+ ; RV64-NEXT: G_STORE [[COPY1]](<vscale x 1 x s64>), [[COPY]](p0) :: (store (<vscale x 1 x s64>) into %ir.pa)
+ ; RV64-NEXT: PseudoRET
+ store <vscale x 1 x i64> %b, ptr %pa
+ ret void
+}
+
+define void @vstore_nx2i64(ptr %pa, <vscale x 2 x i64> %b) {
+ ; RV32-LABEL: name: vstore_nx2i64
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $x10, $v8m2
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $v8m2
+ ; RV32-NEXT: G_STORE [[COPY1]](<vscale x 2 x s64>), [[COPY]](p0) :: (store (<vscale x 2 x s64>) into %ir.pa)
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: vstore_nx2i64
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $x10, $v8m2
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $v8m2
+ ; RV64-NEXT: G_STORE [[COPY1]](<vscale x 2 x s64>), [[COPY]](p0) :: (store (<vscale x 2 x s64>) into %ir.pa)
+ ; RV64-NEXT: PseudoRET
+ store <vscale x 2 x i64> %b, ptr %pa
+ ret void
+}
+
+define void @vstore_nx4i64(ptr %pa, <vscale x 4 x i64> %b) {
+ ; RV32-LABEL: name: vstore_nx4i64
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $x10, $v8m4
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s64>) = COPY $v8m4
+ ; RV32-NEXT: G_STORE [[COPY1]](<vscale x 4 x s64>), [[COPY]](p0) :: (store (<vscale x 4 x s64>) into %ir.pa)
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: vstore_nx4i64
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $x10, $v8m4
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s64>) = COPY $v8m4
+ ; RV64-NEXT: G_STORE [[COPY1]](<vscale x 4 x s64>), [[COPY]](p0) :: (store (<vscale x 4 x s64>) into %ir.pa)
+ ; RV64-NEXT: PseudoRET
+ store <vscale x 4 x i64> %b, ptr %pa
+ ret void
+}
+
+define void @vstore_nx8i64(ptr %pa, <vscale x 8 x i64> %b) {
+ ; RV32-LABEL: name: vstore_nx8i64
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $x10, $v8m8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x s64>) = COPY $v8m8
+ ; RV32-NEXT: G_STORE [[COPY1]](<vscale x 8 x s64>), [[COPY]](p0) :: (store (<vscale x 8 x s64>) into %ir.pa)
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: vstore_nx8i64
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $x10, $v8m8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x s64>) = COPY $v8m8
+ ; RV64-NEXT: G_STORE [[COPY1]](<vscale x 8 x s64>), [[COPY]](p0) :: (store (<vscale x 8 x s64>) into %ir.pa)
+ ; RV64-NEXT: PseudoRET
+ store <vscale x 8 x i64> %b, ptr %pa
+ ret void
+}
+
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