[llvm] [RISCV] Add SMLoc to expanded vector pseudoinstructions in AsmParser. (PR #84875)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 11 22:42:25 PDT 2024
https://github.com/topperc created https://github.com/llvm/llvm-project/pull/84875
This is needed for llvm-mca to correctly apply vsetvli instruments to these instructions.
Fixes #84799.
>From 87b0475aa3edd2af76066a575ffe198b14619bfd Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Mon, 11 Mar 2024 22:40:49 -0700
Subject: [PATCH] [RISCV] Add SMLoc to expanded vector pseudoinstructions in
AsmParser.
This is needed for llvm-mca to correctly apply vsetvli instruments
to these instructions.
Fixes #84799.
---
llvm/include/llvm/MC/MCInstBuilder.h | 6 +++
.../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 39 ++++++++++++-------
2 files changed, 32 insertions(+), 13 deletions(-)
diff --git a/llvm/include/llvm/MC/MCInstBuilder.h b/llvm/include/llvm/MC/MCInstBuilder.h
index 6e5e9dd69018f4..d06ed4c6c840a9 100644
--- a/llvm/include/llvm/MC/MCInstBuilder.h
+++ b/llvm/include/llvm/MC/MCInstBuilder.h
@@ -27,6 +27,12 @@ class MCInstBuilder {
Inst.setOpcode(Opcode);
}
+ /// Set the location.
+ MCInstBuilder &setLoc(SMLoc SM) {
+ Inst.setLoc(SM);
+ return *this;
+ }
+
/// Add a new register operand.
MCInstBuilder &addReg(unsigned Reg) {
Inst.addOperand(MCOperand::createReg(Reg));
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index d83979a873f2a3..caff0e8fcefe23 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -3271,11 +3271,13 @@ void RISCVAsmParser::emitVMSGE(MCInst &Inst, unsigned Opcode, SMLoc IDLoc,
.addOperand(Inst.getOperand(0))
.addOperand(Inst.getOperand(1))
.addOperand(Inst.getOperand(2))
- .addReg(RISCV::NoRegister));
+ .addReg(RISCV::NoRegister)
+ .setLoc(IDLoc));
emitToStreamer(Out, MCInstBuilder(RISCV::VMNAND_MM)
.addOperand(Inst.getOperand(0))
.addOperand(Inst.getOperand(0))
- .addOperand(Inst.getOperand(0)));
+ .addOperand(Inst.getOperand(0))
+ .setLoc(IDLoc));
} else if (Inst.getNumOperands() == 4) {
// masked va >= x, vd != v0
//
@@ -3287,11 +3289,13 @@ void RISCVAsmParser::emitVMSGE(MCInst &Inst, unsigned Opcode, SMLoc IDLoc,
.addOperand(Inst.getOperand(0))
.addOperand(Inst.getOperand(1))
.addOperand(Inst.getOperand(2))
- .addOperand(Inst.getOperand(3)));
+ .addOperand(Inst.getOperand(3))
+ .setLoc(IDLoc));
emitToStreamer(Out, MCInstBuilder(RISCV::VMXOR_MM)
.addOperand(Inst.getOperand(0))
.addOperand(Inst.getOperand(0))
- .addReg(RISCV::V0));
+ .addReg(RISCV::V0)
+ .setLoc(IDLoc));
} else if (Inst.getNumOperands() == 5 &&
Inst.getOperand(0).getReg() == RISCV::V0) {
// masked va >= x, vd == v0
@@ -3306,11 +3310,13 @@ void RISCVAsmParser::emitVMSGE(MCInst &Inst, unsigned Opcode, SMLoc IDLoc,
.addOperand(Inst.getOperand(1))
.addOperand(Inst.getOperand(2))
.addOperand(Inst.getOperand(3))
- .addReg(RISCV::NoRegister));
+ .addReg(RISCV::NoRegister)
+ .setLoc(IDLoc));
emitToStreamer(Out, MCInstBuilder(RISCV::VMANDN_MM)
.addOperand(Inst.getOperand(0))
.addOperand(Inst.getOperand(0))
- .addOperand(Inst.getOperand(1)));
+ .addOperand(Inst.getOperand(1))
+ .setLoc(IDLoc));
} else if (Inst.getNumOperands() == 5) {
// masked va >= x, any vd
//
@@ -3323,19 +3329,23 @@ void RISCVAsmParser::emitVMSGE(MCInst &Inst, unsigned Opcode, SMLoc IDLoc,
.addOperand(Inst.getOperand(1))
.addOperand(Inst.getOperand(2))
.addOperand(Inst.getOperand(3))
- .addReg(RISCV::NoRegister));
+ .addReg(RISCV::NoRegister)
+ .setLoc(IDLoc));
emitToStreamer(Out, MCInstBuilder(RISCV::VMANDN_MM)
.addOperand(Inst.getOperand(1))
.addReg(RISCV::V0)
- .addOperand(Inst.getOperand(1)));
+ .addOperand(Inst.getOperand(1))
+ .setLoc(IDLoc));
emitToStreamer(Out, MCInstBuilder(RISCV::VMANDN_MM)
.addOperand(Inst.getOperand(0))
.addOperand(Inst.getOperand(0))
- .addReg(RISCV::V0));
+ .addReg(RISCV::V0)
+ .setLoc(IDLoc));
emitToStreamer(Out, MCInstBuilder(RISCV::VMOR_MM)
.addOperand(Inst.getOperand(0))
.addOperand(Inst.getOperand(1))
- .addOperand(Inst.getOperand(0)));
+ .addOperand(Inst.getOperand(0))
+ .setLoc(IDLoc));
}
}
@@ -3637,7 +3647,8 @@ bool RISCVAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
.addOperand(Inst.getOperand(0))
.addOperand(Inst.getOperand(1))
.addImm(Imm - 1)
- .addOperand(Inst.getOperand(3)));
+ .addOperand(Inst.getOperand(3))
+ .setLoc(IDLoc));
return false;
}
case RISCV::PseudoVMSGEU_VI:
@@ -3655,7 +3666,8 @@ bool RISCVAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
.addOperand(Inst.getOperand(0))
.addOperand(Inst.getOperand(1))
.addOperand(Inst.getOperand(1))
- .addOperand(Inst.getOperand(3)));
+ .addOperand(Inst.getOperand(3))
+ .setLoc(IDLoc));
} else {
// Other immediate values can subtract one like signed.
unsigned Opc = Inst.getOpcode() == RISCV::PseudoVMSGEU_VI
@@ -3665,7 +3677,8 @@ bool RISCVAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
.addOperand(Inst.getOperand(0))
.addOperand(Inst.getOperand(1))
.addImm(Imm - 1)
- .addOperand(Inst.getOperand(3)));
+ .addOperand(Inst.getOperand(3))
+ .setLoc(IDLoc));
}
return false;
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