[llvm] [AArch64][GlobalISel] Avoid generating inserts for undefs when selecting G_BUILD_VECTOR (PR #84452)
Dhruv Chawla via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 11 20:55:44 PDT 2024
https://github.com/dc03-work updated https://github.com/llvm/llvm-project/pull/84452
>From 4d9d9c76400b057174d721202509ca96bb371d6d Mon Sep 17 00:00:00 2001
From: Dhruv Chawla <dhruvc at nvidia.com>
Date: Fri, 8 Mar 2024 14:50:41 +0530
Subject: [PATCH 1/5] [AArch64][GlobalISel] Avoid generating inserts for undefs
when selecting G_BUILD_VECTOR
It is safe to ignore undef values when selecting G_BUILD_VECTOR as
undef values choose random registers for copying values from.
---
.../GISel/AArch64InstructionSelector.cpp | 21 +-
.../GlobalISel/select-build-vector.mir | 6 +-
.../select-shufflevec-undef-mask-elt.mir | 18 +-
llvm/test/CodeGen/AArch64/aarch64-bif-gen.ll | 1 -
llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll | 1 -
llvm/test/CodeGen/AArch64/abs.ll | 6 -
llvm/test/CodeGen/AArch64/arm64-dup.ll | 6 +-
llvm/test/CodeGen/AArch64/arm64-neon-copy.ll | 45 +--
llvm/test/CodeGen/AArch64/bitcast.ll | 2 -
llvm/test/CodeGen/AArch64/bswap.ll | 1 -
llvm/test/CodeGen/AArch64/fabs.ll | 26 +-
llvm/test/CodeGen/AArch64/faddsub.ll | 62 ++--
llvm/test/CodeGen/AArch64/fcmp.ll | 286 ++++++++----------
llvm/test/CodeGen/AArch64/fcopysign.ll | 4 -
llvm/test/CodeGen/AArch64/fcvt.ll | 182 +++++------
llvm/test/CodeGen/AArch64/fdiv.ll | 31 +-
llvm/test/CodeGen/AArch64/fexplog.ll | 10 -
llvm/test/CodeGen/AArch64/fminimummaximum.ll | 118 ++++----
llvm/test/CodeGen/AArch64/fminmax.ll | 118 ++++----
llvm/test/CodeGen/AArch64/fmla.ll | 164 +++++-----
llvm/test/CodeGen/AArch64/fmul.ll | 31 +-
llvm/test/CodeGen/AArch64/fneg.ll | 26 +-
llvm/test/CodeGen/AArch64/fpext.ll | 2 -
llvm/test/CodeGen/AArch64/fpow.ll | 2 -
llvm/test/CodeGen/AArch64/fpowi.ll | 2 -
llvm/test/CodeGen/AArch64/fptoi.ll | 20 --
llvm/test/CodeGen/AArch64/fptrunc.ll | 30 +-
llvm/test/CodeGen/AArch64/frem.ll | 2 -
llvm/test/CodeGen/AArch64/fsincos.ll | 4 -
llvm/test/CodeGen/AArch64/fsqrt.ll | 18 +-
llvm/test/CodeGen/AArch64/icmp.ll | 14 +-
llvm/test/CodeGen/AArch64/insertextract.ll | 4 -
llvm/test/CodeGen/AArch64/itofp.ll | 60 ----
llvm/test/CodeGen/AArch64/llvm.exp10.ll | 11 +-
llvm/test/CodeGen/AArch64/load.ll | 4 -
llvm/test/CodeGen/AArch64/sext.ll | 7 -
llvm/test/CodeGen/AArch64/shift.ll | 33 --
llvm/test/CodeGen/AArch64/shufflevector.ll | 26 +-
llvm/test/CodeGen/AArch64/xtn.ll | 3 -
llvm/test/CodeGen/AArch64/zext.ll | 13 +-
40 files changed, 543 insertions(+), 877 deletions(-)
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index 0f3c3cb96e6ce3..9ddf3eda453092 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -5938,9 +5938,12 @@ bool AArch64InstructionSelector::selectBuildVector(MachineInstr &I,
for (unsigned i = 2, e = DstSize / EltSize + 1; i < e; ++i) {
// Note that if we don't do a subregister copy, we can end up making an
// extra register.
- PrevMI = &*emitLaneInsert(std::nullopt, DstVec, I.getOperand(i).getReg(),
- i - 1, RB, MIB);
- DstVec = PrevMI->getOperand(0).getReg();
+ Register OpReg = I.getOperand(i).getReg();
+ // Do not emit inserts for undefs
+ if (!getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, OpReg, MRI)) {
+ PrevMI = &*emitLaneInsert(std::nullopt, DstVec, OpReg, i - 1, RB, MIB);
+ DstVec = PrevMI->getOperand(0).getReg();
+ }
}
// If DstTy's size in bits is less than 128, then emit a subregister copy
@@ -5972,12 +5975,20 @@ bool AArch64InstructionSelector::selectBuildVector(MachineInstr &I,
MachineOperand &RegOp = I.getOperand(1);
RegOp.setReg(Reg);
RBI.constrainGenericRegister(DstReg, *RC, MRI);
- } else {
+ } else if (PrevMI) {
// We don't need a subregister copy. Save a copy by re-using the
// destination register on the final insert.
- assert(PrevMI && "PrevMI was null?");
PrevMI->getOperand(0).setReg(I.getOperand(0).getReg());
constrainSelectedInstRegOperands(*PrevMI, TII, TRI, RBI);
+ } else {
+ // All the operands (other than the first one) to the G_BUILD_VECTOR were
+ // undef, so PrevMI is nullptr. Emit a copy from the vector made from the
+ // first operand to the destination register.
+ const TargetRegisterClass *RC =
+ getRegClassForTypeOnBank(DstTy, *RBI.getRegBank(DstVec, MRI, TRI));
+ Register DstReg = I.getOperand(0).getReg();
+ MIB.buildInstr(TargetOpcode::COPY, {DstReg}, {}).addReg(DstVec, 0);
+ RBI.constrainGenericRegister(DstReg, *RC, MRI);
}
I.eraseFromParent();
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir
index 5de97256fc85a3..9e3f65cbe218d1 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir
@@ -266,13 +266,9 @@ body: |
; CHECK-LABEL: name: undef_elts_different_regbanks
; CHECK: liveins: $w0
; CHECK: %val:gpr32all = COPY $w0
- ; CHECK: %undef:gpr32 = IMPLICIT_DEF
; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %val, %subreg.ssub
- ; CHECK: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG]], 1, %undef
- ; CHECK: [[INSvi32gpr1:%[0-9]+]]:fpr128 = INSvi32gpr [[INSvi32gpr]], 2, %undef
- ; CHECK: %bv:fpr128 = INSvi32gpr [[INSvi32gpr1]], 3, %undef
- ; CHECK: $q0 = COPY %bv
+ ; CHECK: $q0 = COPY [[INSERT_SUBREG]]
; CHECK: RET_ReallyLR implicit $q0
%val:gpr(s32) = COPY $w0
%undef:gpr(s32) = G_IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-shufflevec-undef-mask-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-shufflevec-undef-mask-elt.mir
index 6e01723f49935d..5f280ae2e3024e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-shufflevec-undef-mask-elt.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-shufflevec-undef-mask-elt.mir
@@ -19,20 +19,18 @@ body: |
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
- ; CHECK: [[DEF1:%[0-9]+]]:gpr32 = IMPLICIT_DEF
- ; CHECK: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF
- ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[DEF]], %subreg.ssub
- ; CHECK: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG]], 1, [[DEF1]]
- ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr]].dsub
+ ; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+ ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[DEF]], %subreg.ssub
+ ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY [[INSERT_SUBREG]].dsub
; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0
+ ; CHECK: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+ ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[COPY]], %subreg.dsub
; CHECK: [[DEF3:%[0-9]+]]:fpr128 = IMPLICIT_DEF
- ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], [[COPY]], %subreg.dsub
- ; CHECK: [[DEF4:%[0-9]+]]:fpr128 = IMPLICIT_DEF
- ; CHECK: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF4]], [[COPY1]], %subreg.dsub
+ ; CHECK: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], [[COPY1]], %subreg.dsub
; CHECK: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[INSERT_SUBREG1]], 1, [[INSERT_SUBREG2]], 0
- ; CHECK: [[DEF5:%[0-9]+]]:fpr128 = IMPLICIT_DEF
- ; CHECK: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF5]], [[LDRDui]], %subreg.dsub
+ ; CHECK: [[DEF4:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+ ; CHECK: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF4]], [[LDRDui]], %subreg.dsub
; CHECK: [[TBLv16i8One:%[0-9]+]]:fpr128 = TBLv16i8One [[INSvi64lane]], [[INSERT_SUBREG3]]
; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[TBLv16i8One]].dsub
; CHECK: $d0 = COPY [[COPY2]]
diff --git a/llvm/test/CodeGen/AArch64/aarch64-bif-gen.ll b/llvm/test/CodeGen/AArch64/aarch64-bif-gen.ll
index 273bf559554c9d..f47da47002fbcd 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-bif-gen.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-bif-gen.ll
@@ -77,7 +77,6 @@ define <1 x i32> @test_bitf_v1i32(<1 x i32> %A, <1 x i32> %B, <1 x i32> %C) {
; CHECK-GI-NEXT: and w8, w8, w10
; CHECK-GI-NEXT: orr w8, w9, w8
; CHECK-GI-NEXT: fmov s0, w8
-; CHECK-GI-NEXT: mov v0.s[1], w8
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
%neg = xor <1 x i32> %C, <i32 -1>
diff --git a/llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll b/llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll
index a92ae39c69724d..5c006508d284fd 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll
@@ -79,7 +79,6 @@ define <1 x i32> @test_bit_v1i32(<1 x i32> %A, <1 x i32> %B, <1 x i32> %C) {
; CHECK-GI-NEXT: bic w8, w10, w8
; CHECK-GI-NEXT: orr w8, w9, w8
; CHECK-GI-NEXT: fmov s0, w8
-; CHECK-GI-NEXT: mov v0.s[1], w8
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
%and = and <1 x i32> %C, %B
diff --git a/llvm/test/CodeGen/AArch64/abs.ll b/llvm/test/CodeGen/AArch64/abs.ll
index f2cad6631dc267..e00f70b94e3b42 100644
--- a/llvm/test/CodeGen/AArch64/abs.ll
+++ b/llvm/test/CodeGen/AArch64/abs.ll
@@ -252,7 +252,6 @@ define <1 x i32> @abs_v1i32(<1 x i32> %a){
; CHECK-GI-NEXT: add w8, w8, w9
; CHECK-GI-NEXT: eor w8, w8, w9
; CHECK-GI-NEXT: fmov s0, w8
-; CHECK-GI-NEXT: mov v0.s[1], w8
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
entry:
@@ -308,11 +307,6 @@ define <3 x i8> @abs_v3i8(<3 x i8> %a){
; CHECK-GI-NEXT: mov v0.b[1], v1.b[0]
; CHECK-GI-NEXT: fmov s1, w2
; CHECK-GI-NEXT: mov v0.b[2], v1.b[0]
-; CHECK-GI-NEXT: mov v0.b[3], v0.b[0]
-; CHECK-GI-NEXT: mov v0.b[4], v0.b[0]
-; CHECK-GI-NEXT: mov v0.b[5], v0.b[0]
-; CHECK-GI-NEXT: mov v0.b[6], v0.b[0]
-; CHECK-GI-NEXT: mov v0.b[7], v0.b[0]
; CHECK-GI-NEXT: abs v0.8b, v0.8b
; CHECK-GI-NEXT: umov w0, v0.b[0]
; CHECK-GI-NEXT: umov w1, v0.b[1]
diff --git a/llvm/test/CodeGen/AArch64/arm64-dup.ll b/llvm/test/CodeGen/AArch64/arm64-dup.ll
index 2112944cc84793..2bf5419e54830b 100644
--- a/llvm/test/CodeGen/AArch64/arm64-dup.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-dup.ll
@@ -373,11 +373,9 @@ define <4 x i16> @test_build_illegal(<4 x i32> %in) {
;
; CHECK-GI-LABEL: test_build_illegal:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov.h v1[1], v0[0]
; CHECK-GI-NEXT: mov s0, v0[3]
-; CHECK-GI-NEXT: mov.h v1[2], v0[0]
-; CHECK-GI-NEXT: mov.h v1[3], v0[0]
-; CHECK-GI-NEXT: fmov d0, d1
+; CHECK-GI-NEXT: mov.h v0[3], v0[0]
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
%val = extractelement <4 x i32> %in, i32 3
%smallval = trunc i32 %val to i16
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll b/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
index cc3d80008143cd..d282bee81827fd 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
@@ -1346,7 +1346,6 @@ define <2 x i32> @scalar_to_vector.v2i32(i32 %a) {
; CHECK-GI-LABEL: scalar_to_vector.v2i32:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: fmov s0, w0
-; CHECK-GI-NEXT: mov v0.s[1], w8
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
%b = insertelement <2 x i32> undef, i32 %a, i32 0
@@ -1354,33 +1353,19 @@ define <2 x i32> @scalar_to_vector.v2i32(i32 %a) {
}
define <4 x i32> @scalar_to_vector.v4i32(i32 %a) {
-; CHECK-SD-LABEL: scalar_to_vector.v4i32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fmov s0, w0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: scalar_to_vector.v4i32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: fmov s0, w0
-; CHECK-GI-NEXT: mov v0.s[1], w8
-; CHECK-GI-NEXT: mov v0.s[2], w8
-; CHECK-GI-NEXT: mov v0.s[3], w8
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: scalar_to_vector.v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov s0, w0
+; CHECK-NEXT: ret
%b = insertelement <4 x i32> undef, i32 %a, i32 0
ret <4 x i32> %b
}
define <2 x i64> @scalar_to_vector.v2i64(i64 %a) {
-; CHECK-SD-LABEL: scalar_to_vector.v2i64:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fmov d0, x0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: scalar_to_vector.v2i64:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: fmov d0, x0
-; CHECK-GI-NEXT: mov v0.d[1], x8
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: scalar_to_vector.v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov d0, x0
+; CHECK-NEXT: ret
%b = insertelement <2 x i64> undef, i64 %a, i32 0
ret <2 x i64> %b
}
@@ -1900,14 +1885,6 @@ define <16 x i8> @test_concat_v16i8_v8i8_v16i8(<8 x i8> %x, <16 x i8> %y) #0 {
; CHECK-GI-NEXT: mov v0.b[5], v6.b[0]
; CHECK-GI-NEXT: mov v0.b[6], v7.b[0]
; CHECK-GI-NEXT: mov v0.b[7], v16.b[0]
-; CHECK-GI-NEXT: mov v0.b[8], v0.b[0]
-; CHECK-GI-NEXT: mov v0.b[9], v0.b[0]
-; CHECK-GI-NEXT: mov v0.b[10], v0.b[0]
-; CHECK-GI-NEXT: mov v0.b[11], v0.b[0]
-; CHECK-GI-NEXT: mov v0.b[12], v0.b[0]
-; CHECK-GI-NEXT: mov v0.b[13], v0.b[0]
-; CHECK-GI-NEXT: mov v0.b[14], v0.b[0]
-; CHECK-GI-NEXT: mov v0.b[15], v0.b[0]
; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
; CHECK-GI-NEXT: ret
entry:
@@ -2123,10 +2100,6 @@ define <8 x i16> @test_concat_v8i16_v4i16_v8i16(<4 x i16> %x, <8 x i16> %y) #0 {
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI131_0]
; CHECK-GI-NEXT: mov v0.h[2], v3.h[0]
; CHECK-GI-NEXT: mov v0.h[3], v4.h[0]
-; CHECK-GI-NEXT: mov v0.h[4], v0.h[0]
-; CHECK-GI-NEXT: mov v0.h[5], v0.h[0]
-; CHECK-GI-NEXT: mov v0.h[6], v0.h[0]
-; CHECK-GI-NEXT: mov v0.h[7], v0.h[0]
; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
; CHECK-GI-NEXT: ret
entry:
@@ -2266,8 +2239,6 @@ define <4 x i32> @test_concat_v4i32_v2i32_v4i32(<2 x i32> %x, <4 x i32> %y) #0 {
; CHECK-GI-NEXT: mov s2, v0.s[1]
; CHECK-GI-NEXT: mov v0.s[1], v2.s[0]
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI135_0]
-; CHECK-GI-NEXT: mov v0.s[2], v0.s[0]
-; CHECK-GI-NEXT: mov v0.s[3], v0.s[0]
; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
; CHECK-GI-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/AArch64/bitcast.ll b/llvm/test/CodeGen/AArch64/bitcast.ll
index a5551285f2788d..bccfdb93d786f3 100644
--- a/llvm/test/CodeGen/AArch64/bitcast.ll
+++ b/llvm/test/CodeGen/AArch64/bitcast.ll
@@ -21,7 +21,6 @@ define <4 x i16> @foo1(<2 x i32> %a) {
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov w8, #58712 // =0xe558
; CHECK-GI-NEXT: fmov s1, w8
-; CHECK-GI-NEXT: mov v1.s[1], w8
; CHECK-GI-NEXT: zip1 v0.2s, v1.2s, v0.2s
; CHECK-GI-NEXT: rev32 v0.4h, v0.4h
; CHECK-GI-NEXT: ret
@@ -42,7 +41,6 @@ define <4 x i16> @foo2(<2 x i32> %a) {
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov w8, #712 // =0x2c8
; CHECK-GI-NEXT: fmov s1, w8
-; CHECK-GI-NEXT: mov v1.s[1], w8
; CHECK-GI-NEXT: zip1 v0.2s, v1.2s, v0.2s
; CHECK-GI-NEXT: rev32 v0.4h, v0.4h
; CHECK-GI-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/bswap.ll b/llvm/test/CodeGen/AArch64/bswap.ll
index 9b065accce9146..f4221accfcbc52 100644
--- a/llvm/test/CodeGen/AArch64/bswap.ll
+++ b/llvm/test/CodeGen/AArch64/bswap.ll
@@ -137,7 +137,6 @@ define <1 x i32> @bswap_v1i32(<1 x i32> %a){
; CHECK-GI-NEXT: fmov w8, s0
; CHECK-GI-NEXT: rev w8, w8
; CHECK-GI-NEXT: fmov s0, w8
-; CHECK-GI-NEXT: mov v0.s[1], w8
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/AArch64/fabs.ll b/llvm/test/CodeGen/AArch64/fabs.ll
index 7c13b49246d230..de108b0bc2b7a0 100644
--- a/llvm/test/CodeGen/AArch64/fabs.ll
+++ b/llvm/test/CodeGen/AArch64/fabs.ll
@@ -160,21 +160,20 @@ define <7 x half> @fabs_v7f16(<7 x half> %a) {
;
; CHECK-GI-NOFP16-LABEL: fabs_v7f16:
; CHECK-GI-NOFP16: // %bb.0: // %entry
-; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[4]
-; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[5]
-; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v0.4h
-; CHECK-GI-NOFP16-NEXT: mov h0, v0.h[6]
-; CHECK-GI-NOFP16-NEXT: mov v1.h[1], v2.h[0]
-; CHECK-GI-NOFP16-NEXT: fabs v2.4s, v3.4s
-; CHECK-GI-NOFP16-NEXT: mov v1.h[2], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v2.4s
-; CHECK-GI-NOFP16-NEXT: mov v1.h[3], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[1]
+; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[4]
+; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[5]
+; CHECK-GI-NOFP16-NEXT: mov h4, v0.h[6]
+; CHECK-GI-NOFP16-NEXT: fabs v1.4s, v1.4s
+; CHECK-GI-NOFP16-NEXT: mov v2.h[1], v3.h[0]
+; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v1.4s
+; CHECK-GI-NOFP16-NEXT: mov v2.h[2], v4.h[0]
+; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[1]
+; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v2.4h
; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[2]
; CHECK-GI-NOFP16-NEXT: mov h4, v0.h[3]
-; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v1.4h
-; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v2.h[0]
-; CHECK-GI-NOFP16-NEXT: fabs v1.4s, v1.4s
+; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v1.h[0]
+; CHECK-GI-NOFP16-NEXT: fabs v1.4s, v2.4s
; CHECK-GI-NOFP16-NEXT: mov v0.h[2], v3.h[0]
; CHECK-GI-NOFP16-NEXT: fcvtn v1.4h, v1.4s
; CHECK-GI-NOFP16-NEXT: mov v0.h[3], v4.h[0]
@@ -183,7 +182,6 @@ define <7 x half> @fabs_v7f16(<7 x half> %a) {
; CHECK-GI-NOFP16-NEXT: mov h1, v1.h[2]
; CHECK-GI-NOFP16-NEXT: mov v0.h[5], v2.h[0]
; CHECK-GI-NOFP16-NEXT: mov v0.h[6], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[7], v0.h[0]
; CHECK-GI-NOFP16-NEXT: ret
;
; CHECK-GI-FP16-LABEL: fabs_v7f16:
diff --git a/llvm/test/CodeGen/AArch64/faddsub.ll b/llvm/test/CodeGen/AArch64/faddsub.ll
index f8970dc9e8d5d0..6913a62fb266c1 100644
--- a/llvm/test/CodeGen/AArch64/faddsub.ll
+++ b/llvm/test/CodeGen/AArch64/faddsub.ll
@@ -186,26 +186,24 @@ define <7 x half> @fadd_v7f16(<7 x half> %a, <7 x half> %b) {
;
; CHECK-GI-NOFP16-LABEL: fadd_v7f16:
; CHECK-GI-NOFP16: // %bb.0: // %entry
-; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[4]
-; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[5]
-; CHECK-GI-NOFP16-NEXT: mov h4, v1.h[4]
-; CHECK-GI-NOFP16-NEXT: mov h5, v1.h[5]
-; CHECK-GI-NOFP16-NEXT: fcvtl v6.4s, v0.4h
-; CHECK-GI-NOFP16-NEXT: fcvtl v7.4s, v1.4h
-; CHECK-GI-NOFP16-NEXT: mov h0, v0.h[6]
+; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v1.4h
+; CHECK-GI-NOFP16-NEXT: mov h4, v0.h[4]
+; CHECK-GI-NOFP16-NEXT: mov h5, v0.h[5]
+; CHECK-GI-NOFP16-NEXT: mov h6, v1.h[4]
+; CHECK-GI-NOFP16-NEXT: mov h7, v1.h[5]
; CHECK-GI-NOFP16-NEXT: mov h1, v1.h[6]
-; CHECK-GI-NOFP16-NEXT: mov v2.h[1], v3.h[0]
+; CHECK-GI-NOFP16-NEXT: fadd v2.4s, v2.4s, v3.4s
+; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[6]
; CHECK-GI-NOFP16-NEXT: mov v4.h[1], v5.h[0]
-; CHECK-GI-NOFP16-NEXT: fadd v3.4s, v6.4s, v7.4s
-; CHECK-GI-NOFP16-NEXT: mov v2.h[2], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v4.h[2], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v3.4s
-; CHECK-GI-NOFP16-NEXT: mov v2.h[3], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v4.h[3], v0.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v6.h[1], v7.h[0]
+; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v2.4s
+; CHECK-GI-NOFP16-NEXT: mov v4.h[2], v3.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v6.h[2], v1.h[0]
; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[1]
; CHECK-GI-NOFP16-NEXT: mov h5, v0.h[3]
-; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v2.4h
-; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v4.4h
+; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v4.4h
+; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v6.4h
; CHECK-GI-NOFP16-NEXT: mov h4, v0.h[2]
; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v1.h[0]
; CHECK-GI-NOFP16-NEXT: fadd v1.4s, v2.4s, v3.4s
@@ -217,7 +215,6 @@ define <7 x half> @fadd_v7f16(<7 x half> %a, <7 x half> %b) {
; CHECK-GI-NOFP16-NEXT: mov h1, v1.h[2]
; CHECK-GI-NOFP16-NEXT: mov v0.h[5], v2.h[0]
; CHECK-GI-NOFP16-NEXT: mov v0.h[6], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[7], v0.h[0]
; CHECK-GI-NOFP16-NEXT: ret
;
; CHECK-GI-FP16-LABEL: fadd_v7f16:
@@ -538,26 +535,24 @@ define <7 x half> @fsub_v7f16(<7 x half> %a, <7 x half> %b) {
;
; CHECK-GI-NOFP16-LABEL: fsub_v7f16:
; CHECK-GI-NOFP16: // %bb.0: // %entry
-; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[4]
-; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[5]
-; CHECK-GI-NOFP16-NEXT: mov h4, v1.h[4]
-; CHECK-GI-NOFP16-NEXT: mov h5, v1.h[5]
-; CHECK-GI-NOFP16-NEXT: fcvtl v6.4s, v0.4h
-; CHECK-GI-NOFP16-NEXT: fcvtl v7.4s, v1.4h
-; CHECK-GI-NOFP16-NEXT: mov h0, v0.h[6]
+; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v1.4h
+; CHECK-GI-NOFP16-NEXT: mov h4, v0.h[4]
+; CHECK-GI-NOFP16-NEXT: mov h5, v0.h[5]
+; CHECK-GI-NOFP16-NEXT: mov h6, v1.h[4]
+; CHECK-GI-NOFP16-NEXT: mov h7, v1.h[5]
; CHECK-GI-NOFP16-NEXT: mov h1, v1.h[6]
-; CHECK-GI-NOFP16-NEXT: mov v2.h[1], v3.h[0]
+; CHECK-GI-NOFP16-NEXT: fsub v2.4s, v2.4s, v3.4s
+; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[6]
; CHECK-GI-NOFP16-NEXT: mov v4.h[1], v5.h[0]
-; CHECK-GI-NOFP16-NEXT: fsub v3.4s, v6.4s, v7.4s
-; CHECK-GI-NOFP16-NEXT: mov v2.h[2], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v4.h[2], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v3.4s
-; CHECK-GI-NOFP16-NEXT: mov v2.h[3], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v4.h[3], v0.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v6.h[1], v7.h[0]
+; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v2.4s
+; CHECK-GI-NOFP16-NEXT: mov v4.h[2], v3.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v6.h[2], v1.h[0]
; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[1]
; CHECK-GI-NOFP16-NEXT: mov h5, v0.h[3]
-; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v2.4h
-; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v4.4h
+; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v4.4h
+; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v6.4h
; CHECK-GI-NOFP16-NEXT: mov h4, v0.h[2]
; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v1.h[0]
; CHECK-GI-NOFP16-NEXT: fsub v1.4s, v2.4s, v3.4s
@@ -569,7 +564,6 @@ define <7 x half> @fsub_v7f16(<7 x half> %a, <7 x half> %b) {
; CHECK-GI-NOFP16-NEXT: mov h1, v1.h[2]
; CHECK-GI-NOFP16-NEXT: mov v0.h[5], v2.h[0]
; CHECK-GI-NOFP16-NEXT: mov v0.h[6], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[7], v0.h[0]
; CHECK-GI-NOFP16-NEXT: ret
;
; CHECK-GI-FP16-LABEL: fsub_v7f16:
diff --git a/llvm/test/CodeGen/AArch64/fcmp.ll b/llvm/test/CodeGen/AArch64/fcmp.ll
index 0f02784aaf32a0..2d0b5574cdd7ba 100644
--- a/llvm/test/CodeGen/AArch64/fcmp.ll
+++ b/llvm/test/CodeGen/AArch64/fcmp.ll
@@ -262,31 +262,28 @@ define <3 x i32> @v3f64_i32(<3 x double> %a, <3 x double> %b, <3 x i32> %d, <3 x
;
; CHECK-GI-LABEL: v3f64_i32:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov w8, #31 // =0x1f
-; CHECK-GI-NEXT: fcmp d2, d5
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
; CHECK-GI-NEXT: // kill: def $d3 killed $d3 def $q3
+; CHECK-GI-NEXT: mov w8, #31 // =0x1f
; CHECK-GI-NEXT: // kill: def $d4 killed $d4 def $q4
-; CHECK-GI-NEXT: fmov s16, w8
+; CHECK-GI-NEXT: fcmp d2, d5
; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: mov v3.d[1], v4.d[0]
+; CHECK-GI-NEXT: fmov s1, w8
; CHECK-GI-NEXT: cset w9, mi
-; CHECK-GI-NEXT: mov v16.s[1], w8
-; CHECK-GI-NEXT: fmov d1, x9
+; CHECK-GI-NEXT: mov v1.s[1], w8
+; CHECK-GI-NEXT: fmov d2, x9
; CHECK-GI-NEXT: fcmgt v0.2d, v3.2d, v0.2d
-; CHECK-GI-NEXT: mov v1.d[1], x8
-; CHECK-GI-NEXT: mov v16.s[2], w8
+; CHECK-GI-NEXT: mov v1.s[2], w8
; CHECK-GI-NEXT: mov w8, #-1 // =0xffffffff
+; CHECK-GI-NEXT: uzp1 v0.4s, v0.4s, v2.4s
; CHECK-GI-NEXT: fmov s2, w8
-; CHECK-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s
; CHECK-GI-NEXT: mov v2.s[1], w8
-; CHECK-GI-NEXT: mov v16.s[3], w8
+; CHECK-GI-NEXT: neg v3.4s, v1.4s
+; CHECK-GI-NEXT: ushl v0.4s, v0.4s, v1.4s
; CHECK-GI-NEXT: mov v2.s[2], w8
-; CHECK-GI-NEXT: neg v1.4s, v16.4s
-; CHECK-GI-NEXT: ushl v0.4s, v0.4s, v16.4s
-; CHECK-GI-NEXT: mov v2.s[3], w8
-; CHECK-GI-NEXT: sshl v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: sshl v0.4s, v0.4s, v3.4s
; CHECK-GI-NEXT: eor v1.16b, v0.16b, v2.16b
; CHECK-GI-NEXT: and v0.16b, v6.16b, v0.16b
; CHECK-GI-NEXT: and v1.16b, v7.16b, v1.16b
@@ -349,15 +346,13 @@ define <3 x float> @v3f32_float(<3 x float> %a, <3 x float> %b, <3 x float> %d,
; CHECK-GI-NEXT: mov v4.s[1], w8
; CHECK-GI-NEXT: mov v4.s[2], w8
; CHECK-GI-NEXT: mov w8, #-1 // =0xffffffff
-; CHECK-GI-NEXT: fmov s5, w8
-; CHECK-GI-NEXT: mov v5.s[1], w8
-; CHECK-GI-NEXT: mov v4.s[3], w8
-; CHECK-GI-NEXT: mov v5.s[2], w8
-; CHECK-GI-NEXT: neg v1.4s, v4.4s
+; CHECK-GI-NEXT: fmov s1, w8
+; CHECK-GI-NEXT: mov v1.s[1], w8
+; CHECK-GI-NEXT: neg v5.4s, v4.4s
; CHECK-GI-NEXT: ushl v0.4s, v0.4s, v4.4s
-; CHECK-GI-NEXT: mov v5.s[3], w8
-; CHECK-GI-NEXT: sshl v0.4s, v0.4s, v1.4s
-; CHECK-GI-NEXT: eor v1.16b, v0.16b, v5.16b
+; CHECK-GI-NEXT: mov v1.s[2], w8
+; CHECK-GI-NEXT: sshl v0.4s, v0.4s, v5.4s
+; CHECK-GI-NEXT: eor v1.16b, v0.16b, v1.16b
; CHECK-GI-NEXT: and v0.16b, v2.16b, v0.16b
; CHECK-GI-NEXT: and v1.16b, v3.16b, v1.16b
; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
@@ -429,15 +424,13 @@ define <3 x i32> @v3f32_i32(<3 x float> %a, <3 x float> %b, <3 x i32> %d, <3 x i
; CHECK-GI-NEXT: mov v4.s[1], w8
; CHECK-GI-NEXT: mov v4.s[2], w8
; CHECK-GI-NEXT: mov w8, #-1 // =0xffffffff
-; CHECK-GI-NEXT: fmov s5, w8
-; CHECK-GI-NEXT: mov v5.s[1], w8
-; CHECK-GI-NEXT: mov v4.s[3], w8
-; CHECK-GI-NEXT: mov v5.s[2], w8
-; CHECK-GI-NEXT: neg v1.4s, v4.4s
+; CHECK-GI-NEXT: fmov s1, w8
+; CHECK-GI-NEXT: mov v1.s[1], w8
+; CHECK-GI-NEXT: neg v5.4s, v4.4s
; CHECK-GI-NEXT: ushl v0.4s, v0.4s, v4.4s
-; CHECK-GI-NEXT: mov v5.s[3], w8
-; CHECK-GI-NEXT: sshl v0.4s, v0.4s, v1.4s
-; CHECK-GI-NEXT: eor v1.16b, v0.16b, v5.16b
+; CHECK-GI-NEXT: mov v1.s[2], w8
+; CHECK-GI-NEXT: sshl v0.4s, v0.4s, v5.4s
+; CHECK-GI-NEXT: eor v1.16b, v0.16b, v1.16b
; CHECK-GI-NEXT: and v0.16b, v2.16b, v0.16b
; CHECK-GI-NEXT: and v1.16b, v3.16b, v1.16b
; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
@@ -554,44 +547,40 @@ define <7 x half> @v7f16_half(<7 x half> %a, <7 x half> %b, <7 x half> %d, <7 x
; CHECK-GI-NOFP16-NEXT: mov w8, #15 // =0xf
; CHECK-GI-NOFP16-NEXT: mov h6, v0.h[4]
; CHECK-GI-NOFP16-NEXT: mov h7, v0.h[5]
-; CHECK-GI-NOFP16-NEXT: fmov s5, w8
+; CHECK-GI-NOFP16-NEXT: fmov s4, w8
; CHECK-GI-NOFP16-NEXT: mov h16, v1.h[4]
; CHECK-GI-NOFP16-NEXT: mov w8, #65535 // =0xffff
; CHECK-GI-NOFP16-NEXT: mov h17, v1.h[5]
; CHECK-GI-NOFP16-NEXT: mov h18, v0.h[6]
; CHECK-GI-NOFP16-NEXT: mov h19, v1.h[6]
+; CHECK-GI-NOFP16-NEXT: fcvtl v0.4s, v0.4h
; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v1.4h
-; CHECK-GI-NOFP16-NEXT: mov v4.16b, v5.16b
+; CHECK-GI-NOFP16-NEXT: mov v5.16b, v4.16b
; CHECK-GI-NOFP16-NEXT: mov v6.h[1], v7.h[0]
; CHECK-GI-NOFP16-NEXT: fmov s7, w8
; CHECK-GI-NOFP16-NEXT: mov v16.h[1], v17.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v4.h[1], v5.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v5.h[1], v4.h[0]
; CHECK-GI-NOFP16-NEXT: mov v17.16b, v7.16b
+; CHECK-GI-NOFP16-NEXT: fcmgt v0.4s, v1.4s, v0.4s
; CHECK-GI-NOFP16-NEXT: mov v6.h[2], v18.h[0]
; CHECK-GI-NOFP16-NEXT: mov v17.h[1], v7.h[0]
; CHECK-GI-NOFP16-NEXT: mov v16.h[2], v19.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v4.h[2], v5.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v6.h[3], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v17.h[2], v7.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v16.h[3], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-GI-NOFP16-NEXT: mov v4.h[3], v5.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v5.h[2], v4.h[0]
; CHECK-GI-NOFP16-NEXT: fcvtl v6.4s, v6.4h
-; CHECK-GI-NOFP16-NEXT: mov v17.h[3], v7.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v17.h[2], v7.h[0]
; CHECK-GI-NOFP16-NEXT: fcvtl v16.4s, v16.4h
-; CHECK-GI-NOFP16-NEXT: fcmgt v0.4s, v1.4s, v0.4s
-; CHECK-GI-NOFP16-NEXT: mov v4.h[4], v5.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v17.h[4], v7.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v5.h[3], v4.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v17.h[3], v7.h[0]
; CHECK-GI-NOFP16-NEXT: fcmgt v1.4s, v16.4s, v6.4s
-; CHECK-GI-NOFP16-NEXT: mov v4.h[5], v5.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v5.h[4], v4.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v17.h[4], v7.h[0]
+; CHECK-GI-NOFP16-NEXT: uzp1 v0.8h, v0.8h, v1.8h
+; CHECK-GI-NOFP16-NEXT: mov v5.h[5], v4.h[0]
; CHECK-GI-NOFP16-NEXT: mov v17.h[5], v7.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v4.h[6], v5.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v5.h[6], v4.h[0]
; CHECK-GI-NOFP16-NEXT: mov v17.h[6], v7.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v4.h[7], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: uzp1 v0.8h, v0.8h, v1.8h
-; CHECK-GI-NOFP16-NEXT: neg v1.8h, v4.8h
-; CHECK-GI-NOFP16-NEXT: ushl v0.8h, v0.8h, v4.8h
-; CHECK-GI-NOFP16-NEXT: mov v17.h[7], v0.h[0]
+; CHECK-GI-NOFP16-NEXT: neg v1.8h, v5.8h
+; CHECK-GI-NOFP16-NEXT: ushl v0.8h, v0.8h, v5.8h
; CHECK-GI-NOFP16-NEXT: sshl v0.8h, v0.8h, v1.8h
; CHECK-GI-NOFP16-NEXT: eor v1.16b, v0.16b, v17.16b
; CHECK-GI-NOFP16-NEXT: and v0.16b, v2.16b, v0.16b
@@ -602,6 +591,7 @@ define <7 x half> @v7f16_half(<7 x half> %a, <7 x half> %b, <7 x half> %d, <7 x
; CHECK-GI-FP16-LABEL: v7f16_half:
; CHECK-GI-FP16: // %bb.0: // %entry
; CHECK-GI-FP16-NEXT: mov w8, #15 // =0xf
+; CHECK-GI-FP16-NEXT: fcmgt v0.8h, v1.8h, v0.8h
; CHECK-GI-FP16-NEXT: fmov s4, w8
; CHECK-GI-FP16-NEXT: mov w8, #65535 // =0xffff
; CHECK-GI-FP16-NEXT: fmov s6, w8
@@ -619,11 +609,8 @@ define <7 x half> @v7f16_half(<7 x half> %a, <7 x half> %b, <7 x half> %d, <7 x
; CHECK-GI-FP16-NEXT: mov v7.h[5], v6.h[0]
; CHECK-GI-FP16-NEXT: mov v5.h[6], v4.h[0]
; CHECK-GI-FP16-NEXT: mov v7.h[6], v6.h[0]
-; CHECK-GI-FP16-NEXT: mov v5.h[7], v0.h[0]
-; CHECK-GI-FP16-NEXT: fcmgt v0.8h, v1.8h, v0.8h
; CHECK-GI-FP16-NEXT: neg v1.8h, v5.8h
; CHECK-GI-FP16-NEXT: ushl v0.8h, v0.8h, v5.8h
-; CHECK-GI-FP16-NEXT: mov v7.h[7], v0.h[0]
; CHECK-GI-FP16-NEXT: sshl v0.8h, v0.8h, v1.8h
; CHECK-GI-FP16-NEXT: eor v1.16b, v0.16b, v7.16b
; CHECK-GI-FP16-NEXT: and v0.16b, v2.16b, v0.16b
@@ -1054,69 +1041,63 @@ define <7 x i32> @v7f16_i32(<7 x half> %a, <7 x half> %b, <7 x i32> %d, <7 x i32
; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[4]
; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[5]
; CHECK-GI-NOFP16-NEXT: mov w8, #31 // =0x1f
-; CHECK-GI-NOFP16-NEXT: mov h5, v1.h[4]
-; CHECK-GI-NOFP16-NEXT: mov h4, v1.h[5]
-; CHECK-GI-NOFP16-NEXT: ldr s16, [sp, #32]
+; CHECK-GI-NOFP16-NEXT: mov h4, v1.h[4]
+; CHECK-GI-NOFP16-NEXT: mov h5, v1.h[5]
+; CHECK-GI-NOFP16-NEXT: ldr s17, [sp, #32]
; CHECK-GI-NOFP16-NEXT: mov h6, v0.h[6]
; CHECK-GI-NOFP16-NEXT: mov h7, v1.h[6]
-; CHECK-GI-NOFP16-NEXT: ldr s18, [sp, #40]
-; CHECK-GI-NOFP16-NEXT: fmov s17, w4
+; CHECK-GI-NOFP16-NEXT: fmov s16, w0
+; CHECK-GI-NOFP16-NEXT: fcvtl v0.4s, v0.4h
; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v1.4h
; CHECK-GI-NOFP16-NEXT: mov v2.h[1], v3.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v5.h[1], v4.h[0]
-; CHECK-GI-NOFP16-NEXT: fmov s4, w8
-; CHECK-GI-NOFP16-NEXT: mov v17.s[1], w5
-; CHECK-GI-NOFP16-NEXT: mov v2.h[2], v6.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v4.s[1], w8
-; CHECK-GI-NOFP16-NEXT: mov v5.h[2], v7.h[0]
-; CHECK-GI-NOFP16-NEXT: ldr s7, [sp]
-; CHECK-GI-NOFP16-NEXT: mov v17.s[2], w6
-; CHECK-GI-NOFP16-NEXT: fmov w9, s7
-; CHECK-GI-NOFP16-NEXT: fmov s7, w7
-; CHECK-GI-NOFP16-NEXT: mov v2.h[3], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v4.s[2], w8
-; CHECK-GI-NOFP16-NEXT: mov w8, #-1 // =0xffffffff
-; CHECK-GI-NOFP16-NEXT: mov v5.h[3], v0.h[0]
; CHECK-GI-NOFP16-NEXT: fmov s3, w8
-; CHECK-GI-NOFP16-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-GI-NOFP16-NEXT: mov v7.s[1], w9
-; CHECK-GI-NOFP16-NEXT: fcvtl v6.4s, v2.4h
+; CHECK-GI-NOFP16-NEXT: mov v4.h[1], v5.h[0]
+; CHECK-GI-NOFP16-NEXT: ldr s5, [sp]
+; CHECK-GI-NOFP16-NEXT: mov v16.s[1], w1
; CHECK-GI-NOFP16-NEXT: mov v3.s[1], w8
-; CHECK-GI-NOFP16-NEXT: ldr s2, [sp, #24]
-; CHECK-GI-NOFP16-NEXT: fcvtl v5.4s, v5.4h
-; CHECK-GI-NOFP16-NEXT: mov v4.s[3], w8
+; CHECK-GI-NOFP16-NEXT: fmov w9, s5
+; CHECK-GI-NOFP16-NEXT: fmov s5, w7
+; CHECK-GI-NOFP16-NEXT: mov v2.h[2], v6.h[0]
+; CHECK-GI-NOFP16-NEXT: ldr s6, [sp, #8]
; CHECK-GI-NOFP16-NEXT: fcmgt v0.4s, v1.4s, v0.4s
-; CHECK-GI-NOFP16-NEXT: mov v2.s[1], v16.s[0]
-; CHECK-GI-NOFP16-NEXT: ldr s16, [sp, #8]
+; CHECK-GI-NOFP16-NEXT: mov v4.h[2], v7.h[0]
+; CHECK-GI-NOFP16-NEXT: ldr s7, [sp, #24]
+; CHECK-GI-NOFP16-NEXT: mov v16.s[2], w2
+; CHECK-GI-NOFP16-NEXT: mov v5.s[1], w9
+; CHECK-GI-NOFP16-NEXT: fmov w9, s6
+; CHECK-GI-NOFP16-NEXT: ldr s6, [sp, #16]
; CHECK-GI-NOFP16-NEXT: mov v3.s[2], w8
-; CHECK-GI-NOFP16-NEXT: fmov w8, s16
-; CHECK-GI-NOFP16-NEXT: fcmgt v5.4s, v5.4s, v6.4s
-; CHECK-GI-NOFP16-NEXT: fmov s6, w0
-; CHECK-GI-NOFP16-NEXT: neg v19.4s, v4.4s
-; CHECK-GI-NOFP16-NEXT: mov v2.s[2], v18.s[0]
-; CHECK-GI-NOFP16-NEXT: mov v7.s[2], w8
-; CHECK-GI-NOFP16-NEXT: mov v17.s[3], w8
-; CHECK-GI-NOFP16-NEXT: mov v6.s[1], w1
-; CHECK-GI-NOFP16-NEXT: mov v3.s[3], w8
-; CHECK-GI-NOFP16-NEXT: ushl v4.4s, v5.4s, v4.4s
-; CHECK-GI-NOFP16-NEXT: ldr s5, [sp, #16]
-; CHECK-GI-NOFP16-NEXT: mov v2.s[3], v0.s[0]
-; CHECK-GI-NOFP16-NEXT: fmov w8, s5
-; CHECK-GI-NOFP16-NEXT: mov v6.s[2], w2
-; CHECK-GI-NOFP16-NEXT: sshl v4.4s, v4.4s, v19.4s
-; CHECK-GI-NOFP16-NEXT: mov v7.s[3], w8
-; CHECK-GI-NOFP16-NEXT: eor v1.16b, v4.16b, v3.16b
-; CHECK-GI-NOFP16-NEXT: and v3.16b, v17.16b, v4.16b
-; CHECK-GI-NOFP16-NEXT: mov v6.s[3], w3
-; CHECK-GI-NOFP16-NEXT: and v1.16b, v2.16b, v1.16b
-; CHECK-GI-NOFP16-NEXT: bsl v0.16b, v6.16b, v7.16b
-; CHECK-GI-NOFP16-NEXT: orr v1.16b, v3.16b, v1.16b
+; CHECK-GI-NOFP16-NEXT: mov w8, #-1 // =0xffffffff
+; CHECK-GI-NOFP16-NEXT: mov v7.s[1], v17.s[0]
+; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v2.4h
+; CHECK-GI-NOFP16-NEXT: ldr s17, [sp, #40]
+; CHECK-GI-NOFP16-NEXT: fcvtl v4.4s, v4.4h
+; CHECK-GI-NOFP16-NEXT: mov v16.s[3], w3
+; CHECK-GI-NOFP16-NEXT: mov v5.s[2], w9
+; CHECK-GI-NOFP16-NEXT: neg v18.4s, v3.4s
+; CHECK-GI-NOFP16-NEXT: mov v7.s[2], v17.s[0]
+; CHECK-GI-NOFP16-NEXT: fcmgt v2.4s, v4.4s, v2.4s
+; CHECK-GI-NOFP16-NEXT: fmov s4, w8
+; CHECK-GI-NOFP16-NEXT: mov v4.s[1], w8
+; CHECK-GI-NOFP16-NEXT: ushl v2.4s, v2.4s, v3.4s
+; CHECK-GI-NOFP16-NEXT: fmov s3, w4
+; CHECK-GI-NOFP16-NEXT: mov v3.s[1], w5
+; CHECK-GI-NOFP16-NEXT: mov v4.s[2], w8
+; CHECK-GI-NOFP16-NEXT: sshl v2.4s, v2.4s, v18.4s
+; CHECK-GI-NOFP16-NEXT: fmov w8, s6
+; CHECK-GI-NOFP16-NEXT: mov v3.s[2], w6
+; CHECK-GI-NOFP16-NEXT: eor v1.16b, v2.16b, v4.16b
+; CHECK-GI-NOFP16-NEXT: mov v5.s[3], w8
+; CHECK-GI-NOFP16-NEXT: and v1.16b, v7.16b, v1.16b
+; CHECK-GI-NOFP16-NEXT: and v2.16b, v3.16b, v2.16b
+; CHECK-GI-NOFP16-NEXT: bsl v0.16b, v16.16b, v5.16b
+; CHECK-GI-NOFP16-NEXT: orr v1.16b, v2.16b, v1.16b
; CHECK-GI-NOFP16-NEXT: mov s2, v0.s[1]
; CHECK-GI-NOFP16-NEXT: mov s3, v0.s[2]
; CHECK-GI-NOFP16-NEXT: mov s4, v0.s[3]
+; CHECK-GI-NOFP16-NEXT: fmov w0, s0
; CHECK-GI-NOFP16-NEXT: mov s5, v1.s[1]
; CHECK-GI-NOFP16-NEXT: mov s6, v1.s[2]
-; CHECK-GI-NOFP16-NEXT: fmov w0, s0
; CHECK-GI-NOFP16-NEXT: fmov w4, s1
; CHECK-GI-NOFP16-NEXT: fmov w1, s2
; CHECK-GI-NOFP16-NEXT: fmov w2, s3
@@ -1127,65 +1108,60 @@ define <7 x i32> @v7f16_i32(<7 x half> %a, <7 x half> %b, <7 x i32> %d, <7 x i32
;
; CHECK-GI-FP16-LABEL: v7f16_i32:
; CHECK-GI-FP16: // %bb.0: // %entry
-; CHECK-GI-FP16-NEXT: fcmgt v5.8h, v1.8h, v0.8h
-; CHECK-GI-FP16-NEXT: mov w10, #31 // =0x1f
-; CHECK-GI-FP16-NEXT: ldr s6, [sp]
-; CHECK-GI-FP16-NEXT: fmov s2, w10
-; CHECK-GI-FP16-NEXT: ldr s1, [sp, #24]
-; CHECK-GI-FP16-NEXT: ldr s7, [sp, #32]
-; CHECK-GI-FP16-NEXT: fmov s16, w0
-; CHECK-GI-FP16-NEXT: ldr s17, [sp, #40]
-; CHECK-GI-FP16-NEXT: mov v1.s[1], v7.s[0]
-; CHECK-GI-FP16-NEXT: ldr s7, [sp, #8]
-; CHECK-GI-FP16-NEXT: umov w8, v5.h[4]
-; CHECK-GI-FP16-NEXT: umov w9, v5.h[5]
-; CHECK-GI-FP16-NEXT: umov w11, v5.h[0]
-; CHECK-GI-FP16-NEXT: umov w12, v5.h[1]
-; CHECK-GI-FP16-NEXT: mov v2.s[1], w10
-; CHECK-GI-FP16-NEXT: mov v16.s[1], w1
-; CHECK-GI-FP16-NEXT: mov v1.s[2], v17.s[0]
-; CHECK-GI-FP16-NEXT: fmov s3, w8
-; CHECK-GI-FP16-NEXT: umov w8, v5.h[6]
-; CHECK-GI-FP16-NEXT: fmov s0, w11
-; CHECK-GI-FP16-NEXT: mov v2.s[2], w10
-; CHECK-GI-FP16-NEXT: umov w10, v5.h[3]
-; CHECK-GI-FP16-NEXT: mov v16.s[2], w2
-; CHECK-GI-FP16-NEXT: mov v3.s[1], w9
-; CHECK-GI-FP16-NEXT: umov w9, v5.h[2]
-; CHECK-GI-FP16-NEXT: mov v0.s[1], w12
-; CHECK-GI-FP16-NEXT: fmov s5, w4
-; CHECK-GI-FP16-NEXT: mov v16.s[3], w3
+; CHECK-GI-FP16-NEXT: fcmgt v1.8h, v1.8h, v0.8h
+; CHECK-GI-FP16-NEXT: mov w12, #31 // =0x1f
+; CHECK-GI-FP16-NEXT: ldr s4, [sp]
+; CHECK-GI-FP16-NEXT: fmov s2, w12
+; CHECK-GI-FP16-NEXT: fmov s6, w0
+; CHECK-GI-FP16-NEXT: ldr s5, [sp, #8]
+; CHECK-GI-FP16-NEXT: ldr s7, [sp, #24]
+; CHECK-GI-FP16-NEXT: ldr s16, [sp, #32]
+; CHECK-GI-FP16-NEXT: umov w9, v1.h[4]
+; CHECK-GI-FP16-NEXT: umov w8, v1.h[0]
+; CHECK-GI-FP16-NEXT: umov w11, v1.h[5]
+; CHECK-GI-FP16-NEXT: umov w10, v1.h[1]
+; CHECK-GI-FP16-NEXT: mov v2.s[1], w12
+; CHECK-GI-FP16-NEXT: umov w13, v1.h[2]
+; CHECK-GI-FP16-NEXT: mov v6.s[1], w1
+; CHECK-GI-FP16-NEXT: mov v7.s[1], v16.s[0]
+; CHECK-GI-FP16-NEXT: ldr s16, [sp, #40]
+; CHECK-GI-FP16-NEXT: fmov s3, w9
+; CHECK-GI-FP16-NEXT: fmov s0, w8
+; CHECK-GI-FP16-NEXT: umov w8, v1.h[6]
+; CHECK-GI-FP16-NEXT: mov v2.s[2], w12
+; CHECK-GI-FP16-NEXT: umov w9, v1.h[3]
+; CHECK-GI-FP16-NEXT: mov v6.s[2], w2
+; CHECK-GI-FP16-NEXT: mov v7.s[2], v16.s[0]
+; CHECK-GI-FP16-NEXT: mov v3.s[1], w11
+; CHECK-GI-FP16-NEXT: mov v0.s[1], w10
+; CHECK-GI-FP16-NEXT: mov w10, #-1 // =0xffffffff
+; CHECK-GI-FP16-NEXT: fmov s1, w10
+; CHECK-GI-FP16-NEXT: neg v17.4s, v2.4s
+; CHECK-GI-FP16-NEXT: mov v6.s[3], w3
; CHECK-GI-FP16-NEXT: mov v3.s[2], w8
-; CHECK-GI-FP16-NEXT: mov w8, #-1 // =0xffffffff
-; CHECK-GI-FP16-NEXT: mov v0.s[2], w9
-; CHECK-GI-FP16-NEXT: fmov s4, w8
-; CHECK-GI-FP16-NEXT: mov v2.s[3], w8
-; CHECK-GI-FP16-NEXT: mov v5.s[1], w5
-; CHECK-GI-FP16-NEXT: fmov w9, s6
-; CHECK-GI-FP16-NEXT: fmov s6, w7
+; CHECK-GI-FP16-NEXT: fmov w8, s4
+; CHECK-GI-FP16-NEXT: fmov s4, w7
+; CHECK-GI-FP16-NEXT: mov v0.s[2], w13
+; CHECK-GI-FP16-NEXT: mov v1.s[1], w10
; CHECK-GI-FP16-NEXT: mov v4.s[1], w8
-; CHECK-GI-FP16-NEXT: mov v3.s[3], w8
-; CHECK-GI-FP16-NEXT: mov v0.s[3], w10
-; CHECK-GI-FP16-NEXT: mov v6.s[1], w9
-; CHECK-GI-FP16-NEXT: neg v18.4s, v2.4s
-; CHECK-GI-FP16-NEXT: mov v5.s[2], w6
-; CHECK-GI-FP16-NEXT: mov v4.s[2], w8
-; CHECK-GI-FP16-NEXT: fmov w8, s7
+; CHECK-GI-FP16-NEXT: fmov w8, s5
+; CHECK-GI-FP16-NEXT: ldr s5, [sp, #16]
; CHECK-GI-FP16-NEXT: ushl v2.4s, v3.4s, v2.4s
-; CHECK-GI-FP16-NEXT: ldr s3, [sp, #16]
+; CHECK-GI-FP16-NEXT: fmov s3, w4
+; CHECK-GI-FP16-NEXT: mov v0.s[3], w9
+; CHECK-GI-FP16-NEXT: mov v1.s[2], w10
+; CHECK-GI-FP16-NEXT: mov v3.s[1], w5
+; CHECK-GI-FP16-NEXT: mov v4.s[2], w8
+; CHECK-GI-FP16-NEXT: sshl v2.4s, v2.4s, v17.4s
+; CHECK-GI-FP16-NEXT: fmov w8, s5
; CHECK-GI-FP16-NEXT: shl v0.4s, v0.4s, #31
-; CHECK-GI-FP16-NEXT: mov v6.s[2], w8
-; CHECK-GI-FP16-NEXT: sshl v2.4s, v2.4s, v18.4s
-; CHECK-GI-FP16-NEXT: mov v5.s[3], w8
+; CHECK-GI-FP16-NEXT: eor v1.16b, v2.16b, v1.16b
+; CHECK-GI-FP16-NEXT: mov v3.s[2], w6
; CHECK-GI-FP16-NEXT: mov v4.s[3], w8
-; CHECK-GI-FP16-NEXT: fmov w8, s3
-; CHECK-GI-FP16-NEXT: mov v1.s[3], v0.s[0]
; CHECK-GI-FP16-NEXT: sshr v0.4s, v0.4s, #31
-; CHECK-GI-FP16-NEXT: mov v6.s[3], w8
-; CHECK-GI-FP16-NEXT: eor v3.16b, v2.16b, v4.16b
-; CHECK-GI-FP16-NEXT: and v2.16b, v5.16b, v2.16b
-; CHECK-GI-FP16-NEXT: and v1.16b, v1.16b, v3.16b
-; CHECK-GI-FP16-NEXT: bsl v0.16b, v16.16b, v6.16b
+; CHECK-GI-FP16-NEXT: and v1.16b, v7.16b, v1.16b
+; CHECK-GI-FP16-NEXT: and v2.16b, v3.16b, v2.16b
+; CHECK-GI-FP16-NEXT: bsl v0.16b, v6.16b, v4.16b
; CHECK-GI-FP16-NEXT: orr v1.16b, v2.16b, v1.16b
; CHECK-GI-FP16-NEXT: mov s2, v0.s[1]
; CHECK-GI-FP16-NEXT: mov s3, v0.s[2]
diff --git a/llvm/test/CodeGen/AArch64/fcopysign.ll b/llvm/test/CodeGen/AArch64/fcopysign.ll
index 78fd38ca9f268a..84376107679d84 100644
--- a/llvm/test/CodeGen/AArch64/fcopysign.ll
+++ b/llvm/test/CodeGen/AArch64/fcopysign.ll
@@ -162,8 +162,6 @@ define <3 x float> @copysign_v3f32(<3 x float> %a, <3 x float> %b) {
; CHECK-GI-NEXT: mov v3.s[1], w8
; CHECK-GI-NEXT: mov v2.s[2], w9
; CHECK-GI-NEXT: mov v3.s[2], w8
-; CHECK-GI-NEXT: mov v2.s[3], w8
-; CHECK-GI-NEXT: mov v3.s[3], w8
; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b
; CHECK-GI-NEXT: and v1.16b, v1.16b, v3.16b
; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
@@ -223,8 +221,6 @@ define <7 x half> @copysign_v7f16(<7 x half> %a, <7 x half> %b) {
; CHECK-GI-NEXT: mov v5.h[5], v3.h[0]
; CHECK-GI-NEXT: mov v4.h[6], v2.h[0]
; CHECK-GI-NEXT: mov v5.h[6], v3.h[0]
-; CHECK-GI-NEXT: mov v4.h[7], v0.h[0]
-; CHECK-GI-NEXT: mov v5.h[7], v0.h[0]
; CHECK-GI-NEXT: and v0.16b, v0.16b, v4.16b
; CHECK-GI-NEXT: and v1.16b, v1.16b, v5.16b
; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
diff --git a/llvm/test/CodeGen/AArch64/fcvt.ll b/llvm/test/CodeGen/AArch64/fcvt.ll
index 3b8a22a052b836..1c761ea083028a 100644
--- a/llvm/test/CodeGen/AArch64/fcvt.ll
+++ b/llvm/test/CodeGen/AArch64/fcvt.ll
@@ -163,21 +163,20 @@ define <7 x half> @ceil_v7f16(<7 x half> %a) {
;
; CHECK-GI-NOFP16-LABEL: ceil_v7f16:
; CHECK-GI-NOFP16: // %bb.0: // %entry
-; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[4]
-; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[5]
-; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v0.4h
-; CHECK-GI-NOFP16-NEXT: mov h0, v0.h[6]
-; CHECK-GI-NOFP16-NEXT: mov v1.h[1], v2.h[0]
-; CHECK-GI-NOFP16-NEXT: frintp v2.4s, v3.4s
-; CHECK-GI-NOFP16-NEXT: mov v1.h[2], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v2.4s
-; CHECK-GI-NOFP16-NEXT: mov v1.h[3], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[1]
+; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[4]
+; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[5]
+; CHECK-GI-NOFP16-NEXT: mov h4, v0.h[6]
+; CHECK-GI-NOFP16-NEXT: frintp v1.4s, v1.4s
+; CHECK-GI-NOFP16-NEXT: mov v2.h[1], v3.h[0]
+; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v1.4s
+; CHECK-GI-NOFP16-NEXT: mov v2.h[2], v4.h[0]
+; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[1]
+; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v2.4h
; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[2]
; CHECK-GI-NOFP16-NEXT: mov h4, v0.h[3]
-; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v1.4h
-; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v2.h[0]
-; CHECK-GI-NOFP16-NEXT: frintp v1.4s, v1.4s
+; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v1.h[0]
+; CHECK-GI-NOFP16-NEXT: frintp v1.4s, v2.4s
; CHECK-GI-NOFP16-NEXT: mov v0.h[2], v3.h[0]
; CHECK-GI-NOFP16-NEXT: fcvtn v1.4h, v1.4s
; CHECK-GI-NOFP16-NEXT: mov v0.h[3], v4.h[0]
@@ -186,7 +185,6 @@ define <7 x half> @ceil_v7f16(<7 x half> %a) {
; CHECK-GI-NOFP16-NEXT: mov h1, v1.h[2]
; CHECK-GI-NOFP16-NEXT: mov v0.h[5], v2.h[0]
; CHECK-GI-NOFP16-NEXT: mov v0.h[6], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[7], v0.h[0]
; CHECK-GI-NOFP16-NEXT: ret
;
; CHECK-GI-FP16-LABEL: ceil_v7f16:
@@ -470,21 +468,20 @@ define <7 x half> @floor_v7f16(<7 x half> %a) {
;
; CHECK-GI-NOFP16-LABEL: floor_v7f16:
; CHECK-GI-NOFP16: // %bb.0: // %entry
-; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[4]
-; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[5]
-; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v0.4h
-; CHECK-GI-NOFP16-NEXT: mov h0, v0.h[6]
-; CHECK-GI-NOFP16-NEXT: mov v1.h[1], v2.h[0]
-; CHECK-GI-NOFP16-NEXT: frintm v2.4s, v3.4s
-; CHECK-GI-NOFP16-NEXT: mov v1.h[2], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v2.4s
-; CHECK-GI-NOFP16-NEXT: mov v1.h[3], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[1]
+; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[4]
+; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[5]
+; CHECK-GI-NOFP16-NEXT: mov h4, v0.h[6]
+; CHECK-GI-NOFP16-NEXT: frintm v1.4s, v1.4s
+; CHECK-GI-NOFP16-NEXT: mov v2.h[1], v3.h[0]
+; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v1.4s
+; CHECK-GI-NOFP16-NEXT: mov v2.h[2], v4.h[0]
+; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[1]
+; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v2.4h
; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[2]
; CHECK-GI-NOFP16-NEXT: mov h4, v0.h[3]
-; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v1.4h
-; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v2.h[0]
-; CHECK-GI-NOFP16-NEXT: frintm v1.4s, v1.4s
+; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v1.h[0]
+; CHECK-GI-NOFP16-NEXT: frintm v1.4s, v2.4s
; CHECK-GI-NOFP16-NEXT: mov v0.h[2], v3.h[0]
; CHECK-GI-NOFP16-NEXT: fcvtn v1.4h, v1.4s
; CHECK-GI-NOFP16-NEXT: mov v0.h[3], v4.h[0]
@@ -493,7 +490,6 @@ define <7 x half> @floor_v7f16(<7 x half> %a) {
; CHECK-GI-NOFP16-NEXT: mov h1, v1.h[2]
; CHECK-GI-NOFP16-NEXT: mov v0.h[5], v2.h[0]
; CHECK-GI-NOFP16-NEXT: mov v0.h[6], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[7], v0.h[0]
; CHECK-GI-NOFP16-NEXT: ret
;
; CHECK-GI-FP16-LABEL: floor_v7f16:
@@ -777,21 +773,20 @@ define <7 x half> @nearbyint_v7f16(<7 x half> %a) {
;
; CHECK-GI-NOFP16-LABEL: nearbyint_v7f16:
; CHECK-GI-NOFP16: // %bb.0: // %entry
-; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[4]
-; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[5]
-; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v0.4h
-; CHECK-GI-NOFP16-NEXT: mov h0, v0.h[6]
-; CHECK-GI-NOFP16-NEXT: mov v1.h[1], v2.h[0]
-; CHECK-GI-NOFP16-NEXT: frinti v2.4s, v3.4s
-; CHECK-GI-NOFP16-NEXT: mov v1.h[2], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v2.4s
-; CHECK-GI-NOFP16-NEXT: mov v1.h[3], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[1]
+; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[4]
+; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[5]
+; CHECK-GI-NOFP16-NEXT: mov h4, v0.h[6]
+; CHECK-GI-NOFP16-NEXT: frinti v1.4s, v1.4s
+; CHECK-GI-NOFP16-NEXT: mov v2.h[1], v3.h[0]
+; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v1.4s
+; CHECK-GI-NOFP16-NEXT: mov v2.h[2], v4.h[0]
+; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[1]
+; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v2.4h
; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[2]
; CHECK-GI-NOFP16-NEXT: mov h4, v0.h[3]
-; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v1.4h
-; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v2.h[0]
-; CHECK-GI-NOFP16-NEXT: frinti v1.4s, v1.4s
+; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v1.h[0]
+; CHECK-GI-NOFP16-NEXT: frinti v1.4s, v2.4s
; CHECK-GI-NOFP16-NEXT: mov v0.h[2], v3.h[0]
; CHECK-GI-NOFP16-NEXT: fcvtn v1.4h, v1.4s
; CHECK-GI-NOFP16-NEXT: mov v0.h[3], v4.h[0]
@@ -800,7 +795,6 @@ define <7 x half> @nearbyint_v7f16(<7 x half> %a) {
; CHECK-GI-NOFP16-NEXT: mov h1, v1.h[2]
; CHECK-GI-NOFP16-NEXT: mov v0.h[5], v2.h[0]
; CHECK-GI-NOFP16-NEXT: mov v0.h[6], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[7], v0.h[0]
; CHECK-GI-NOFP16-NEXT: ret
;
; CHECK-GI-FP16-LABEL: nearbyint_v7f16:
@@ -1084,21 +1078,20 @@ define <7 x half> @roundeven_v7f16(<7 x half> %a) {
;
; CHECK-GI-NOFP16-LABEL: roundeven_v7f16:
; CHECK-GI-NOFP16: // %bb.0: // %entry
-; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[4]
-; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[5]
-; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v0.4h
-; CHECK-GI-NOFP16-NEXT: mov h0, v0.h[6]
-; CHECK-GI-NOFP16-NEXT: mov v1.h[1], v2.h[0]
-; CHECK-GI-NOFP16-NEXT: frintn v2.4s, v3.4s
-; CHECK-GI-NOFP16-NEXT: mov v1.h[2], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v2.4s
-; CHECK-GI-NOFP16-NEXT: mov v1.h[3], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[1]
+; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[4]
+; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[5]
+; CHECK-GI-NOFP16-NEXT: mov h4, v0.h[6]
+; CHECK-GI-NOFP16-NEXT: frintn v1.4s, v1.4s
+; CHECK-GI-NOFP16-NEXT: mov v2.h[1], v3.h[0]
+; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v1.4s
+; CHECK-GI-NOFP16-NEXT: mov v2.h[2], v4.h[0]
+; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[1]
+; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v2.4h
; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[2]
; CHECK-GI-NOFP16-NEXT: mov h4, v0.h[3]
-; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v1.4h
-; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v2.h[0]
-; CHECK-GI-NOFP16-NEXT: frintn v1.4s, v1.4s
+; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v1.h[0]
+; CHECK-GI-NOFP16-NEXT: frintn v1.4s, v2.4s
; CHECK-GI-NOFP16-NEXT: mov v0.h[2], v3.h[0]
; CHECK-GI-NOFP16-NEXT: fcvtn v1.4h, v1.4s
; CHECK-GI-NOFP16-NEXT: mov v0.h[3], v4.h[0]
@@ -1107,7 +1100,6 @@ define <7 x half> @roundeven_v7f16(<7 x half> %a) {
; CHECK-GI-NOFP16-NEXT: mov h1, v1.h[2]
; CHECK-GI-NOFP16-NEXT: mov v0.h[5], v2.h[0]
; CHECK-GI-NOFP16-NEXT: mov v0.h[6], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[7], v0.h[0]
; CHECK-GI-NOFP16-NEXT: ret
;
; CHECK-GI-FP16-LABEL: roundeven_v7f16:
@@ -1391,21 +1383,20 @@ define <7 x half> @rint_v7f16(<7 x half> %a) {
;
; CHECK-GI-NOFP16-LABEL: rint_v7f16:
; CHECK-GI-NOFP16: // %bb.0: // %entry
-; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[4]
-; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[5]
-; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v0.4h
-; CHECK-GI-NOFP16-NEXT: mov h0, v0.h[6]
-; CHECK-GI-NOFP16-NEXT: mov v1.h[1], v2.h[0]
-; CHECK-GI-NOFP16-NEXT: frintx v2.4s, v3.4s
-; CHECK-GI-NOFP16-NEXT: mov v1.h[2], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v2.4s
-; CHECK-GI-NOFP16-NEXT: mov v1.h[3], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[1]
+; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[4]
+; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[5]
+; CHECK-GI-NOFP16-NEXT: mov h4, v0.h[6]
+; CHECK-GI-NOFP16-NEXT: frintx v1.4s, v1.4s
+; CHECK-GI-NOFP16-NEXT: mov v2.h[1], v3.h[0]
+; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v1.4s
+; CHECK-GI-NOFP16-NEXT: mov v2.h[2], v4.h[0]
+; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[1]
+; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v2.4h
; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[2]
; CHECK-GI-NOFP16-NEXT: mov h4, v0.h[3]
-; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v1.4h
-; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v2.h[0]
-; CHECK-GI-NOFP16-NEXT: frintx v1.4s, v1.4s
+; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v1.h[0]
+; CHECK-GI-NOFP16-NEXT: frintx v1.4s, v2.4s
; CHECK-GI-NOFP16-NEXT: mov v0.h[2], v3.h[0]
; CHECK-GI-NOFP16-NEXT: fcvtn v1.4h, v1.4s
; CHECK-GI-NOFP16-NEXT: mov v0.h[3], v4.h[0]
@@ -1414,7 +1405,6 @@ define <7 x half> @rint_v7f16(<7 x half> %a) {
; CHECK-GI-NOFP16-NEXT: mov h1, v1.h[2]
; CHECK-GI-NOFP16-NEXT: mov v0.h[5], v2.h[0]
; CHECK-GI-NOFP16-NEXT: mov v0.h[6], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[7], v0.h[0]
; CHECK-GI-NOFP16-NEXT: ret
;
; CHECK-GI-FP16-LABEL: rint_v7f16:
@@ -1698,21 +1688,20 @@ define <7 x half> @round_v7f16(<7 x half> %a) {
;
; CHECK-GI-NOFP16-LABEL: round_v7f16:
; CHECK-GI-NOFP16: // %bb.0: // %entry
-; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[4]
-; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[5]
-; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v0.4h
-; CHECK-GI-NOFP16-NEXT: mov h0, v0.h[6]
-; CHECK-GI-NOFP16-NEXT: mov v1.h[1], v2.h[0]
-; CHECK-GI-NOFP16-NEXT: frinta v2.4s, v3.4s
-; CHECK-GI-NOFP16-NEXT: mov v1.h[2], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v2.4s
-; CHECK-GI-NOFP16-NEXT: mov v1.h[3], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[1]
+; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[4]
+; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[5]
+; CHECK-GI-NOFP16-NEXT: mov h4, v0.h[6]
+; CHECK-GI-NOFP16-NEXT: frinta v1.4s, v1.4s
+; CHECK-GI-NOFP16-NEXT: mov v2.h[1], v3.h[0]
+; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v1.4s
+; CHECK-GI-NOFP16-NEXT: mov v2.h[2], v4.h[0]
+; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[1]
+; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v2.4h
; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[2]
; CHECK-GI-NOFP16-NEXT: mov h4, v0.h[3]
-; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v1.4h
-; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v2.h[0]
-; CHECK-GI-NOFP16-NEXT: frinta v1.4s, v1.4s
+; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v1.h[0]
+; CHECK-GI-NOFP16-NEXT: frinta v1.4s, v2.4s
; CHECK-GI-NOFP16-NEXT: mov v0.h[2], v3.h[0]
; CHECK-GI-NOFP16-NEXT: fcvtn v1.4h, v1.4s
; CHECK-GI-NOFP16-NEXT: mov v0.h[3], v4.h[0]
@@ -1721,7 +1710,6 @@ define <7 x half> @round_v7f16(<7 x half> %a) {
; CHECK-GI-NOFP16-NEXT: mov h1, v1.h[2]
; CHECK-GI-NOFP16-NEXT: mov v0.h[5], v2.h[0]
; CHECK-GI-NOFP16-NEXT: mov v0.h[6], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[7], v0.h[0]
; CHECK-GI-NOFP16-NEXT: ret
;
; CHECK-GI-FP16-LABEL: round_v7f16:
@@ -2005,21 +1993,20 @@ define <7 x half> @trunc_v7f16(<7 x half> %a) {
;
; CHECK-GI-NOFP16-LABEL: trunc_v7f16:
; CHECK-GI-NOFP16: // %bb.0: // %entry
-; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[4]
-; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[5]
-; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v0.4h
-; CHECK-GI-NOFP16-NEXT: mov h0, v0.h[6]
-; CHECK-GI-NOFP16-NEXT: mov v1.h[1], v2.h[0]
-; CHECK-GI-NOFP16-NEXT: frintz v2.4s, v3.4s
-; CHECK-GI-NOFP16-NEXT: mov v1.h[2], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v2.4s
-; CHECK-GI-NOFP16-NEXT: mov v1.h[3], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[1]
+; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[4]
+; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[5]
+; CHECK-GI-NOFP16-NEXT: mov h4, v0.h[6]
+; CHECK-GI-NOFP16-NEXT: frintz v1.4s, v1.4s
+; CHECK-GI-NOFP16-NEXT: mov v2.h[1], v3.h[0]
+; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v1.4s
+; CHECK-GI-NOFP16-NEXT: mov v2.h[2], v4.h[0]
+; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[1]
+; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v2.4h
; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[2]
; CHECK-GI-NOFP16-NEXT: mov h4, v0.h[3]
-; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v1.4h
-; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v2.h[0]
-; CHECK-GI-NOFP16-NEXT: frintz v1.4s, v1.4s
+; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v1.h[0]
+; CHECK-GI-NOFP16-NEXT: frintz v1.4s, v2.4s
; CHECK-GI-NOFP16-NEXT: mov v0.h[2], v3.h[0]
; CHECK-GI-NOFP16-NEXT: fcvtn v1.4h, v1.4s
; CHECK-GI-NOFP16-NEXT: mov v0.h[3], v4.h[0]
@@ -2028,7 +2015,6 @@ define <7 x half> @trunc_v7f16(<7 x half> %a) {
; CHECK-GI-NOFP16-NEXT: mov h1, v1.h[2]
; CHECK-GI-NOFP16-NEXT: mov v0.h[5], v2.h[0]
; CHECK-GI-NOFP16-NEXT: mov v0.h[6], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[7], v0.h[0]
; CHECK-GI-NOFP16-NEXT: ret
;
; CHECK-GI-FP16-LABEL: trunc_v7f16:
diff --git a/llvm/test/CodeGen/AArch64/fdiv.ll b/llvm/test/CodeGen/AArch64/fdiv.ll
index e73124fbb595bb..d73a5dc73eefcd 100644
--- a/llvm/test/CodeGen/AArch64/fdiv.ll
+++ b/llvm/test/CodeGen/AArch64/fdiv.ll
@@ -186,25 +186,23 @@ define <7 x half> @fdiv_v7f16(<7 x half> %a, <7 x half> %b) {
;
; CHECK-GI-NOFP16-LABEL: fdiv_v7f16:
; CHECK-GI-NOFP16: // %bb.0: // %entry
-; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[4]
-; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[5]
-; CHECK-GI-NOFP16-NEXT: mov h4, v1.h[4]
-; CHECK-GI-NOFP16-NEXT: mov h5, v1.h[5]
-; CHECK-GI-NOFP16-NEXT: fcvtl v6.4s, v0.4h
-; CHECK-GI-NOFP16-NEXT: fcvtl v7.4s, v1.4h
+; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v1.4h
+; CHECK-GI-NOFP16-NEXT: mov h4, v0.h[4]
+; CHECK-GI-NOFP16-NEXT: mov h5, v0.h[5]
+; CHECK-GI-NOFP16-NEXT: mov h6, v1.h[4]
+; CHECK-GI-NOFP16-NEXT: mov h7, v1.h[5]
; CHECK-GI-NOFP16-NEXT: mov h0, v0.h[6]
; CHECK-GI-NOFP16-NEXT: mov h1, v1.h[6]
-; CHECK-GI-NOFP16-NEXT: mov v2.h[1], v3.h[0]
+; CHECK-GI-NOFP16-NEXT: fdiv v2.4s, v2.4s, v3.4s
; CHECK-GI-NOFP16-NEXT: mov v4.h[1], v5.h[0]
-; CHECK-GI-NOFP16-NEXT: fdiv v3.4s, v6.4s, v7.4s
-; CHECK-GI-NOFP16-NEXT: mov v2.h[2], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v4.h[2], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v2.h[3], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v4.h[3], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v2.4h
-; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v4.4h
-; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v3.4s
-; CHECK-GI-NOFP16-NEXT: fdiv v1.4s, v1.4s, v2.4s
+; CHECK-GI-NOFP16-NEXT: mov v6.h[1], v7.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v4.h[2], v0.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v6.h[2], v1.h[0]
+; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v4.4h
+; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v6.4h
+; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v2.4s
+; CHECK-GI-NOFP16-NEXT: fdiv v1.4s, v1.4s, v3.4s
; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[1]
; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[2]
; CHECK-GI-NOFP16-NEXT: mov h4, v0.h[3]
@@ -217,7 +215,6 @@ define <7 x half> @fdiv_v7f16(<7 x half> %a, <7 x half> %b) {
; CHECK-GI-NOFP16-NEXT: mov h1, v1.h[2]
; CHECK-GI-NOFP16-NEXT: mov v0.h[5], v2.h[0]
; CHECK-GI-NOFP16-NEXT: mov v0.h[6], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[7], v0.h[0]
; CHECK-GI-NOFP16-NEXT: ret
;
; CHECK-GI-FP16-LABEL: fdiv_v7f16:
diff --git a/llvm/test/CodeGen/AArch64/fexplog.ll b/llvm/test/CodeGen/AArch64/fexplog.ll
index e3c0ced79f07a6..519a2978d8604b 100644
--- a/llvm/test/CodeGen/AArch64/fexplog.ll
+++ b/llvm/test/CodeGen/AArch64/fexplog.ll
@@ -332,7 +332,6 @@ define <3 x float> @exp_v3f32(<3 x float> %a) {
; CHECK-GI-NEXT: ldp d9, d8, [sp, #32] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v1.s[1], v2.s[0]
; CHECK-GI-NEXT: mov v1.s[2], v0.s[0]
-; CHECK-GI-NEXT: mov v1.s[3], v0.s[0]
; CHECK-GI-NEXT: mov v0.16b, v1.16b
; CHECK-GI-NEXT: add sp, sp, #64
; CHECK-GI-NEXT: ret
@@ -703,7 +702,6 @@ define <7 x half> @exp_v7f16(<7 x half> %a) {
; CHECK-GI-NEXT: mov v1.h[4], v3.h[0]
; CHECK-GI-NEXT: mov v1.h[5], v2.h[0]
; CHECK-GI-NEXT: mov v1.h[6], v0.h[0]
-; CHECK-GI-NEXT: mov v1.h[7], v0.h[0]
; CHECK-GI-NEXT: mov v0.16b, v1.16b
; CHECK-GI-NEXT: add sp, sp, #160
; CHECK-GI-NEXT: ret
@@ -1591,7 +1589,6 @@ define <3 x float> @exp2_v3f32(<3 x float> %a) {
; CHECK-GI-NEXT: ldp d9, d8, [sp, #32] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v1.s[1], v2.s[0]
; CHECK-GI-NEXT: mov v1.s[2], v0.s[0]
-; CHECK-GI-NEXT: mov v1.s[3], v0.s[0]
; CHECK-GI-NEXT: mov v0.16b, v1.16b
; CHECK-GI-NEXT: add sp, sp, #64
; CHECK-GI-NEXT: ret
@@ -1962,7 +1959,6 @@ define <7 x half> @exp2_v7f16(<7 x half> %a) {
; CHECK-GI-NEXT: mov v1.h[4], v3.h[0]
; CHECK-GI-NEXT: mov v1.h[5], v2.h[0]
; CHECK-GI-NEXT: mov v1.h[6], v0.h[0]
-; CHECK-GI-NEXT: mov v1.h[7], v0.h[0]
; CHECK-GI-NEXT: mov v0.16b, v1.16b
; CHECK-GI-NEXT: add sp, sp, #160
; CHECK-GI-NEXT: ret
@@ -2850,7 +2846,6 @@ define <3 x float> @log_v3f32(<3 x float> %a) {
; CHECK-GI-NEXT: ldp d9, d8, [sp, #32] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v1.s[1], v2.s[0]
; CHECK-GI-NEXT: mov v1.s[2], v0.s[0]
-; CHECK-GI-NEXT: mov v1.s[3], v0.s[0]
; CHECK-GI-NEXT: mov v0.16b, v1.16b
; CHECK-GI-NEXT: add sp, sp, #64
; CHECK-GI-NEXT: ret
@@ -3221,7 +3216,6 @@ define <7 x half> @log_v7f16(<7 x half> %a) {
; CHECK-GI-NEXT: mov v1.h[4], v3.h[0]
; CHECK-GI-NEXT: mov v1.h[5], v2.h[0]
; CHECK-GI-NEXT: mov v1.h[6], v0.h[0]
-; CHECK-GI-NEXT: mov v1.h[7], v0.h[0]
; CHECK-GI-NEXT: mov v0.16b, v1.16b
; CHECK-GI-NEXT: add sp, sp, #160
; CHECK-GI-NEXT: ret
@@ -4109,7 +4103,6 @@ define <3 x float> @log2_v3f32(<3 x float> %a) {
; CHECK-GI-NEXT: ldp d9, d8, [sp, #32] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v1.s[1], v2.s[0]
; CHECK-GI-NEXT: mov v1.s[2], v0.s[0]
-; CHECK-GI-NEXT: mov v1.s[3], v0.s[0]
; CHECK-GI-NEXT: mov v0.16b, v1.16b
; CHECK-GI-NEXT: add sp, sp, #64
; CHECK-GI-NEXT: ret
@@ -4480,7 +4473,6 @@ define <7 x half> @log2_v7f16(<7 x half> %a) {
; CHECK-GI-NEXT: mov v1.h[4], v3.h[0]
; CHECK-GI-NEXT: mov v1.h[5], v2.h[0]
; CHECK-GI-NEXT: mov v1.h[6], v0.h[0]
-; CHECK-GI-NEXT: mov v1.h[7], v0.h[0]
; CHECK-GI-NEXT: mov v0.16b, v1.16b
; CHECK-GI-NEXT: add sp, sp, #160
; CHECK-GI-NEXT: ret
@@ -5368,7 +5360,6 @@ define <3 x float> @log10_v3f32(<3 x float> %a) {
; CHECK-GI-NEXT: ldp d9, d8, [sp, #32] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v1.s[1], v2.s[0]
; CHECK-GI-NEXT: mov v1.s[2], v0.s[0]
-; CHECK-GI-NEXT: mov v1.s[3], v0.s[0]
; CHECK-GI-NEXT: mov v0.16b, v1.16b
; CHECK-GI-NEXT: add sp, sp, #64
; CHECK-GI-NEXT: ret
@@ -5739,7 +5730,6 @@ define <7 x half> @log10_v7f16(<7 x half> %a) {
; CHECK-GI-NEXT: mov v1.h[4], v3.h[0]
; CHECK-GI-NEXT: mov v1.h[5], v2.h[0]
; CHECK-GI-NEXT: mov v1.h[6], v0.h[0]
-; CHECK-GI-NEXT: mov v1.h[7], v0.h[0]
; CHECK-GI-NEXT: mov v0.16b, v1.16b
; CHECK-GI-NEXT: add sp, sp, #160
; CHECK-GI-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/fminimummaximum.ll b/llvm/test/CodeGen/AArch64/fminimummaximum.ll
index f0e946c1399874..357d91960624bd 100644
--- a/llvm/test/CodeGen/AArch64/fminimummaximum.ll
+++ b/llvm/test/CodeGen/AArch64/fminimummaximum.ll
@@ -334,41 +334,39 @@ define <7 x float> @min_v7f32(<7 x float> %a, <7 x float> %b) {
;
; CHECK-GI-LABEL: min_v7f32:
; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ldr s16, [sp]
; CHECK-GI-NEXT: // kill: def $s0 killed $s0 def $q0
+; CHECK-GI-NEXT: // kill: def $s7 killed $s7 def $q7
; CHECK-GI-NEXT: // kill: def $s1 killed $s1 def $q1
-; CHECK-GI-NEXT: ldr s16, [sp]
-; CHECK-GI-NEXT: ldr s17, [sp, #24]
+; CHECK-GI-NEXT: ldr s17, [sp, #32]
; CHECK-GI-NEXT: // kill: def $s4 killed $s4 def $q4
-; CHECK-GI-NEXT: // kill: def $s7 killed $s7 def $q7
; CHECK-GI-NEXT: // kill: def $s2 killed $s2 def $q2
; CHECK-GI-NEXT: // kill: def $s5 killed $s5 def $q5
-; CHECK-GI-NEXT: // kill: def $s6 killed $s6 def $q6
; CHECK-GI-NEXT: // kill: def $s3 killed $s3 def $q3
-; CHECK-GI-NEXT: ldr s18, [sp, #32]
+; CHECK-GI-NEXT: // kill: def $s6 killed $s6 def $q6
; CHECK-GI-NEXT: mov v0.s[1], v1.s[0]
-; CHECK-GI-NEXT: mov v4.s[1], v5.s[0]
; CHECK-GI-NEXT: ldr s1, [sp, #8]
+; CHECK-GI-NEXT: mov v4.s[1], v5.s[0]
; CHECK-GI-NEXT: mov v7.s[1], v16.s[0]
-; CHECK-GI-NEXT: mov v17.s[1], v18.s[0]
-; CHECK-GI-NEXT: ldr s5, [sp, #40]
+; CHECK-GI-NEXT: ldr s16, [sp, #24]
+; CHECK-GI-NEXT: mov v16.s[1], v17.s[0]
; CHECK-GI-NEXT: mov v0.s[2], v2.s[0]
+; CHECK-GI-NEXT: ldr s2, [sp, #40]
; CHECK-GI-NEXT: mov v4.s[2], v6.s[0]
; CHECK-GI-NEXT: mov v7.s[2], v1.s[0]
-; CHECK-GI-NEXT: mov v17.s[2], v5.s[0]
; CHECK-GI-NEXT: ldr s1, [sp, #16]
+; CHECK-GI-NEXT: mov v16.s[2], v2.s[0]
; CHECK-GI-NEXT: mov v0.s[3], v3.s[0]
; CHECK-GI-NEXT: mov v7.s[3], v1.s[0]
-; CHECK-GI-NEXT: mov v4.s[3], v0.s[0]
-; CHECK-GI-NEXT: mov v17.s[3], v0.s[0]
+; CHECK-GI-NEXT: fmin v4.4s, v4.4s, v16.4s
; CHECK-GI-NEXT: fmin v0.4s, v0.4s, v7.4s
-; CHECK-GI-NEXT: fmin v4.4s, v4.4s, v17.4s
+; CHECK-GI-NEXT: mov s5, v4.s[1]
+; CHECK-GI-NEXT: mov s6, v4.s[2]
+; CHECK-GI-NEXT: // kill: def $s4 killed $s4 killed $q4
; CHECK-GI-NEXT: mov s1, v0.s[1]
; CHECK-GI-NEXT: mov s2, v0.s[2]
; CHECK-GI-NEXT: mov s3, v0.s[3]
; CHECK-GI-NEXT: // kill: def $s0 killed $s0 killed $q0
-; CHECK-GI-NEXT: mov s5, v4.s[1]
-; CHECK-GI-NEXT: mov s6, v4.s[2]
-; CHECK-GI-NEXT: // kill: def $s4 killed $s4 killed $q4
; CHECK-GI-NEXT: ret
entry:
%c = call <7 x float> @llvm.minimum.v7f32(<7 x float> %a, <7 x float> %b)
@@ -415,41 +413,39 @@ define <7 x float> @max_v7f32(<7 x float> %a, <7 x float> %b) {
;
; CHECK-GI-LABEL: max_v7f32:
; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ldr s16, [sp]
; CHECK-GI-NEXT: // kill: def $s0 killed $s0 def $q0
+; CHECK-GI-NEXT: // kill: def $s7 killed $s7 def $q7
; CHECK-GI-NEXT: // kill: def $s1 killed $s1 def $q1
-; CHECK-GI-NEXT: ldr s16, [sp]
-; CHECK-GI-NEXT: ldr s17, [sp, #24]
+; CHECK-GI-NEXT: ldr s17, [sp, #32]
; CHECK-GI-NEXT: // kill: def $s4 killed $s4 def $q4
-; CHECK-GI-NEXT: // kill: def $s7 killed $s7 def $q7
; CHECK-GI-NEXT: // kill: def $s2 killed $s2 def $q2
; CHECK-GI-NEXT: // kill: def $s5 killed $s5 def $q5
-; CHECK-GI-NEXT: // kill: def $s6 killed $s6 def $q6
; CHECK-GI-NEXT: // kill: def $s3 killed $s3 def $q3
-; CHECK-GI-NEXT: ldr s18, [sp, #32]
+; CHECK-GI-NEXT: // kill: def $s6 killed $s6 def $q6
; CHECK-GI-NEXT: mov v0.s[1], v1.s[0]
-; CHECK-GI-NEXT: mov v4.s[1], v5.s[0]
; CHECK-GI-NEXT: ldr s1, [sp, #8]
+; CHECK-GI-NEXT: mov v4.s[1], v5.s[0]
; CHECK-GI-NEXT: mov v7.s[1], v16.s[0]
-; CHECK-GI-NEXT: mov v17.s[1], v18.s[0]
-; CHECK-GI-NEXT: ldr s5, [sp, #40]
+; CHECK-GI-NEXT: ldr s16, [sp, #24]
+; CHECK-GI-NEXT: mov v16.s[1], v17.s[0]
; CHECK-GI-NEXT: mov v0.s[2], v2.s[0]
+; CHECK-GI-NEXT: ldr s2, [sp, #40]
; CHECK-GI-NEXT: mov v4.s[2], v6.s[0]
; CHECK-GI-NEXT: mov v7.s[2], v1.s[0]
-; CHECK-GI-NEXT: mov v17.s[2], v5.s[0]
; CHECK-GI-NEXT: ldr s1, [sp, #16]
+; CHECK-GI-NEXT: mov v16.s[2], v2.s[0]
; CHECK-GI-NEXT: mov v0.s[3], v3.s[0]
; CHECK-GI-NEXT: mov v7.s[3], v1.s[0]
-; CHECK-GI-NEXT: mov v4.s[3], v0.s[0]
-; CHECK-GI-NEXT: mov v17.s[3], v0.s[0]
+; CHECK-GI-NEXT: fmax v4.4s, v4.4s, v16.4s
; CHECK-GI-NEXT: fmax v0.4s, v0.4s, v7.4s
-; CHECK-GI-NEXT: fmax v4.4s, v4.4s, v17.4s
+; CHECK-GI-NEXT: mov s5, v4.s[1]
+; CHECK-GI-NEXT: mov s6, v4.s[2]
+; CHECK-GI-NEXT: // kill: def $s4 killed $s4 killed $q4
; CHECK-GI-NEXT: mov s1, v0.s[1]
; CHECK-GI-NEXT: mov s2, v0.s[2]
; CHECK-GI-NEXT: mov s3, v0.s[3]
; CHECK-GI-NEXT: // kill: def $s0 killed $s0 killed $q0
-; CHECK-GI-NEXT: mov s5, v4.s[1]
-; CHECK-GI-NEXT: mov s6, v4.s[2]
-; CHECK-GI-NEXT: // kill: def $s4 killed $s4 killed $q4
; CHECK-GI-NEXT: ret
entry:
%c = call <7 x float> @llvm.maximum.v7f32(<7 x float> %a, <7 x float> %b)
@@ -666,26 +662,24 @@ define <7 x half> @min_v7f16(<7 x half> %a, <7 x half> %b) {
;
; CHECK-NOFP16-GI-LABEL: min_v7f16:
; CHECK-NOFP16-GI: // %bb.0: // %entry
-; CHECK-NOFP16-GI-NEXT: mov h2, v0.h[4]
-; CHECK-NOFP16-GI-NEXT: mov h3, v0.h[5]
-; CHECK-NOFP16-GI-NEXT: mov h4, v1.h[4]
-; CHECK-NOFP16-GI-NEXT: mov h5, v1.h[5]
-; CHECK-NOFP16-GI-NEXT: fcvtl v6.4s, v0.4h
-; CHECK-NOFP16-GI-NEXT: fcvtl v7.4s, v1.4h
-; CHECK-NOFP16-GI-NEXT: mov h0, v0.h[6]
+; CHECK-NOFP16-GI-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-NOFP16-GI-NEXT: fcvtl v3.4s, v1.4h
+; CHECK-NOFP16-GI-NEXT: mov h4, v0.h[4]
+; CHECK-NOFP16-GI-NEXT: mov h5, v0.h[5]
+; CHECK-NOFP16-GI-NEXT: mov h6, v1.h[4]
+; CHECK-NOFP16-GI-NEXT: mov h7, v1.h[5]
; CHECK-NOFP16-GI-NEXT: mov h1, v1.h[6]
-; CHECK-NOFP16-GI-NEXT: mov v2.h[1], v3.h[0]
+; CHECK-NOFP16-GI-NEXT: fmin v2.4s, v2.4s, v3.4s
+; CHECK-NOFP16-GI-NEXT: mov h3, v0.h[6]
; CHECK-NOFP16-GI-NEXT: mov v4.h[1], v5.h[0]
-; CHECK-NOFP16-GI-NEXT: fmin v3.4s, v6.4s, v7.4s
-; CHECK-NOFP16-GI-NEXT: mov v2.h[2], v0.h[0]
-; CHECK-NOFP16-GI-NEXT: mov v4.h[2], v1.h[0]
-; CHECK-NOFP16-GI-NEXT: fcvtn v0.4h, v3.4s
-; CHECK-NOFP16-GI-NEXT: mov v2.h[3], v0.h[0]
-; CHECK-NOFP16-GI-NEXT: mov v4.h[3], v0.h[0]
+; CHECK-NOFP16-GI-NEXT: mov v6.h[1], v7.h[0]
+; CHECK-NOFP16-GI-NEXT: fcvtn v0.4h, v2.4s
+; CHECK-NOFP16-GI-NEXT: mov v4.h[2], v3.h[0]
+; CHECK-NOFP16-GI-NEXT: mov v6.h[2], v1.h[0]
; CHECK-NOFP16-GI-NEXT: mov h1, v0.h[1]
; CHECK-NOFP16-GI-NEXT: mov h5, v0.h[3]
-; CHECK-NOFP16-GI-NEXT: fcvtl v2.4s, v2.4h
-; CHECK-NOFP16-GI-NEXT: fcvtl v3.4s, v4.4h
+; CHECK-NOFP16-GI-NEXT: fcvtl v2.4s, v4.4h
+; CHECK-NOFP16-GI-NEXT: fcvtl v3.4s, v6.4h
; CHECK-NOFP16-GI-NEXT: mov h4, v0.h[2]
; CHECK-NOFP16-GI-NEXT: mov v0.h[1], v1.h[0]
; CHECK-NOFP16-GI-NEXT: fmin v1.4s, v2.4s, v3.4s
@@ -697,7 +691,6 @@ define <7 x half> @min_v7f16(<7 x half> %a, <7 x half> %b) {
; CHECK-NOFP16-GI-NEXT: mov h1, v1.h[2]
; CHECK-NOFP16-GI-NEXT: mov v0.h[5], v2.h[0]
; CHECK-NOFP16-GI-NEXT: mov v0.h[6], v1.h[0]
-; CHECK-NOFP16-GI-NEXT: mov v0.h[7], v0.h[0]
; CHECK-NOFP16-GI-NEXT: ret
;
; CHECK-FP16-GI-LABEL: min_v7f16:
@@ -775,26 +768,24 @@ define <7 x half> @max_v7f16(<7 x half> %a, <7 x half> %b) {
;
; CHECK-NOFP16-GI-LABEL: max_v7f16:
; CHECK-NOFP16-GI: // %bb.0: // %entry
-; CHECK-NOFP16-GI-NEXT: mov h2, v0.h[4]
-; CHECK-NOFP16-GI-NEXT: mov h3, v0.h[5]
-; CHECK-NOFP16-GI-NEXT: mov h4, v1.h[4]
-; CHECK-NOFP16-GI-NEXT: mov h5, v1.h[5]
-; CHECK-NOFP16-GI-NEXT: fcvtl v6.4s, v0.4h
-; CHECK-NOFP16-GI-NEXT: fcvtl v7.4s, v1.4h
-; CHECK-NOFP16-GI-NEXT: mov h0, v0.h[6]
+; CHECK-NOFP16-GI-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-NOFP16-GI-NEXT: fcvtl v3.4s, v1.4h
+; CHECK-NOFP16-GI-NEXT: mov h4, v0.h[4]
+; CHECK-NOFP16-GI-NEXT: mov h5, v0.h[5]
+; CHECK-NOFP16-GI-NEXT: mov h6, v1.h[4]
+; CHECK-NOFP16-GI-NEXT: mov h7, v1.h[5]
; CHECK-NOFP16-GI-NEXT: mov h1, v1.h[6]
-; CHECK-NOFP16-GI-NEXT: mov v2.h[1], v3.h[0]
+; CHECK-NOFP16-GI-NEXT: fmax v2.4s, v2.4s, v3.4s
+; CHECK-NOFP16-GI-NEXT: mov h3, v0.h[6]
; CHECK-NOFP16-GI-NEXT: mov v4.h[1], v5.h[0]
-; CHECK-NOFP16-GI-NEXT: fmax v3.4s, v6.4s, v7.4s
-; CHECK-NOFP16-GI-NEXT: mov v2.h[2], v0.h[0]
-; CHECK-NOFP16-GI-NEXT: mov v4.h[2], v1.h[0]
-; CHECK-NOFP16-GI-NEXT: fcvtn v0.4h, v3.4s
-; CHECK-NOFP16-GI-NEXT: mov v2.h[3], v0.h[0]
-; CHECK-NOFP16-GI-NEXT: mov v4.h[3], v0.h[0]
+; CHECK-NOFP16-GI-NEXT: mov v6.h[1], v7.h[0]
+; CHECK-NOFP16-GI-NEXT: fcvtn v0.4h, v2.4s
+; CHECK-NOFP16-GI-NEXT: mov v4.h[2], v3.h[0]
+; CHECK-NOFP16-GI-NEXT: mov v6.h[2], v1.h[0]
; CHECK-NOFP16-GI-NEXT: mov h1, v0.h[1]
; CHECK-NOFP16-GI-NEXT: mov h5, v0.h[3]
-; CHECK-NOFP16-GI-NEXT: fcvtl v2.4s, v2.4h
-; CHECK-NOFP16-GI-NEXT: fcvtl v3.4s, v4.4h
+; CHECK-NOFP16-GI-NEXT: fcvtl v2.4s, v4.4h
+; CHECK-NOFP16-GI-NEXT: fcvtl v3.4s, v6.4h
; CHECK-NOFP16-GI-NEXT: mov h4, v0.h[2]
; CHECK-NOFP16-GI-NEXT: mov v0.h[1], v1.h[0]
; CHECK-NOFP16-GI-NEXT: fmax v1.4s, v2.4s, v3.4s
@@ -806,7 +797,6 @@ define <7 x half> @max_v7f16(<7 x half> %a, <7 x half> %b) {
; CHECK-NOFP16-GI-NEXT: mov h1, v1.h[2]
; CHECK-NOFP16-GI-NEXT: mov v0.h[5], v2.h[0]
; CHECK-NOFP16-GI-NEXT: mov v0.h[6], v1.h[0]
-; CHECK-NOFP16-GI-NEXT: mov v0.h[7], v0.h[0]
; CHECK-NOFP16-GI-NEXT: ret
;
; CHECK-FP16-GI-LABEL: max_v7f16:
diff --git a/llvm/test/CodeGen/AArch64/fminmax.ll b/llvm/test/CodeGen/AArch64/fminmax.ll
index cdf9973b49f46b..61199f82615bbe 100644
--- a/llvm/test/CodeGen/AArch64/fminmax.ll
+++ b/llvm/test/CodeGen/AArch64/fminmax.ll
@@ -334,41 +334,39 @@ define <7 x float> @min_v7f32(<7 x float> %a, <7 x float> %b) {
;
; CHECK-GI-LABEL: min_v7f32:
; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ldr s16, [sp]
; CHECK-GI-NEXT: // kill: def $s0 killed $s0 def $q0
+; CHECK-GI-NEXT: // kill: def $s7 killed $s7 def $q7
; CHECK-GI-NEXT: // kill: def $s1 killed $s1 def $q1
-; CHECK-GI-NEXT: ldr s16, [sp]
-; CHECK-GI-NEXT: ldr s17, [sp, #24]
+; CHECK-GI-NEXT: ldr s17, [sp, #32]
; CHECK-GI-NEXT: // kill: def $s4 killed $s4 def $q4
-; CHECK-GI-NEXT: // kill: def $s7 killed $s7 def $q7
; CHECK-GI-NEXT: // kill: def $s2 killed $s2 def $q2
; CHECK-GI-NEXT: // kill: def $s5 killed $s5 def $q5
-; CHECK-GI-NEXT: // kill: def $s6 killed $s6 def $q6
; CHECK-GI-NEXT: // kill: def $s3 killed $s3 def $q3
-; CHECK-GI-NEXT: ldr s18, [sp, #32]
+; CHECK-GI-NEXT: // kill: def $s6 killed $s6 def $q6
; CHECK-GI-NEXT: mov v0.s[1], v1.s[0]
-; CHECK-GI-NEXT: mov v4.s[1], v5.s[0]
; CHECK-GI-NEXT: ldr s1, [sp, #8]
+; CHECK-GI-NEXT: mov v4.s[1], v5.s[0]
; CHECK-GI-NEXT: mov v7.s[1], v16.s[0]
-; CHECK-GI-NEXT: mov v17.s[1], v18.s[0]
-; CHECK-GI-NEXT: ldr s5, [sp, #40]
+; CHECK-GI-NEXT: ldr s16, [sp, #24]
+; CHECK-GI-NEXT: mov v16.s[1], v17.s[0]
; CHECK-GI-NEXT: mov v0.s[2], v2.s[0]
+; CHECK-GI-NEXT: ldr s2, [sp, #40]
; CHECK-GI-NEXT: mov v4.s[2], v6.s[0]
; CHECK-GI-NEXT: mov v7.s[2], v1.s[0]
-; CHECK-GI-NEXT: mov v17.s[2], v5.s[0]
; CHECK-GI-NEXT: ldr s1, [sp, #16]
+; CHECK-GI-NEXT: mov v16.s[2], v2.s[0]
; CHECK-GI-NEXT: mov v0.s[3], v3.s[0]
; CHECK-GI-NEXT: mov v7.s[3], v1.s[0]
-; CHECK-GI-NEXT: mov v4.s[3], v0.s[0]
-; CHECK-GI-NEXT: mov v17.s[3], v0.s[0]
+; CHECK-GI-NEXT: fminnm v4.4s, v4.4s, v16.4s
; CHECK-GI-NEXT: fminnm v0.4s, v0.4s, v7.4s
-; CHECK-GI-NEXT: fminnm v4.4s, v4.4s, v17.4s
+; CHECK-GI-NEXT: mov s5, v4.s[1]
+; CHECK-GI-NEXT: mov s6, v4.s[2]
+; CHECK-GI-NEXT: // kill: def $s4 killed $s4 killed $q4
; CHECK-GI-NEXT: mov s1, v0.s[1]
; CHECK-GI-NEXT: mov s2, v0.s[2]
; CHECK-GI-NEXT: mov s3, v0.s[3]
; CHECK-GI-NEXT: // kill: def $s0 killed $s0 killed $q0
-; CHECK-GI-NEXT: mov s5, v4.s[1]
-; CHECK-GI-NEXT: mov s6, v4.s[2]
-; CHECK-GI-NEXT: // kill: def $s4 killed $s4 killed $q4
; CHECK-GI-NEXT: ret
entry:
%c = call <7 x float> @llvm.minnum.v7f32(<7 x float> %a, <7 x float> %b)
@@ -415,41 +413,39 @@ define <7 x float> @max_v7f32(<7 x float> %a, <7 x float> %b) {
;
; CHECK-GI-LABEL: max_v7f32:
; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ldr s16, [sp]
; CHECK-GI-NEXT: // kill: def $s0 killed $s0 def $q0
+; CHECK-GI-NEXT: // kill: def $s7 killed $s7 def $q7
; CHECK-GI-NEXT: // kill: def $s1 killed $s1 def $q1
-; CHECK-GI-NEXT: ldr s16, [sp]
-; CHECK-GI-NEXT: ldr s17, [sp, #24]
+; CHECK-GI-NEXT: ldr s17, [sp, #32]
; CHECK-GI-NEXT: // kill: def $s4 killed $s4 def $q4
-; CHECK-GI-NEXT: // kill: def $s7 killed $s7 def $q7
; CHECK-GI-NEXT: // kill: def $s2 killed $s2 def $q2
; CHECK-GI-NEXT: // kill: def $s5 killed $s5 def $q5
-; CHECK-GI-NEXT: // kill: def $s6 killed $s6 def $q6
; CHECK-GI-NEXT: // kill: def $s3 killed $s3 def $q3
-; CHECK-GI-NEXT: ldr s18, [sp, #32]
+; CHECK-GI-NEXT: // kill: def $s6 killed $s6 def $q6
; CHECK-GI-NEXT: mov v0.s[1], v1.s[0]
-; CHECK-GI-NEXT: mov v4.s[1], v5.s[0]
; CHECK-GI-NEXT: ldr s1, [sp, #8]
+; CHECK-GI-NEXT: mov v4.s[1], v5.s[0]
; CHECK-GI-NEXT: mov v7.s[1], v16.s[0]
-; CHECK-GI-NEXT: mov v17.s[1], v18.s[0]
-; CHECK-GI-NEXT: ldr s5, [sp, #40]
+; CHECK-GI-NEXT: ldr s16, [sp, #24]
+; CHECK-GI-NEXT: mov v16.s[1], v17.s[0]
; CHECK-GI-NEXT: mov v0.s[2], v2.s[0]
+; CHECK-GI-NEXT: ldr s2, [sp, #40]
; CHECK-GI-NEXT: mov v4.s[2], v6.s[0]
; CHECK-GI-NEXT: mov v7.s[2], v1.s[0]
-; CHECK-GI-NEXT: mov v17.s[2], v5.s[0]
; CHECK-GI-NEXT: ldr s1, [sp, #16]
+; CHECK-GI-NEXT: mov v16.s[2], v2.s[0]
; CHECK-GI-NEXT: mov v0.s[3], v3.s[0]
; CHECK-GI-NEXT: mov v7.s[3], v1.s[0]
-; CHECK-GI-NEXT: mov v4.s[3], v0.s[0]
-; CHECK-GI-NEXT: mov v17.s[3], v0.s[0]
+; CHECK-GI-NEXT: fmaxnm v4.4s, v4.4s, v16.4s
; CHECK-GI-NEXT: fmaxnm v0.4s, v0.4s, v7.4s
-; CHECK-GI-NEXT: fmaxnm v4.4s, v4.4s, v17.4s
+; CHECK-GI-NEXT: mov s5, v4.s[1]
+; CHECK-GI-NEXT: mov s6, v4.s[2]
+; CHECK-GI-NEXT: // kill: def $s4 killed $s4 killed $q4
; CHECK-GI-NEXT: mov s1, v0.s[1]
; CHECK-GI-NEXT: mov s2, v0.s[2]
; CHECK-GI-NEXT: mov s3, v0.s[3]
; CHECK-GI-NEXT: // kill: def $s0 killed $s0 killed $q0
-; CHECK-GI-NEXT: mov s5, v4.s[1]
-; CHECK-GI-NEXT: mov s6, v4.s[2]
-; CHECK-GI-NEXT: // kill: def $s4 killed $s4 killed $q4
; CHECK-GI-NEXT: ret
entry:
%c = call <7 x float> @llvm.maxnum.v7f32(<7 x float> %a, <7 x float> %b)
@@ -666,26 +662,24 @@ define <7 x half> @min_v7f16(<7 x half> %a, <7 x half> %b) {
;
; CHECK-NOFP16-GI-LABEL: min_v7f16:
; CHECK-NOFP16-GI: // %bb.0: // %entry
-; CHECK-NOFP16-GI-NEXT: mov h2, v0.h[4]
-; CHECK-NOFP16-GI-NEXT: mov h3, v0.h[5]
-; CHECK-NOFP16-GI-NEXT: mov h4, v1.h[4]
-; CHECK-NOFP16-GI-NEXT: mov h5, v1.h[5]
-; CHECK-NOFP16-GI-NEXT: fcvtl v6.4s, v0.4h
-; CHECK-NOFP16-GI-NEXT: fcvtl v7.4s, v1.4h
-; CHECK-NOFP16-GI-NEXT: mov h0, v0.h[6]
+; CHECK-NOFP16-GI-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-NOFP16-GI-NEXT: fcvtl v3.4s, v1.4h
+; CHECK-NOFP16-GI-NEXT: mov h4, v0.h[4]
+; CHECK-NOFP16-GI-NEXT: mov h5, v0.h[5]
+; CHECK-NOFP16-GI-NEXT: mov h6, v1.h[4]
+; CHECK-NOFP16-GI-NEXT: mov h7, v1.h[5]
; CHECK-NOFP16-GI-NEXT: mov h1, v1.h[6]
-; CHECK-NOFP16-GI-NEXT: mov v2.h[1], v3.h[0]
+; CHECK-NOFP16-GI-NEXT: fminnm v2.4s, v2.4s, v3.4s
+; CHECK-NOFP16-GI-NEXT: mov h3, v0.h[6]
; CHECK-NOFP16-GI-NEXT: mov v4.h[1], v5.h[0]
-; CHECK-NOFP16-GI-NEXT: fminnm v3.4s, v6.4s, v7.4s
-; CHECK-NOFP16-GI-NEXT: mov v2.h[2], v0.h[0]
-; CHECK-NOFP16-GI-NEXT: mov v4.h[2], v1.h[0]
-; CHECK-NOFP16-GI-NEXT: fcvtn v0.4h, v3.4s
-; CHECK-NOFP16-GI-NEXT: mov v2.h[3], v0.h[0]
-; CHECK-NOFP16-GI-NEXT: mov v4.h[3], v0.h[0]
+; CHECK-NOFP16-GI-NEXT: mov v6.h[1], v7.h[0]
+; CHECK-NOFP16-GI-NEXT: fcvtn v0.4h, v2.4s
+; CHECK-NOFP16-GI-NEXT: mov v4.h[2], v3.h[0]
+; CHECK-NOFP16-GI-NEXT: mov v6.h[2], v1.h[0]
; CHECK-NOFP16-GI-NEXT: mov h1, v0.h[1]
; CHECK-NOFP16-GI-NEXT: mov h5, v0.h[3]
-; CHECK-NOFP16-GI-NEXT: fcvtl v2.4s, v2.4h
-; CHECK-NOFP16-GI-NEXT: fcvtl v3.4s, v4.4h
+; CHECK-NOFP16-GI-NEXT: fcvtl v2.4s, v4.4h
+; CHECK-NOFP16-GI-NEXT: fcvtl v3.4s, v6.4h
; CHECK-NOFP16-GI-NEXT: mov h4, v0.h[2]
; CHECK-NOFP16-GI-NEXT: mov v0.h[1], v1.h[0]
; CHECK-NOFP16-GI-NEXT: fminnm v1.4s, v2.4s, v3.4s
@@ -697,7 +691,6 @@ define <7 x half> @min_v7f16(<7 x half> %a, <7 x half> %b) {
; CHECK-NOFP16-GI-NEXT: mov h1, v1.h[2]
; CHECK-NOFP16-GI-NEXT: mov v0.h[5], v2.h[0]
; CHECK-NOFP16-GI-NEXT: mov v0.h[6], v1.h[0]
-; CHECK-NOFP16-GI-NEXT: mov v0.h[7], v0.h[0]
; CHECK-NOFP16-GI-NEXT: ret
;
; CHECK-FP16-GI-LABEL: min_v7f16:
@@ -775,26 +768,24 @@ define <7 x half> @max_v7f16(<7 x half> %a, <7 x half> %b) {
;
; CHECK-NOFP16-GI-LABEL: max_v7f16:
; CHECK-NOFP16-GI: // %bb.0: // %entry
-; CHECK-NOFP16-GI-NEXT: mov h2, v0.h[4]
-; CHECK-NOFP16-GI-NEXT: mov h3, v0.h[5]
-; CHECK-NOFP16-GI-NEXT: mov h4, v1.h[4]
-; CHECK-NOFP16-GI-NEXT: mov h5, v1.h[5]
-; CHECK-NOFP16-GI-NEXT: fcvtl v6.4s, v0.4h
-; CHECK-NOFP16-GI-NEXT: fcvtl v7.4s, v1.4h
-; CHECK-NOFP16-GI-NEXT: mov h0, v0.h[6]
+; CHECK-NOFP16-GI-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-NOFP16-GI-NEXT: fcvtl v3.4s, v1.4h
+; CHECK-NOFP16-GI-NEXT: mov h4, v0.h[4]
+; CHECK-NOFP16-GI-NEXT: mov h5, v0.h[5]
+; CHECK-NOFP16-GI-NEXT: mov h6, v1.h[4]
+; CHECK-NOFP16-GI-NEXT: mov h7, v1.h[5]
; CHECK-NOFP16-GI-NEXT: mov h1, v1.h[6]
-; CHECK-NOFP16-GI-NEXT: mov v2.h[1], v3.h[0]
+; CHECK-NOFP16-GI-NEXT: fmaxnm v2.4s, v2.4s, v3.4s
+; CHECK-NOFP16-GI-NEXT: mov h3, v0.h[6]
; CHECK-NOFP16-GI-NEXT: mov v4.h[1], v5.h[0]
-; CHECK-NOFP16-GI-NEXT: fmaxnm v3.4s, v6.4s, v7.4s
-; CHECK-NOFP16-GI-NEXT: mov v2.h[2], v0.h[0]
-; CHECK-NOFP16-GI-NEXT: mov v4.h[2], v1.h[0]
-; CHECK-NOFP16-GI-NEXT: fcvtn v0.4h, v3.4s
-; CHECK-NOFP16-GI-NEXT: mov v2.h[3], v0.h[0]
-; CHECK-NOFP16-GI-NEXT: mov v4.h[3], v0.h[0]
+; CHECK-NOFP16-GI-NEXT: mov v6.h[1], v7.h[0]
+; CHECK-NOFP16-GI-NEXT: fcvtn v0.4h, v2.4s
+; CHECK-NOFP16-GI-NEXT: mov v4.h[2], v3.h[0]
+; CHECK-NOFP16-GI-NEXT: mov v6.h[2], v1.h[0]
; CHECK-NOFP16-GI-NEXT: mov h1, v0.h[1]
; CHECK-NOFP16-GI-NEXT: mov h5, v0.h[3]
-; CHECK-NOFP16-GI-NEXT: fcvtl v2.4s, v2.4h
-; CHECK-NOFP16-GI-NEXT: fcvtl v3.4s, v4.4h
+; CHECK-NOFP16-GI-NEXT: fcvtl v2.4s, v4.4h
+; CHECK-NOFP16-GI-NEXT: fcvtl v3.4s, v6.4h
; CHECK-NOFP16-GI-NEXT: mov h4, v0.h[2]
; CHECK-NOFP16-GI-NEXT: mov v0.h[1], v1.h[0]
; CHECK-NOFP16-GI-NEXT: fmaxnm v1.4s, v2.4s, v3.4s
@@ -806,7 +797,6 @@ define <7 x half> @max_v7f16(<7 x half> %a, <7 x half> %b) {
; CHECK-NOFP16-GI-NEXT: mov h1, v1.h[2]
; CHECK-NOFP16-GI-NEXT: mov v0.h[5], v2.h[0]
; CHECK-NOFP16-GI-NEXT: mov v0.h[6], v1.h[0]
-; CHECK-NOFP16-GI-NEXT: mov v0.h[7], v0.h[0]
; CHECK-NOFP16-GI-NEXT: ret
;
; CHECK-FP16-GI-LABEL: max_v7f16:
diff --git a/llvm/test/CodeGen/AArch64/fmla.ll b/llvm/test/CodeGen/AArch64/fmla.ll
index 336c9705f399d9..4b019b57d968d3 100644
--- a/llvm/test/CodeGen/AArch64/fmla.ll
+++ b/llvm/test/CodeGen/AArch64/fmla.ll
@@ -254,35 +254,32 @@ define <7 x half> @fma_v7f16(<7 x half> %a, <7 x half> %b, <7 x half> %c) {
;
; CHECK-GI-NOFP16-LABEL: fma_v7f16:
; CHECK-GI-NOFP16: // %bb.0: // %entry
-; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[4]
-; CHECK-GI-NOFP16-NEXT: mov h6, v0.h[5]
-; CHECK-GI-NOFP16-NEXT: mov h4, v1.h[4]
-; CHECK-GI-NOFP16-NEXT: mov h7, v1.h[5]
-; CHECK-GI-NOFP16-NEXT: mov h5, v2.h[4]
-; CHECK-GI-NOFP16-NEXT: mov h16, v2.h[5]
-; CHECK-GI-NOFP16-NEXT: fcvtl v17.4s, v0.4h
-; CHECK-GI-NOFP16-NEXT: fcvtl v18.4s, v1.4h
-; CHECK-GI-NOFP16-NEXT: fcvtl v19.4s, v2.4h
-; CHECK-GI-NOFP16-NEXT: mov h0, v0.h[6]
+; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v0.4h
+; CHECK-GI-NOFP16-NEXT: fcvtl v4.4s, v1.4h
+; CHECK-GI-NOFP16-NEXT: fcvtl v5.4s, v2.4h
+; CHECK-GI-NOFP16-NEXT: mov h6, v0.h[4]
+; CHECK-GI-NOFP16-NEXT: mov h7, v0.h[5]
+; CHECK-GI-NOFP16-NEXT: mov h16, v1.h[4]
+; CHECK-GI-NOFP16-NEXT: mov h17, v1.h[5]
+; CHECK-GI-NOFP16-NEXT: mov h18, v2.h[4]
+; CHECK-GI-NOFP16-NEXT: mov h19, v2.h[5]
; CHECK-GI-NOFP16-NEXT: mov h1, v1.h[6]
; CHECK-GI-NOFP16-NEXT: mov h2, v2.h[6]
-; CHECK-GI-NOFP16-NEXT: mov v3.h[1], v6.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v4.h[1], v7.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v5.h[1], v16.h[0]
-; CHECK-GI-NOFP16-NEXT: fmla v19.4s, v18.4s, v17.4s
-; CHECK-GI-NOFP16-NEXT: mov v3.h[2], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v4.h[2], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v5.h[2], v2.h[0]
-; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v19.4s
-; CHECK-GI-NOFP16-NEXT: mov v3.h[3], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v4.h[3], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v5.h[3], v0.h[0]
+; CHECK-GI-NOFP16-NEXT: fmla v5.4s, v4.4s, v3.4s
+; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[6]
+; CHECK-GI-NOFP16-NEXT: mov v6.h[1], v7.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v16.h[1], v17.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v18.h[1], v19.h[0]
+; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v5.4s
+; CHECK-GI-NOFP16-NEXT: mov v6.h[2], v3.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v16.h[2], v1.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v18.h[2], v2.h[0]
; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[1]
-; CHECK-GI-NOFP16-NEXT: mov h6, v0.h[3]
-; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v3.4h
-; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v4.4h
-; CHECK-GI-NOFP16-NEXT: fcvtl v4.4s, v5.4h
; CHECK-GI-NOFP16-NEXT: mov h5, v0.h[2]
+; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v6.4h
+; CHECK-GI-NOFP16-NEXT: mov h6, v0.h[3]
+; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v16.4h
+; CHECK-GI-NOFP16-NEXT: fcvtl v4.4s, v18.4h
; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v1.h[0]
; CHECK-GI-NOFP16-NEXT: fmla v4.4s, v3.4s, v2.4s
; CHECK-GI-NOFP16-NEXT: mov v0.h[2], v5.h[0]
@@ -293,7 +290,6 @@ define <7 x half> @fma_v7f16(<7 x half> %a, <7 x half> %b, <7 x half> %c) {
; CHECK-GI-NOFP16-NEXT: mov h1, v1.h[2]
; CHECK-GI-NOFP16-NEXT: mov v0.h[5], v2.h[0]
; CHECK-GI-NOFP16-NEXT: mov v0.h[6], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[7], v0.h[0]
; CHECK-GI-NOFP16-NEXT: ret
;
; CHECK-GI-FP16-LABEL: fma_v7f16:
@@ -866,43 +862,40 @@ define <7 x half> @fmuladd_v7f16(<7 x half> %a, <7 x half> %b, <7 x half> %c) {
;
; CHECK-GI-NOFP16-LABEL: fmuladd_v7f16:
; CHECK-GI-NOFP16: // %bb.0: // %entry
-; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[4]
-; CHECK-GI-NOFP16-NEXT: mov h4, v0.h[5]
-; CHECK-GI-NOFP16-NEXT: mov h5, v1.h[4]
-; CHECK-GI-NOFP16-NEXT: mov h6, v1.h[5]
-; CHECK-GI-NOFP16-NEXT: fcvtl v7.4s, v0.4h
-; CHECK-GI-NOFP16-NEXT: fcvtl v16.4s, v1.4h
+; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v0.4h
+; CHECK-GI-NOFP16-NEXT: fcvtl v4.4s, v1.4h
+; CHECK-GI-NOFP16-NEXT: mov h5, v0.h[4]
+; CHECK-GI-NOFP16-NEXT: mov h6, v0.h[5]
+; CHECK-GI-NOFP16-NEXT: mov h7, v1.h[4]
+; CHECK-GI-NOFP16-NEXT: mov h16, v1.h[5]
; CHECK-GI-NOFP16-NEXT: mov h0, v0.h[6]
; CHECK-GI-NOFP16-NEXT: mov h1, v1.h[6]
-; CHECK-GI-NOFP16-NEXT: mov v3.h[1], v4.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v5.h[1], v6.h[0]
-; CHECK-GI-NOFP16-NEXT: fmul v4.4s, v7.4s, v16.4s
-; CHECK-GI-NOFP16-NEXT: fcvtl v6.4s, v2.4h
-; CHECK-GI-NOFP16-NEXT: mov v3.h[2], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v5.h[2], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v4.4s
-; CHECK-GI-NOFP16-NEXT: mov h1, v2.h[4]
+; CHECK-GI-NOFP16-NEXT: fmul v3.4s, v3.4s, v4.4s
; CHECK-GI-NOFP16-NEXT: mov h4, v2.h[5]
-; CHECK-GI-NOFP16-NEXT: mov h2, v2.h[6]
-; CHECK-GI-NOFP16-NEXT: mov v3.h[3], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v5.h[3], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-GI-NOFP16-NEXT: mov v1.h[1], v4.h[0]
-; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v3.4h
-; CHECK-GI-NOFP16-NEXT: fcvtl v4.4s, v5.4h
-; CHECK-GI-NOFP16-NEXT: fadd v0.4s, v0.4s, v6.4s
-; CHECK-GI-NOFP16-NEXT: mov v1.h[2], v2.h[0]
-; CHECK-GI-NOFP16-NEXT: fmul v2.4s, v3.4s, v4.4s
+; CHECK-GI-NOFP16-NEXT: mov v5.h[1], v6.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v7.h[1], v16.h[0]
+; CHECK-GI-NOFP16-NEXT: fcvtn v3.4h, v3.4s
+; CHECK-GI-NOFP16-NEXT: mov v5.h[2], v0.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v7.h[2], v1.h[0]
+; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v2.4h
+; CHECK-GI-NOFP16-NEXT: fcvtl v0.4s, v3.4h
+; CHECK-GI-NOFP16-NEXT: mov h3, v2.h[4]
+; CHECK-GI-NOFP16-NEXT: fcvtl v5.4s, v5.4h
+; CHECK-GI-NOFP16-NEXT: fcvtl v6.4s, v7.4h
+; CHECK-GI-NOFP16-NEXT: fadd v0.4s, v0.4s, v1.4s
+; CHECK-GI-NOFP16-NEXT: mov h1, v2.h[6]
+; CHECK-GI-NOFP16-NEXT: mov v3.h[1], v4.h[0]
+; CHECK-GI-NOFP16-NEXT: fmul v2.4s, v5.4s, v6.4s
; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v0.4s
-; CHECK-GI-NOFP16-NEXT: mov v1.h[3], v0.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v3.h[2], v1.h[0]
; CHECK-GI-NOFP16-NEXT: fcvtn v2.4h, v2.4s
-; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[1]
+; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[1]
+; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v3.4h
; CHECK-GI-NOFP16-NEXT: mov h4, v0.h[2]
-; CHECK-GI-NOFP16-NEXT: mov h5, v0.h[3]
-; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v1.4h
; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v2.4h
-; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v3.h[0]
-; CHECK-GI-NOFP16-NEXT: fadd v1.4s, v2.4s, v1.4s
+; CHECK-GI-NOFP16-NEXT: mov h5, v0.h[3]
+; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v1.h[0]
+; CHECK-GI-NOFP16-NEXT: fadd v1.4s, v2.4s, v3.4s
; CHECK-GI-NOFP16-NEXT: mov v0.h[2], v4.h[0]
; CHECK-GI-NOFP16-NEXT: fcvtn v1.4h, v1.4s
; CHECK-GI-NOFP16-NEXT: mov v0.h[3], v5.h[0]
@@ -911,7 +904,6 @@ define <7 x half> @fmuladd_v7f16(<7 x half> %a, <7 x half> %b, <7 x half> %c) {
; CHECK-GI-NOFP16-NEXT: mov h1, v1.h[2]
; CHECK-GI-NOFP16-NEXT: mov v0.h[5], v2.h[0]
; CHECK-GI-NOFP16-NEXT: mov v0.h[6], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[7], v0.h[0]
; CHECK-GI-NOFP16-NEXT: ret
;
; CHECK-GI-FP16-LABEL: fmuladd_v7f16:
@@ -1368,43 +1360,40 @@ define <7 x half> @fmul_v7f16(<7 x half> %a, <7 x half> %b, <7 x half> %c) {
;
; CHECK-GI-NOFP16-LABEL: fmul_v7f16:
; CHECK-GI-NOFP16: // %bb.0: // %entry
-; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[4]
-; CHECK-GI-NOFP16-NEXT: mov h4, v0.h[5]
-; CHECK-GI-NOFP16-NEXT: mov h5, v1.h[4]
-; CHECK-GI-NOFP16-NEXT: mov h6, v1.h[5]
-; CHECK-GI-NOFP16-NEXT: fcvtl v7.4s, v0.4h
-; CHECK-GI-NOFP16-NEXT: fcvtl v16.4s, v1.4h
+; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v0.4h
+; CHECK-GI-NOFP16-NEXT: fcvtl v4.4s, v1.4h
+; CHECK-GI-NOFP16-NEXT: mov h5, v0.h[4]
+; CHECK-GI-NOFP16-NEXT: mov h6, v0.h[5]
+; CHECK-GI-NOFP16-NEXT: mov h7, v1.h[4]
+; CHECK-GI-NOFP16-NEXT: mov h16, v1.h[5]
; CHECK-GI-NOFP16-NEXT: mov h0, v0.h[6]
; CHECK-GI-NOFP16-NEXT: mov h1, v1.h[6]
-; CHECK-GI-NOFP16-NEXT: mov v3.h[1], v4.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v5.h[1], v6.h[0]
-; CHECK-GI-NOFP16-NEXT: fmul v4.4s, v7.4s, v16.4s
-; CHECK-GI-NOFP16-NEXT: fcvtl v6.4s, v2.4h
-; CHECK-GI-NOFP16-NEXT: mov v3.h[2], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v5.h[2], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v4.4s
-; CHECK-GI-NOFP16-NEXT: mov h1, v2.h[4]
+; CHECK-GI-NOFP16-NEXT: fmul v3.4s, v3.4s, v4.4s
; CHECK-GI-NOFP16-NEXT: mov h4, v2.h[5]
-; CHECK-GI-NOFP16-NEXT: mov h2, v2.h[6]
-; CHECK-GI-NOFP16-NEXT: mov v3.h[3], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v5.h[3], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-GI-NOFP16-NEXT: mov v1.h[1], v4.h[0]
-; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v3.4h
-; CHECK-GI-NOFP16-NEXT: fcvtl v4.4s, v5.4h
-; CHECK-GI-NOFP16-NEXT: fadd v0.4s, v0.4s, v6.4s
-; CHECK-GI-NOFP16-NEXT: mov v1.h[2], v2.h[0]
-; CHECK-GI-NOFP16-NEXT: fmul v2.4s, v3.4s, v4.4s
+; CHECK-GI-NOFP16-NEXT: mov v5.h[1], v6.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v7.h[1], v16.h[0]
+; CHECK-GI-NOFP16-NEXT: fcvtn v3.4h, v3.4s
+; CHECK-GI-NOFP16-NEXT: mov v5.h[2], v0.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v7.h[2], v1.h[0]
+; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v2.4h
+; CHECK-GI-NOFP16-NEXT: fcvtl v0.4s, v3.4h
+; CHECK-GI-NOFP16-NEXT: mov h3, v2.h[4]
+; CHECK-GI-NOFP16-NEXT: fcvtl v5.4s, v5.4h
+; CHECK-GI-NOFP16-NEXT: fcvtl v6.4s, v7.4h
+; CHECK-GI-NOFP16-NEXT: fadd v0.4s, v0.4s, v1.4s
+; CHECK-GI-NOFP16-NEXT: mov h1, v2.h[6]
+; CHECK-GI-NOFP16-NEXT: mov v3.h[1], v4.h[0]
+; CHECK-GI-NOFP16-NEXT: fmul v2.4s, v5.4s, v6.4s
; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v0.4s
-; CHECK-GI-NOFP16-NEXT: mov v1.h[3], v0.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v3.h[2], v1.h[0]
; CHECK-GI-NOFP16-NEXT: fcvtn v2.4h, v2.4s
-; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[1]
+; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[1]
+; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v3.4h
; CHECK-GI-NOFP16-NEXT: mov h4, v0.h[2]
-; CHECK-GI-NOFP16-NEXT: mov h5, v0.h[3]
-; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v1.4h
; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v2.4h
-; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v3.h[0]
-; CHECK-GI-NOFP16-NEXT: fadd v1.4s, v2.4s, v1.4s
+; CHECK-GI-NOFP16-NEXT: mov h5, v0.h[3]
+; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v1.h[0]
+; CHECK-GI-NOFP16-NEXT: fadd v1.4s, v2.4s, v3.4s
; CHECK-GI-NOFP16-NEXT: mov v0.h[2], v4.h[0]
; CHECK-GI-NOFP16-NEXT: fcvtn v1.4h, v1.4s
; CHECK-GI-NOFP16-NEXT: mov v0.h[3], v5.h[0]
@@ -1413,7 +1402,6 @@ define <7 x half> @fmul_v7f16(<7 x half> %a, <7 x half> %b, <7 x half> %c) {
; CHECK-GI-NOFP16-NEXT: mov h1, v1.h[2]
; CHECK-GI-NOFP16-NEXT: mov v0.h[5], v2.h[0]
; CHECK-GI-NOFP16-NEXT: mov v0.h[6], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[7], v0.h[0]
; CHECK-GI-NOFP16-NEXT: ret
;
; CHECK-GI-FP16-LABEL: fmul_v7f16:
diff --git a/llvm/test/CodeGen/AArch64/fmul.ll b/llvm/test/CodeGen/AArch64/fmul.ll
index 1f49601a18272f..1f41f2385c3357 100644
--- a/llvm/test/CodeGen/AArch64/fmul.ll
+++ b/llvm/test/CodeGen/AArch64/fmul.ll
@@ -186,26 +186,24 @@ define <7 x half> @fmul_v7f16(<7 x half> %a, <7 x half> %b) {
;
; CHECK-GI-NOFP16-LABEL: fmul_v7f16:
; CHECK-GI-NOFP16: // %bb.0: // %entry
-; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[4]
-; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[5]
-; CHECK-GI-NOFP16-NEXT: mov h4, v1.h[4]
-; CHECK-GI-NOFP16-NEXT: mov h5, v1.h[5]
-; CHECK-GI-NOFP16-NEXT: fcvtl v6.4s, v0.4h
-; CHECK-GI-NOFP16-NEXT: fcvtl v7.4s, v1.4h
-; CHECK-GI-NOFP16-NEXT: mov h0, v0.h[6]
+; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v1.4h
+; CHECK-GI-NOFP16-NEXT: mov h4, v0.h[4]
+; CHECK-GI-NOFP16-NEXT: mov h5, v0.h[5]
+; CHECK-GI-NOFP16-NEXT: mov h6, v1.h[4]
+; CHECK-GI-NOFP16-NEXT: mov h7, v1.h[5]
; CHECK-GI-NOFP16-NEXT: mov h1, v1.h[6]
-; CHECK-GI-NOFP16-NEXT: mov v2.h[1], v3.h[0]
+; CHECK-GI-NOFP16-NEXT: fmul v2.4s, v2.4s, v3.4s
+; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[6]
; CHECK-GI-NOFP16-NEXT: mov v4.h[1], v5.h[0]
-; CHECK-GI-NOFP16-NEXT: fmul v3.4s, v6.4s, v7.4s
-; CHECK-GI-NOFP16-NEXT: mov v2.h[2], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v4.h[2], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v3.4s
-; CHECK-GI-NOFP16-NEXT: mov v2.h[3], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v4.h[3], v0.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v6.h[1], v7.h[0]
+; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v2.4s
+; CHECK-GI-NOFP16-NEXT: mov v4.h[2], v3.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v6.h[2], v1.h[0]
; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[1]
; CHECK-GI-NOFP16-NEXT: mov h5, v0.h[3]
-; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v2.4h
-; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v4.4h
+; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v4.4h
+; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v6.4h
; CHECK-GI-NOFP16-NEXT: mov h4, v0.h[2]
; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v1.h[0]
; CHECK-GI-NOFP16-NEXT: fmul v1.4s, v2.4s, v3.4s
@@ -217,7 +215,6 @@ define <7 x half> @fmul_v7f16(<7 x half> %a, <7 x half> %b) {
; CHECK-GI-NOFP16-NEXT: mov h1, v1.h[2]
; CHECK-GI-NOFP16-NEXT: mov v0.h[5], v2.h[0]
; CHECK-GI-NOFP16-NEXT: mov v0.h[6], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[7], v0.h[0]
; CHECK-GI-NOFP16-NEXT: ret
;
; CHECK-GI-FP16-LABEL: fmul_v7f16:
diff --git a/llvm/test/CodeGen/AArch64/fneg.ll b/llvm/test/CodeGen/AArch64/fneg.ll
index d5010cf360841a..cc0f7d2fd6075d 100644
--- a/llvm/test/CodeGen/AArch64/fneg.ll
+++ b/llvm/test/CodeGen/AArch64/fneg.ll
@@ -161,21 +161,20 @@ define <7 x half> @fabs_v7f16(<7 x half> %a) {
;
; CHECK-GI-NOFP16-LABEL: fabs_v7f16:
; CHECK-GI-NOFP16: // %bb.0: // %entry
-; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[4]
-; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[5]
-; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v0.4h
-; CHECK-GI-NOFP16-NEXT: mov h0, v0.h[6]
-; CHECK-GI-NOFP16-NEXT: mov v1.h[1], v2.h[0]
-; CHECK-GI-NOFP16-NEXT: fneg v2.4s, v3.4s
-; CHECK-GI-NOFP16-NEXT: mov v1.h[2], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v2.4s
-; CHECK-GI-NOFP16-NEXT: mov v1.h[3], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[1]
+; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[4]
+; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[5]
+; CHECK-GI-NOFP16-NEXT: mov h4, v0.h[6]
+; CHECK-GI-NOFP16-NEXT: fneg v1.4s, v1.4s
+; CHECK-GI-NOFP16-NEXT: mov v2.h[1], v3.h[0]
+; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v1.4s
+; CHECK-GI-NOFP16-NEXT: mov v2.h[2], v4.h[0]
+; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[1]
+; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v2.4h
; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[2]
; CHECK-GI-NOFP16-NEXT: mov h4, v0.h[3]
-; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v1.4h
-; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v2.h[0]
-; CHECK-GI-NOFP16-NEXT: fneg v1.4s, v1.4s
+; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v1.h[0]
+; CHECK-GI-NOFP16-NEXT: fneg v1.4s, v2.4s
; CHECK-GI-NOFP16-NEXT: mov v0.h[2], v3.h[0]
; CHECK-GI-NOFP16-NEXT: fcvtn v1.4h, v1.4s
; CHECK-GI-NOFP16-NEXT: mov v0.h[3], v4.h[0]
@@ -184,7 +183,6 @@ define <7 x half> @fabs_v7f16(<7 x half> %a) {
; CHECK-GI-NOFP16-NEXT: mov h1, v1.h[2]
; CHECK-GI-NOFP16-NEXT: mov v0.h[5], v2.h[0]
; CHECK-GI-NOFP16-NEXT: mov v0.h[6], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[7], v0.h[0]
; CHECK-GI-NOFP16-NEXT: ret
;
; CHECK-GI-FP16-LABEL: fabs_v7f16:
diff --git a/llvm/test/CodeGen/AArch64/fpext.ll b/llvm/test/CodeGen/AArch64/fpext.ll
index 86f7322f7c4eeb..24a2451df48425 100644
--- a/llvm/test/CodeGen/AArch64/fpext.ll
+++ b/llvm/test/CodeGen/AArch64/fpext.ll
@@ -168,8 +168,6 @@ define <2 x float> @fpext_v2f16_v2f32(<2 x half> %a) {
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-GI-NEXT: mov h1, v0.h[1]
; CHECK-GI-NEXT: mov v0.h[1], v1.h[0]
-; CHECK-GI-NEXT: mov v0.h[2], v0.h[0]
-; CHECK-GI-NEXT: mov v0.h[3], v0.h[0]
; CHECK-GI-NEXT: fcvtl v0.4s, v0.4h
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/fpow.ll b/llvm/test/CodeGen/AArch64/fpow.ll
index 1dd5450c271cbe..c2ad1aafd65fc4 100644
--- a/llvm/test/CodeGen/AArch64/fpow.ll
+++ b/llvm/test/CodeGen/AArch64/fpow.ll
@@ -395,7 +395,6 @@ define <3 x float> @pow_v3f32(<3 x float> %a, <3 x float> %b) {
; CHECK-GI-NEXT: ldp d11, d10, [sp, #32] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v1.s[1], v2.s[0]
; CHECK-GI-NEXT: mov v1.s[2], v0.s[0]
-; CHECK-GI-NEXT: mov v1.s[3], v0.s[0]
; CHECK-GI-NEXT: mov v0.16b, v1.16b
; CHECK-GI-NEXT: add sp, sp, #80
; CHECK-GI-NEXT: ret
@@ -856,7 +855,6 @@ define <7 x half> @pow_v7f16(<7 x half> %a, <7 x half> %b) {
; CHECK-GI-NEXT: ldr q2, [sp, #80] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v1.h[5], v2.h[0]
; CHECK-GI-NEXT: mov v1.h[6], v0.h[0]
-; CHECK-GI-NEXT: mov v1.h[7], v0.h[0]
; CHECK-GI-NEXT: mov v0.16b, v1.16b
; CHECK-GI-NEXT: add sp, sp, #176
; CHECK-GI-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/fpowi.ll b/llvm/test/CodeGen/AArch64/fpowi.ll
index b496c7d15eef31..5dbcaa4a5fda17 100644
--- a/llvm/test/CodeGen/AArch64/fpowi.ll
+++ b/llvm/test/CodeGen/AArch64/fpowi.ll
@@ -370,7 +370,6 @@ define <3 x float> @powi_v3f32(<3 x float> %a, i32 %b) {
; CHECK-GI-NEXT: ldp d9, d8, [sp, #32] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v1.s[1], v2.s[0]
; CHECK-GI-NEXT: mov v1.s[2], v0.s[0]
-; CHECK-GI-NEXT: mov v1.s[3], v0.s[0]
; CHECK-GI-NEXT: mov v0.16b, v1.16b
; CHECK-GI-NEXT: add sp, sp, #64
; CHECK-GI-NEXT: ret
@@ -787,7 +786,6 @@ define <7 x half> @powi_v7f16(<7 x half> %a, i32 %b) {
; CHECK-GI-NEXT: mov v1.h[4], v3.h[0]
; CHECK-GI-NEXT: mov v1.h[5], v2.h[0]
; CHECK-GI-NEXT: mov v1.h[6], v0.h[0]
-; CHECK-GI-NEXT: mov v1.h[7], v0.h[0]
; CHECK-GI-NEXT: mov v0.16b, v1.16b
; CHECK-GI-NEXT: add sp, sp, #160
; CHECK-GI-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/fptoi.ll b/llvm/test/CodeGen/AArch64/fptoi.ll
index facb89671056f6..67190e8596c46c 100644
--- a/llvm/test/CodeGen/AArch64/fptoi.ll
+++ b/llvm/test/CodeGen/AArch64/fptoi.ll
@@ -2708,7 +2708,6 @@ define <3 x i16> @fptos_v3f32_v3i16(<3 x float> %a) {
; CHECK-GI-NEXT: mov s2, v0.s[2]
; CHECK-GI-NEXT: mov v0.h[1], v1.h[0]
; CHECK-GI-NEXT: mov v0.h[2], v2.h[0]
-; CHECK-GI-NEXT: mov v0.h[3], v0.h[0]
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
entry:
@@ -2730,7 +2729,6 @@ define <3 x i16> @fptou_v3f32_v3i16(<3 x float> %a) {
; CHECK-GI-NEXT: mov s2, v0.s[2]
; CHECK-GI-NEXT: mov v0.h[1], v1.h[0]
; CHECK-GI-NEXT: mov v0.h[2], v2.h[0]
-; CHECK-GI-NEXT: mov v0.h[3], v0.h[0]
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
entry:
@@ -3243,8 +3241,6 @@ define <2 x i64> @fptos_v2f16_v2i64(<2 x half> %a) {
; CHECK-GI-NOFP16-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[1]
; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[2], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[3], v0.h[0]
; CHECK-GI-NOFP16-NEXT: fcvtl v0.4s, v0.4h
; CHECK-GI-NOFP16-NEXT: fcvtl v0.2d, v0.2s
; CHECK-GI-NOFP16-NEXT: fcvtzs v0.2d, v0.2d
@@ -3292,8 +3288,6 @@ define <2 x i64> @fptou_v2f16_v2i64(<2 x half> %a) {
; CHECK-GI-NOFP16-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[1]
; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[2], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[3], v0.h[0]
; CHECK-GI-NOFP16-NEXT: fcvtl v0.4s, v0.4h
; CHECK-GI-NOFP16-NEXT: fcvtl v0.2d, v0.2s
; CHECK-GI-NOFP16-NEXT: fcvtzu v0.2d, v0.2d
@@ -4996,8 +4990,6 @@ define <2 x i32> @fptos_v2f16_v2i32(<2 x half> %a) {
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-GI-NEXT: mov h1, v0.h[1]
; CHECK-GI-NEXT: mov v0.h[1], v1.h[0]
-; CHECK-GI-NEXT: mov v0.h[2], v0.h[0]
-; CHECK-GI-NEXT: mov v0.h[3], v0.h[0]
; CHECK-GI-NEXT: fcvtl v0.4s, v0.4h
; CHECK-GI-NEXT: fcvtzs v0.2s, v0.2s
; CHECK-GI-NEXT: ret
@@ -5019,8 +5011,6 @@ define <2 x i32> @fptou_v2f16_v2i32(<2 x half> %a) {
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-GI-NEXT: mov h1, v0.h[1]
; CHECK-GI-NEXT: mov v0.h[1], v1.h[0]
-; CHECK-GI-NEXT: mov v0.h[2], v0.h[0]
-; CHECK-GI-NEXT: mov v0.h[3], v0.h[0]
; CHECK-GI-NEXT: fcvtl v0.4s, v0.4h
; CHECK-GI-NEXT: fcvtzu v0.2s, v0.2s
; CHECK-GI-NEXT: ret
@@ -5276,8 +5266,6 @@ define <2 x i16> @fptos_v2f16_v2i16(<2 x half> %a) {
; CHECK-GI-NOFP16-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[1]
; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[2], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[3], v0.h[0]
; CHECK-GI-NOFP16-NEXT: fcvtl v0.4s, v0.4h
; CHECK-GI-NOFP16-NEXT: fcvtzs v0.2s, v0.2s
; CHECK-GI-NOFP16-NEXT: ret
@@ -5306,8 +5294,6 @@ define <2 x i16> @fptou_v2f16_v2i16(<2 x half> %a) {
; CHECK-GI-NOFP16-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[1]
; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[2], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[3], v0.h[0]
; CHECK-GI-NOFP16-NEXT: fcvtl v0.4s, v0.4h
; CHECK-GI-NOFP16-NEXT: fcvtzu v0.2s, v0.2s
; CHECK-GI-NOFP16-NEXT: ret
@@ -5344,7 +5330,6 @@ define <3 x i16> @fptos_v3f16_v3i16(<3 x half> %a) {
; CHECK-GI-NOFP16-NEXT: mov s2, v0.s[2]
; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v1.h[0]
; CHECK-GI-NOFP16-NEXT: mov v0.h[2], v2.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[3], v0.h[0]
; CHECK-GI-NOFP16-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NOFP16-NEXT: ret
;
@@ -5378,7 +5363,6 @@ define <3 x i16> @fptou_v3f16_v3i16(<3 x half> %a) {
; CHECK-GI-NOFP16-NEXT: mov s2, v0.s[2]
; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v1.h[0]
; CHECK-GI-NOFP16-NEXT: mov v0.h[2], v2.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[3], v0.h[0]
; CHECK-GI-NOFP16-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NOFP16-NEXT: ret
;
@@ -5756,8 +5740,6 @@ define <2 x i8> @fptos_v2f16_v2i8(<2 x half> %a) {
; CHECK-GI-NOFP16-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[1]
; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[2], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[3], v0.h[0]
; CHECK-GI-NOFP16-NEXT: fcvtl v0.4s, v0.4h
; CHECK-GI-NOFP16-NEXT: fcvtzs v0.2s, v0.2s
; CHECK-GI-NOFP16-NEXT: ret
@@ -5786,8 +5768,6 @@ define <2 x i8> @fptou_v2f16_v2i8(<2 x half> %a) {
; CHECK-GI-NOFP16-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[1]
; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[2], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[3], v0.h[0]
; CHECK-GI-NOFP16-NEXT: fcvtl v0.4s, v0.4h
; CHECK-GI-NOFP16-NEXT: fcvtzu v0.2s, v0.2s
; CHECK-GI-NOFP16-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/fptrunc.ll b/llvm/test/CodeGen/AArch64/fptrunc.ll
index 3efc98ab5fd532..61dddd442976f8 100644
--- a/llvm/test/CodeGen/AArch64/fptrunc.ll
+++ b/llvm/test/CodeGen/AArch64/fptrunc.ll
@@ -63,7 +63,6 @@ define <3 x float> @fptrunc_v3f64_v3f32(<3 x double> %a) {
; CHECK-GI-NEXT: mov s1, v0.s[1]
; CHECK-GI-NEXT: mov v0.s[1], v1.s[0]
; CHECK-GI-NEXT: mov v0.s[2], v2.s[0]
-; CHECK-GI-NEXT: mov v0.s[3], v0.s[0]
; CHECK-GI-NEXT: ret
entry:
%c = fptrunc <3 x double> %a to <3 x float>
@@ -82,22 +81,14 @@ entry:
}
define <2 x half> @fptrunc_v2f64_v2f16(<2 x double> %a) {
-; CHECK-SD-LABEL: fptrunc_v2f64_v2f16:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: fcvtxn v0.2s, v0.2d
-; CHECK-SD-NEXT: fcvtn v0.4h, v0.4s
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fptrunc_v2f64_v2f16:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: fcvt h0, d0
-; CHECK-GI-NEXT: fcvt h1, d1
-; CHECK-GI-NEXT: mov v0.h[1], v1.h[0]
-; CHECK-GI-NEXT: mov v0.h[2], v0.h[0]
-; CHECK-GI-NEXT: mov v0.h[3], v0.h[0]
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fptrunc_v2f64_v2f16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov d1, v0.d[1]
+; CHECK-NEXT: fcvt h0, d0
+; CHECK-NEXT: fcvt h1, d1
+; CHECK-NEXT: mov v0.h[1], v1.h[0]
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: ret
entry:
%c = fptrunc <2 x double> %a to <2 x half>
ret <2 x half> %c
@@ -121,7 +112,6 @@ define <3 x half> @fptrunc_v3f64_v3f16(<3 x double> %a) {
; CHECK-GI-NEXT: fcvt h2, d2
; CHECK-GI-NEXT: mov v0.h[1], v1.h[0]
; CHECK-GI-NEXT: mov v0.h[2], v2.h[0]
-; CHECK-GI-NEXT: mov v0.h[3], v0.h[0]
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
entry:
@@ -167,13 +157,9 @@ define <2 x half> @fptrunc_v2f32_v2f16(<2 x float> %a) {
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-GI-NEXT: mov s1, v0.s[1]
; CHECK-GI-NEXT: mov v0.s[1], v1.s[0]
-; CHECK-GI-NEXT: mov v0.s[2], v0.s[0]
-; CHECK-GI-NEXT: mov v0.s[3], v0.s[0]
; CHECK-GI-NEXT: fcvtn v0.4h, v0.4s
; CHECK-GI-NEXT: mov h1, v0.h[1]
; CHECK-GI-NEXT: mov v0.h[1], v1.h[0]
-; CHECK-GI-NEXT: mov v0.h[2], v0.h[0]
-; CHECK-GI-NEXT: mov v0.h[3], v0.h[0]
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/AArch64/frem.ll b/llvm/test/CodeGen/AArch64/frem.ll
index 03caf0a33eb459..1a10fd2f1cdc3d 100644
--- a/llvm/test/CodeGen/AArch64/frem.ll
+++ b/llvm/test/CodeGen/AArch64/frem.ll
@@ -397,7 +397,6 @@ define <3 x float> @frem_v3f32(<3 x float> %a, <3 x float> %b) {
; CHECK-GI-NEXT: ldp d11, d10, [sp, #32] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v1.s[1], v2.s[0]
; CHECK-GI-NEXT: mov v1.s[2], v0.s[0]
-; CHECK-GI-NEXT: mov v1.s[3], v0.s[0]
; CHECK-GI-NEXT: mov v0.16b, v1.16b
; CHECK-GI-NEXT: add sp, sp, #80
; CHECK-GI-NEXT: ret
@@ -858,7 +857,6 @@ define <7 x half> @frem_v7f16(<7 x half> %a, <7 x half> %b) {
; CHECK-GI-NEXT: ldr q2, [sp, #80] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v1.h[5], v2.h[0]
; CHECK-GI-NEXT: mov v1.h[6], v0.h[0]
-; CHECK-GI-NEXT: mov v1.h[7], v0.h[0]
; CHECK-GI-NEXT: mov v0.16b, v1.16b
; CHECK-GI-NEXT: add sp, sp, #176
; CHECK-GI-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/fsincos.ll b/llvm/test/CodeGen/AArch64/fsincos.ll
index 2c76d969d6efe1..2ab1610edcc7f1 100644
--- a/llvm/test/CodeGen/AArch64/fsincos.ll
+++ b/llvm/test/CodeGen/AArch64/fsincos.ll
@@ -332,7 +332,6 @@ define <3 x float> @sin_v3f32(<3 x float> %a) {
; CHECK-GI-NEXT: ldp d9, d8, [sp, #32] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v1.s[1], v2.s[0]
; CHECK-GI-NEXT: mov v1.s[2], v0.s[0]
-; CHECK-GI-NEXT: mov v1.s[3], v0.s[0]
; CHECK-GI-NEXT: mov v0.16b, v1.16b
; CHECK-GI-NEXT: add sp, sp, #64
; CHECK-GI-NEXT: ret
@@ -703,7 +702,6 @@ define <7 x half> @sin_v7f16(<7 x half> %a) {
; CHECK-GI-NEXT: mov v1.h[4], v3.h[0]
; CHECK-GI-NEXT: mov v1.h[5], v2.h[0]
; CHECK-GI-NEXT: mov v1.h[6], v0.h[0]
-; CHECK-GI-NEXT: mov v1.h[7], v0.h[0]
; CHECK-GI-NEXT: mov v0.16b, v1.16b
; CHECK-GI-NEXT: add sp, sp, #160
; CHECK-GI-NEXT: ret
@@ -1591,7 +1589,6 @@ define <3 x float> @cos_v3f32(<3 x float> %a) {
; CHECK-GI-NEXT: ldp d9, d8, [sp, #32] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v1.s[1], v2.s[0]
; CHECK-GI-NEXT: mov v1.s[2], v0.s[0]
-; CHECK-GI-NEXT: mov v1.s[3], v0.s[0]
; CHECK-GI-NEXT: mov v0.16b, v1.16b
; CHECK-GI-NEXT: add sp, sp, #64
; CHECK-GI-NEXT: ret
@@ -1962,7 +1959,6 @@ define <7 x half> @cos_v7f16(<7 x half> %a) {
; CHECK-GI-NEXT: mov v1.h[4], v3.h[0]
; CHECK-GI-NEXT: mov v1.h[5], v2.h[0]
; CHECK-GI-NEXT: mov v1.h[6], v0.h[0]
-; CHECK-GI-NEXT: mov v1.h[7], v0.h[0]
; CHECK-GI-NEXT: mov v0.16b, v1.16b
; CHECK-GI-NEXT: add sp, sp, #160
; CHECK-GI-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/fsqrt.ll b/llvm/test/CodeGen/AArch64/fsqrt.ll
index 683544a69ebe1f..4b48bcc5508db0 100644
--- a/llvm/test/CodeGen/AArch64/fsqrt.ll
+++ b/llvm/test/CodeGen/AArch64/fsqrt.ll
@@ -195,17 +195,16 @@ define <7 x half> @sqrt_v7f16(<7 x half> %a) {
;
; CHECK-GI-NOFP16-LABEL: sqrt_v7f16:
; CHECK-GI-NOFP16: // %bb.0: // %entry
-; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[4]
-; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[5]
-; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v0.4h
+; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[4]
+; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[5]
; CHECK-GI-NOFP16-NEXT: mov h0, v0.h[6]
-; CHECK-GI-NOFP16-NEXT: mov v1.h[1], v2.h[0]
-; CHECK-GI-NOFP16-NEXT: fsqrt v2.4s, v3.4s
-; CHECK-GI-NOFP16-NEXT: mov v1.h[2], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v1.h[3], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v1.4h
-; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v2.4s
; CHECK-GI-NOFP16-NEXT: fsqrt v1.4s, v1.4s
+; CHECK-GI-NOFP16-NEXT: mov v2.h[1], v3.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v2.h[2], v0.h[0]
+; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v2.4h
+; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v1.4s
+; CHECK-GI-NOFP16-NEXT: fsqrt v1.4s, v2.4s
; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[1]
; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[2]
; CHECK-GI-NOFP16-NEXT: mov h4, v0.h[3]
@@ -218,7 +217,6 @@ define <7 x half> @sqrt_v7f16(<7 x half> %a) {
; CHECK-GI-NOFP16-NEXT: mov h1, v1.h[2]
; CHECK-GI-NOFP16-NEXT: mov v0.h[5], v2.h[0]
; CHECK-GI-NOFP16-NEXT: mov v0.h[6], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[7], v0.h[0]
; CHECK-GI-NOFP16-NEXT: ret
;
; CHECK-GI-FP16-LABEL: sqrt_v7f16:
diff --git a/llvm/test/CodeGen/AArch64/icmp.ll b/llvm/test/CodeGen/AArch64/icmp.ll
index 2e8c93a00a0d80..e7352fe03d01a8 100644
--- a/llvm/test/CodeGen/AArch64/icmp.ll
+++ b/llvm/test/CodeGen/AArch64/icmp.ll
@@ -177,15 +177,13 @@ define <3 x i32> @v3i32_i32(<3 x i32> %a, <3 x i32> %b, <3 x i32> %d, <3 x i32>
; CHECK-GI-NEXT: mov v4.s[1], w8
; CHECK-GI-NEXT: mov v4.s[2], w8
; CHECK-GI-NEXT: mov w8, #-1 // =0xffffffff
-; CHECK-GI-NEXT: fmov s5, w8
-; CHECK-GI-NEXT: mov v5.s[1], w8
-; CHECK-GI-NEXT: mov v4.s[3], w8
-; CHECK-GI-NEXT: mov v5.s[2], w8
-; CHECK-GI-NEXT: neg v1.4s, v4.4s
+; CHECK-GI-NEXT: fmov s1, w8
+; CHECK-GI-NEXT: mov v1.s[1], w8
+; CHECK-GI-NEXT: neg v5.4s, v4.4s
; CHECK-GI-NEXT: ushl v0.4s, v0.4s, v4.4s
-; CHECK-GI-NEXT: mov v5.s[3], w8
-; CHECK-GI-NEXT: sshl v0.4s, v0.4s, v1.4s
-; CHECK-GI-NEXT: eor v1.16b, v0.16b, v5.16b
+; CHECK-GI-NEXT: mov v1.s[2], w8
+; CHECK-GI-NEXT: sshl v0.4s, v0.4s, v5.4s
+; CHECK-GI-NEXT: eor v1.16b, v0.16b, v1.16b
; CHECK-GI-NEXT: and v0.16b, v2.16b, v0.16b
; CHECK-GI-NEXT: and v1.16b, v3.16b, v1.16b
; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
diff --git a/llvm/test/CodeGen/AArch64/insertextract.ll b/llvm/test/CodeGen/AArch64/insertextract.ll
index b0df5cb3d83717..5c2dd761bdc0da 100644
--- a/llvm/test/CodeGen/AArch64/insertextract.ll
+++ b/llvm/test/CodeGen/AArch64/insertextract.ll
@@ -233,7 +233,6 @@ define <3 x float> @insert_v3f32_0(<3 x float> %a, float %b, i32 %c) {
; CHECK-GI-NEXT: mov s0, v0.s[2]
; CHECK-GI-NEXT: mov v1.s[1], v2.s[0]
; CHECK-GI-NEXT: mov v1.s[2], v0.s[0]
-; CHECK-GI-NEXT: mov v1.s[3], v0.s[0]
; CHECK-GI-NEXT: mov v0.16b, v1.16b
; CHECK-GI-NEXT: ret
entry:
@@ -254,7 +253,6 @@ define <3 x float> @insert_v3f32_2(<3 x float> %a, float %b, i32 %c) {
; CHECK-GI-NEXT: // kill: def $s1 killed $s1 def $q1
; CHECK-GI-NEXT: mov v0.s[1], v2.s[0]
; CHECK-GI-NEXT: mov v0.s[2], v1.s[0]
-; CHECK-GI-NEXT: mov v0.s[3], v0.s[0]
; CHECK-GI-NEXT: ret
entry:
%d = insertelement <3 x float> %a, float %b, i32 2
@@ -766,7 +764,6 @@ define <3 x i32> @insert_v3i32_0(<3 x i32> %a, i32 %b, i32 %c) {
; CHECK-GI-NEXT: mov v0.s[1], w8
; CHECK-GI-NEXT: fmov w8, s2
; CHECK-GI-NEXT: mov v0.s[2], w8
-; CHECK-GI-NEXT: mov v0.s[3], w8
; CHECK-GI-NEXT: ret
entry:
%d = insertelement <3 x i32> %a, i32 %b, i32 0
@@ -785,7 +782,6 @@ define <3 x i32> @insert_v3i32_2(<3 x i32> %a, i32 %b, i32 %c) {
; CHECK-GI-NEXT: mov v0.s[1], v1.s[0]
; CHECK-GI-NEXT: fmov s1, w0
; CHECK-GI-NEXT: mov v0.s[2], v1.s[0]
-; CHECK-GI-NEXT: mov v0.s[3], v0.s[0]
; CHECK-GI-NEXT: ret
entry:
%d = insertelement <3 x i32> %a, i32 %b, i32 2
diff --git a/llvm/test/CodeGen/AArch64/itofp.ll b/llvm/test/CodeGen/AArch64/itofp.ll
index 708bb43887f866..2164c2aad20111 100644
--- a/llvm/test/CodeGen/AArch64/itofp.ll
+++ b/llvm/test/CodeGen/AArch64/itofp.ll
@@ -2605,7 +2605,6 @@ define <3 x float> @stofp_v3i64_v3f32(<3 x i64> %a) {
; CHECK-GI-NEXT: mov s2, v0.s[1]
; CHECK-GI-NEXT: mov v0.s[1], v2.s[0]
; CHECK-GI-NEXT: mov v0.s[2], v1.s[0]
-; CHECK-GI-NEXT: mov v0.s[3], v0.s[0]
; CHECK-GI-NEXT: ret
entry:
%c = sitofp <3 x i64> %a to <3 x float>
@@ -2638,7 +2637,6 @@ define <3 x float> @utofp_v3i64_v3f32(<3 x i64> %a) {
; CHECK-GI-NEXT: mov s2, v0.s[1]
; CHECK-GI-NEXT: mov v0.s[1], v2.s[0]
; CHECK-GI-NEXT: mov v0.s[2], v1.s[0]
-; CHECK-GI-NEXT: mov v0.s[3], v0.s[0]
; CHECK-GI-NEXT: ret
entry:
%c = uitofp <3 x i64> %a to <3 x float>
@@ -3754,13 +3752,9 @@ define <2 x half> @stofp_v2i64_v2f16(<2 x i64> %a) {
; CHECK-GI-NOFP16-NEXT: fcvtn v0.2s, v0.2d
; CHECK-GI-NOFP16-NEXT: mov s1, v0.s[1]
; CHECK-GI-NOFP16-NEXT: mov v0.s[1], v1.s[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.s[2], v0.s[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.s[3], v0.s[0]
; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v0.4s
; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[1]
; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[2], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[3], v0.h[0]
; CHECK-GI-NOFP16-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NOFP16-NEXT: ret
;
@@ -3771,8 +3765,6 @@ define <2 x half> @stofp_v2i64_v2f16(<2 x i64> %a) {
; CHECK-GI-FP16-NEXT: fcvt h0, d0
; CHECK-GI-FP16-NEXT: fcvt h1, d1
; CHECK-GI-FP16-NEXT: mov v0.h[1], v1.h[0]
-; CHECK-GI-FP16-NEXT: mov v0.h[2], v0.h[0]
-; CHECK-GI-FP16-NEXT: mov v0.h[3], v0.h[0]
; CHECK-GI-FP16-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-FP16-NEXT: ret
entry:
@@ -3809,13 +3801,9 @@ define <2 x half> @utofp_v2i64_v2f16(<2 x i64> %a) {
; CHECK-GI-NOFP16-NEXT: fcvtn v0.2s, v0.2d
; CHECK-GI-NOFP16-NEXT: mov s1, v0.s[1]
; CHECK-GI-NOFP16-NEXT: mov v0.s[1], v1.s[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.s[2], v0.s[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.s[3], v0.s[0]
; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v0.4s
; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[1]
; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[2], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[3], v0.h[0]
; CHECK-GI-NOFP16-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NOFP16-NEXT: ret
;
@@ -3826,8 +3814,6 @@ define <2 x half> @utofp_v2i64_v2f16(<2 x i64> %a) {
; CHECK-GI-FP16-NEXT: fcvt h0, d0
; CHECK-GI-FP16-NEXT: fcvt h1, d1
; CHECK-GI-FP16-NEXT: mov v0.h[1], v1.h[0]
-; CHECK-GI-FP16-NEXT: mov v0.h[2], v0.h[0]
-; CHECK-GI-FP16-NEXT: mov v0.h[3], v0.h[0]
; CHECK-GI-FP16-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-FP16-NEXT: ret
entry:
@@ -3876,7 +3862,6 @@ define <3 x half> @stofp_v3i64_v3f16(<3 x i64> %a) {
; CHECK-GI-FP16-NEXT: fcvt h1, d1
; CHECK-GI-FP16-NEXT: mov v0.h[1], v1.h[0]
; CHECK-GI-FP16-NEXT: mov v0.h[2], v2.h[0]
-; CHECK-GI-FP16-NEXT: mov v0.h[3], v0.h[0]
; CHECK-GI-FP16-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-FP16-NEXT: ret
entry:
@@ -3925,7 +3910,6 @@ define <3 x half> @utofp_v3i64_v3f16(<3 x i64> %a) {
; CHECK-GI-FP16-NEXT: fcvt h1, d1
; CHECK-GI-FP16-NEXT: mov v0.h[1], v1.h[0]
; CHECK-GI-FP16-NEXT: mov v0.h[2], v2.h[0]
-; CHECK-GI-FP16-NEXT: mov v0.h[3], v0.h[0]
; CHECK-GI-FP16-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-FP16-NEXT: ret
entry:
@@ -4756,13 +4740,9 @@ define <2 x half> @stofp_v2i32_v2f16(<2 x i32> %a) {
; CHECK-GI-NEXT: scvtf v0.2s, v0.2s
; CHECK-GI-NEXT: mov s1, v0.s[1]
; CHECK-GI-NEXT: mov v0.s[1], v1.s[0]
-; CHECK-GI-NEXT: mov v0.s[2], v0.s[0]
-; CHECK-GI-NEXT: mov v0.s[3], v0.s[0]
; CHECK-GI-NEXT: fcvtn v0.4h, v0.4s
; CHECK-GI-NEXT: mov h1, v0.h[1]
; CHECK-GI-NEXT: mov v0.h[1], v1.h[0]
-; CHECK-GI-NEXT: mov v0.h[2], v0.h[0]
-; CHECK-GI-NEXT: mov v0.h[3], v0.h[0]
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
entry:
@@ -4783,13 +4763,9 @@ define <2 x half> @utofp_v2i32_v2f16(<2 x i32> %a) {
; CHECK-GI-NEXT: ucvtf v0.2s, v0.2s
; CHECK-GI-NEXT: mov s1, v0.s[1]
; CHECK-GI-NEXT: mov v0.s[1], v1.s[0]
-; CHECK-GI-NEXT: mov v0.s[2], v0.s[0]
-; CHECK-GI-NEXT: mov v0.s[3], v0.s[0]
; CHECK-GI-NEXT: fcvtn v0.4h, v0.4s
; CHECK-GI-NEXT: mov h1, v0.h[1]
; CHECK-GI-NEXT: mov v0.h[1], v1.h[0]
-; CHECK-GI-NEXT: mov v0.h[2], v0.h[0]
-; CHECK-GI-NEXT: mov v0.h[3], v0.h[0]
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
entry:
@@ -4997,13 +4973,9 @@ define <2 x half> @stofp_v2i16_v2f16(<2 x i16> %a) {
; CHECK-GI-NOFP16-NEXT: scvtf v0.2s, v0.2s
; CHECK-GI-NOFP16-NEXT: mov s1, v0.s[1]
; CHECK-GI-NOFP16-NEXT: mov v0.s[1], v1.s[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.s[2], v0.s[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.s[3], v0.s[0]
; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v0.4s
; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[1]
; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[2], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[3], v0.h[0]
; CHECK-GI-NOFP16-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NOFP16-NEXT: ret
;
@@ -5012,13 +4984,9 @@ define <2 x half> @stofp_v2i16_v2f16(<2 x i16> %a) {
; CHECK-GI-FP16-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-GI-FP16-NEXT: mov s1, v0.s[1]
; CHECK-GI-FP16-NEXT: mov v0.h[1], v1.h[0]
-; CHECK-GI-FP16-NEXT: mov v0.h[2], v0.h[0]
-; CHECK-GI-FP16-NEXT: mov v0.h[3], v0.h[0]
; CHECK-GI-FP16-NEXT: scvtf v0.4h, v0.4h
; CHECK-GI-FP16-NEXT: mov h1, v0.h[1]
; CHECK-GI-FP16-NEXT: mov v0.h[1], v1.h[0]
-; CHECK-GI-FP16-NEXT: mov v0.h[2], v0.h[0]
-; CHECK-GI-FP16-NEXT: mov v0.h[3], v0.h[0]
; CHECK-GI-FP16-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-FP16-NEXT: ret
entry:
@@ -5048,13 +5016,9 @@ define <2 x half> @utofp_v2i16_v2f16(<2 x i16> %a) {
; CHECK-GI-NOFP16-NEXT: ucvtf v0.2s, v0.2s
; CHECK-GI-NOFP16-NEXT: mov s1, v0.s[1]
; CHECK-GI-NOFP16-NEXT: mov v0.s[1], v1.s[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.s[2], v0.s[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.s[3], v0.s[0]
; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v0.4s
; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[1]
; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[2], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[3], v0.h[0]
; CHECK-GI-NOFP16-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NOFP16-NEXT: ret
;
@@ -5063,13 +5027,9 @@ define <2 x half> @utofp_v2i16_v2f16(<2 x i16> %a) {
; CHECK-GI-FP16-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-GI-FP16-NEXT: mov s1, v0.s[1]
; CHECK-GI-FP16-NEXT: mov v0.h[1], v1.h[0]
-; CHECK-GI-FP16-NEXT: mov v0.h[2], v0.h[0]
-; CHECK-GI-FP16-NEXT: mov v0.h[3], v0.h[0]
; CHECK-GI-FP16-NEXT: ucvtf v0.4h, v0.4h
; CHECK-GI-FP16-NEXT: mov h1, v0.h[1]
; CHECK-GI-FP16-NEXT: mov v0.h[1], v1.h[0]
-; CHECK-GI-FP16-NEXT: mov v0.h[2], v0.h[0]
-; CHECK-GI-FP16-NEXT: mov v0.h[3], v0.h[0]
; CHECK-GI-FP16-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-FP16-NEXT: ret
entry:
@@ -5551,13 +5511,9 @@ define <2 x half> @stofp_v2i8_v2f16(<2 x i8> %a) {
; CHECK-GI-NOFP16-NEXT: scvtf v0.2s, v0.2s
; CHECK-GI-NOFP16-NEXT: mov s1, v0.s[1]
; CHECK-GI-NOFP16-NEXT: mov v0.s[1], v1.s[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.s[2], v0.s[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.s[3], v0.s[0]
; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v0.4s
; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[1]
; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[2], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[3], v0.h[0]
; CHECK-GI-NOFP16-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NOFP16-NEXT: ret
;
@@ -5566,19 +5522,13 @@ define <2 x half> @stofp_v2i8_v2f16(<2 x i8> %a) {
; CHECK-GI-FP16-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-GI-FP16-NEXT: mov s1, v0.s[1]
; CHECK-GI-FP16-NEXT: mov v0.h[1], v1.h[0]
-; CHECK-GI-FP16-NEXT: mov v0.h[2], v0.h[0]
-; CHECK-GI-FP16-NEXT: mov v0.h[3], v0.h[0]
; CHECK-GI-FP16-NEXT: shl v0.4h, v0.4h, #8
; CHECK-GI-FP16-NEXT: sshr v0.4h, v0.4h, #8
; CHECK-GI-FP16-NEXT: mov h1, v0.h[1]
; CHECK-GI-FP16-NEXT: mov v0.h[1], v1.h[0]
-; CHECK-GI-FP16-NEXT: mov v0.h[2], v0.h[0]
-; CHECK-GI-FP16-NEXT: mov v0.h[3], v0.h[0]
; CHECK-GI-FP16-NEXT: scvtf v0.4h, v0.4h
; CHECK-GI-FP16-NEXT: mov h1, v0.h[1]
; CHECK-GI-FP16-NEXT: mov v0.h[1], v1.h[0]
-; CHECK-GI-FP16-NEXT: mov v0.h[2], v0.h[0]
-; CHECK-GI-FP16-NEXT: mov v0.h[3], v0.h[0]
; CHECK-GI-FP16-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-FP16-NEXT: ret
entry:
@@ -5622,13 +5572,9 @@ define <2 x half> @utofp_v2i8_v2f16(<2 x i8> %a) {
; CHECK-GI-NOFP16-NEXT: ucvtf v0.2s, v0.2s
; CHECK-GI-NOFP16-NEXT: mov s1, v0.s[1]
; CHECK-GI-NOFP16-NEXT: mov v0.s[1], v1.s[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.s[2], v0.s[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.s[3], v0.s[0]
; CHECK-GI-NOFP16-NEXT: fcvtn v0.4h, v0.4s
; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[1]
; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v1.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[2], v0.h[0]
-; CHECK-GI-NOFP16-NEXT: mov v0.h[3], v0.h[0]
; CHECK-GI-NOFP16-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NOFP16-NEXT: ret
;
@@ -5638,13 +5584,9 @@ define <2 x half> @utofp_v2i8_v2f16(<2 x i8> %a) {
; CHECK-GI-FP16-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-GI-FP16-NEXT: mov s1, v0.s[1]
; CHECK-GI-FP16-NEXT: mov v0.h[1], v1.h[0]
-; CHECK-GI-FP16-NEXT: mov v0.h[2], v0.h[0]
-; CHECK-GI-FP16-NEXT: mov v0.h[3], v0.h[0]
; CHECK-GI-FP16-NEXT: ucvtf v0.4h, v0.4h
; CHECK-GI-FP16-NEXT: mov h1, v0.h[1]
; CHECK-GI-FP16-NEXT: mov v0.h[1], v1.h[0]
-; CHECK-GI-FP16-NEXT: mov v0.h[2], v0.h[0]
-; CHECK-GI-FP16-NEXT: mov v0.h[3], v0.h[0]
; CHECK-GI-FP16-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-FP16-NEXT: ret
entry:
@@ -5694,7 +5636,6 @@ define <3 x half> @stofp_v3i8_v3f16(<3 x i8> %a) {
; CHECK-GI-FP16-NEXT: mov v0.h[1], v1.h[0]
; CHECK-GI-FP16-NEXT: fmov s1, w2
; CHECK-GI-FP16-NEXT: mov v0.h[2], v1.h[0]
-; CHECK-GI-FP16-NEXT: mov v0.h[3], v0.h[0]
; CHECK-GI-FP16-NEXT: shl v0.4h, v0.4h, #8
; CHECK-GI-FP16-NEXT: sshr v0.4h, v0.4h, #8
; CHECK-GI-FP16-NEXT: scvtf v0.4h, v0.4h
@@ -5744,7 +5685,6 @@ define <3 x half> @utofp_v3i8_v3f16(<3 x i8> %a) {
; CHECK-GI-FP16-NEXT: fmov s1, w2
; CHECK-GI-FP16-NEXT: mov v0.h[2], v1.h[0]
; CHECK-GI-FP16-NEXT: movi d1, #0xff00ff00ff00ff
-; CHECK-GI-FP16-NEXT: mov v0.h[3], v0.h[0]
; CHECK-GI-FP16-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-GI-FP16-NEXT: ucvtf v0.4h, v0.4h
; CHECK-GI-FP16-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/llvm.exp10.ll b/llvm/test/CodeGen/AArch64/llvm.exp10.ll
index 70df88ba9f8985..56f4272c4363c8 100644
--- a/llvm/test/CodeGen/AArch64/llvm.exp10.ll
+++ b/llvm/test/CodeGen/AArch64/llvm.exp10.ll
@@ -109,14 +109,11 @@ define <2 x half> @exp10_v2f16(<2 x half> %x) {
; GISEL-NEXT: str q0, [sp] // 16-byte Folded Spill
; GISEL-NEXT: fmov s0, s1
; GISEL-NEXT: bl exp10f
-; GISEL-NEXT: fcvt h0, s0
-; GISEL-NEXT: ldr q1, [sp] // 16-byte Folded Reload
+; GISEL-NEXT: fcvt h1, s0
+; GISEL-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; GISEL-NEXT: ldr x30, [sp, #24] // 8-byte Folded Reload
; GISEL-NEXT: ldr d8, [sp, #16] // 8-byte Folded Reload
-; GISEL-NEXT: mov v1.h[1], v0.h[0]
-; GISEL-NEXT: mov v1.h[2], v0.h[0]
-; GISEL-NEXT: mov v1.h[3], v0.h[0]
-; GISEL-NEXT: mov v0.16b, v1.16b
+; GISEL-NEXT: mov v0.h[1], v1.h[0]
; GISEL-NEXT: // kill: def $d0 killed $d0 killed $q0
; GISEL-NEXT: add sp, sp, #32
; GISEL-NEXT: ret
@@ -196,7 +193,6 @@ define <3 x half> @exp10_v3f16(<3 x half> %x) {
; GISEL-NEXT: ldr x30, [sp, #48] // 8-byte Folded Reload
; GISEL-NEXT: mov v1.h[1], v2.h[0]
; GISEL-NEXT: mov v1.h[2], v0.h[0]
-; GISEL-NEXT: mov v1.h[3], v0.h[0]
; GISEL-NEXT: mov v0.16b, v1.16b
; GISEL-NEXT: // kill: def $d0 killed $d0 killed $q0
; GISEL-NEXT: add sp, sp, #64
@@ -440,7 +436,6 @@ define <3 x float> @exp10_v3f32(<3 x float> %x) {
; GISEL-NEXT: ldp d9, d8, [sp, #32] // 16-byte Folded Reload
; GISEL-NEXT: mov v1.s[1], v2.s[0]
; GISEL-NEXT: mov v1.s[2], v0.s[0]
-; GISEL-NEXT: mov v1.s[3], v0.s[0]
; GISEL-NEXT: mov v0.16b, v1.16b
; GISEL-NEXT: add sp, sp, #64
; GISEL-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/load.ll b/llvm/test/CodeGen/AArch64/load.ll
index 7f4540d915ab37..39143e5c53ffd1 100644
--- a/llvm/test/CodeGen/AArch64/load.ll
+++ b/llvm/test/CodeGen/AArch64/load.ll
@@ -245,7 +245,6 @@ define <7 x i8> @load_v7i8(ptr %ptr){
; CHECK-GI-NEXT: mov v0.b[5], v1.b[0]
; CHECK-GI-NEXT: ldr b1, [x0, #6]
; CHECK-GI-NEXT: mov v0.b[6], v1.b[0]
-; CHECK-GI-NEXT: mov v0.b[7], v0.b[0]
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
%a = load <7 x i8>, ptr %ptr
@@ -265,7 +264,6 @@ define <3 x i16> @load_v3i16(ptr %ptr){
; CHECK-GI-NEXT: mov v0.h[1], v1.h[0]
; CHECK-GI-NEXT: ldr h1, [x0, #4]
; CHECK-GI-NEXT: mov v0.h[2], v1.h[0]
-; CHECK-GI-NEXT: mov v0.h[3], v0.h[0]
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
%a = load <3 x i16>, ptr %ptr
@@ -293,7 +291,6 @@ define <7 x i16> @load_v7i16(ptr %ptr){
; CHECK-GI-NEXT: mov v0.h[5], v1.h[0]
; CHECK-GI-NEXT: ldr h1, [x0, #12]
; CHECK-GI-NEXT: mov v0.h[6], v1.h[0]
-; CHECK-GI-NEXT: mov v0.h[7], v0.h[0]
; CHECK-GI-NEXT: ret
%a = load <7 x i16>, ptr %ptr
ret <7 x i16> %a
@@ -311,7 +308,6 @@ define <3 x i32> @load_v3i32(ptr %ptr){
; CHECK-GI-NEXT: mov v0.s[1], v1.s[0]
; CHECK-GI-NEXT: ldr s1, [x0, #8]
; CHECK-GI-NEXT: mov v0.s[2], v1.s[0]
-; CHECK-GI-NEXT: mov v0.s[3], v0.s[0]
; CHECK-GI-NEXT: ret
%a = load <3 x i32>, ptr %ptr
ret <3 x i32> %a
diff --git a/llvm/test/CodeGen/AArch64/sext.ll b/llvm/test/CodeGen/AArch64/sext.ll
index f319721e0f2f0f..61f04fbf0484f7 100644
--- a/llvm/test/CodeGen/AArch64/sext.ll
+++ b/llvm/test/CodeGen/AArch64/sext.ll
@@ -222,7 +222,6 @@ define <3 x i16> @sext_v3i8_v3i16(<3 x i8> %a) {
; CHECK-GI-NEXT: fmov s0, w0
; CHECK-GI-NEXT: mov v0.s[1], w1
; CHECK-GI-NEXT: mov v0.s[2], w2
-; CHECK-GI-NEXT: mov v0.s[3], w8
; CHECK-GI-NEXT: xtn v0.4h, v0.4s
; CHECK-GI-NEXT: shl v0.4h, v0.4h, #8
; CHECK-GI-NEXT: sshr v0.4h, v0.4h, #8
@@ -252,8 +251,6 @@ define <3 x i32> @sext_v3i8_v3i32(<3 x i8> %a) {
; CHECK-GI-NEXT: mov v0.s[1], w8
; CHECK-GI-NEXT: mov v1.s[2], w2
; CHECK-GI-NEXT: mov v0.s[2], w8
-; CHECK-GI-NEXT: mov v1.s[3], w8
-; CHECK-GI-NEXT: mov v0.s[3], w8
; CHECK-GI-NEXT: neg v2.4s, v0.4s
; CHECK-GI-NEXT: ushl v0.4s, v1.4s, v0.4s
; CHECK-GI-NEXT: sshl v0.4s, v0.4s, v2.4s
@@ -315,7 +312,6 @@ define <3 x i32> @sext_v3i16_v3i32(<3 x i16> %a) {
; CHECK-GI-NEXT: smov w8, v0.h[2]
; CHECK-GI-NEXT: mov v1.s[1], w9
; CHECK-GI-NEXT: mov v1.s[2], w8
-; CHECK-GI-NEXT: mov v1.s[3], w8
; CHECK-GI-NEXT: mov v0.16b, v1.16b
; CHECK-GI-NEXT: ret
entry:
@@ -390,7 +386,6 @@ define <3 x i16> @sext_v3i10_v3i16(<3 x i10> %a) {
; CHECK-GI-NEXT: fmov s0, w0
; CHECK-GI-NEXT: mov v0.s[1], w1
; CHECK-GI-NEXT: mov v0.s[2], w2
-; CHECK-GI-NEXT: mov v0.s[3], w8
; CHECK-GI-NEXT: xtn v0.4h, v0.4s
; CHECK-GI-NEXT: shl v0.4h, v0.4h, #6
; CHECK-GI-NEXT: sshr v0.4h, v0.4h, #6
@@ -420,8 +415,6 @@ define <3 x i32> @sext_v3i10_v3i32(<3 x i10> %a) {
; CHECK-GI-NEXT: mov v0.s[1], w8
; CHECK-GI-NEXT: mov v1.s[2], w2
; CHECK-GI-NEXT: mov v0.s[2], w8
-; CHECK-GI-NEXT: mov v1.s[3], w8
-; CHECK-GI-NEXT: mov v0.s[3], w8
; CHECK-GI-NEXT: neg v2.4s, v0.4s
; CHECK-GI-NEXT: ushl v0.4s, v1.4s, v0.4s
; CHECK-GI-NEXT: sshl v0.4s, v0.4s, v2.4s
diff --git a/llvm/test/CodeGen/AArch64/shift.ll b/llvm/test/CodeGen/AArch64/shift.ll
index ccc06f2e1058d5..5287839ee7b705 100644
--- a/llvm/test/CodeGen/AArch64/shift.ll
+++ b/llvm/test/CodeGen/AArch64/shift.ll
@@ -594,7 +594,6 @@ define <1 x i32> @shl_v1i32(<1 x i32> %0, <1 x i32> %1){
; CHECK-GI-NEXT: fmov w9, s1
; CHECK-GI-NEXT: lsl w8, w8, w9
; CHECK-GI-NEXT: fmov s0, w8
-; CHECK-GI-NEXT: mov v0.s[1], w8
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
%3 = shl <1 x i32> %0, %1
@@ -697,7 +696,6 @@ define <1 x i32> @ashr_v1i32(<1 x i32> %0, <1 x i32> %1){
; CHECK-GI-NEXT: fmov w9, s1
; CHECK-GI-NEXT: asr w8, w8, w9
; CHECK-GI-NEXT: fmov s0, w8
-; CHECK-GI-NEXT: mov v0.s[1], w8
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
%3 = ashr <1 x i32> %0, %1
@@ -790,7 +788,6 @@ define <1 x i32> @lshr_v1i32(<1 x i32> %0, <1 x i32> %1){
; CHECK-GI-NEXT: fmov w9, s1
; CHECK-GI-NEXT: lsr w8, w8, w9
; CHECK-GI-NEXT: fmov s0, w8
-; CHECK-GI-NEXT: mov v0.s[1], w8
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
%3 = lshr <1 x i32> %0, %1
@@ -851,16 +848,6 @@ define <3 x i8> @shl_v3i8(<3 x i8> %0, <3 x i8> %1){
; CHECK-GI-NEXT: fmov s3, w5
; CHECK-GI-NEXT: mov v0.b[2], v1.b[0]
; CHECK-GI-NEXT: mov v2.b[2], v3.b[0]
-; CHECK-GI-NEXT: mov v0.b[3], v0.b[0]
-; CHECK-GI-NEXT: mov v2.b[3], v0.b[0]
-; CHECK-GI-NEXT: mov v0.b[4], v0.b[0]
-; CHECK-GI-NEXT: mov v2.b[4], v0.b[0]
-; CHECK-GI-NEXT: mov v0.b[5], v0.b[0]
-; CHECK-GI-NEXT: mov v2.b[5], v0.b[0]
-; CHECK-GI-NEXT: mov v0.b[6], v0.b[0]
-; CHECK-GI-NEXT: mov v2.b[6], v0.b[0]
-; CHECK-GI-NEXT: mov v0.b[7], v0.b[0]
-; CHECK-GI-NEXT: mov v2.b[7], v0.b[0]
; CHECK-GI-NEXT: ushl v0.8b, v0.8b, v2.8b
; CHECK-GI-NEXT: umov w0, v0.b[0]
; CHECK-GI-NEXT: umov w1, v0.b[1]
@@ -937,16 +924,6 @@ define <3 x i8> @ashr_v3i8(<3 x i8> %0, <3 x i8> %1){
; CHECK-GI-NEXT: mov v0.b[2], v2.b[0]
; CHECK-GI-NEXT: fmov s2, w2
; CHECK-GI-NEXT: mov v1.b[2], v2.b[0]
-; CHECK-GI-NEXT: mov v0.b[3], v0.b[0]
-; CHECK-GI-NEXT: mov v1.b[3], v0.b[0]
-; CHECK-GI-NEXT: mov v0.b[4], v0.b[0]
-; CHECK-GI-NEXT: mov v1.b[4], v0.b[0]
-; CHECK-GI-NEXT: mov v0.b[5], v0.b[0]
-; CHECK-GI-NEXT: mov v1.b[5], v0.b[0]
-; CHECK-GI-NEXT: mov v0.b[6], v0.b[0]
-; CHECK-GI-NEXT: mov v1.b[6], v0.b[0]
-; CHECK-GI-NEXT: mov v0.b[7], v0.b[0]
-; CHECK-GI-NEXT: mov v1.b[7], v0.b[0]
; CHECK-GI-NEXT: neg v0.8b, v0.8b
; CHECK-GI-NEXT: sshl v0.8b, v1.8b, v0.8b
; CHECK-GI-NEXT: umov w0, v0.b[0]
@@ -1027,16 +1004,6 @@ define <3 x i8> @lshr_v3i8(<3 x i8> %0, <3 x i8> %1){
; CHECK-GI-NEXT: mov v0.b[2], v2.b[0]
; CHECK-GI-NEXT: fmov s2, w2
; CHECK-GI-NEXT: mov v1.b[2], v2.b[0]
-; CHECK-GI-NEXT: mov v0.b[3], v0.b[0]
-; CHECK-GI-NEXT: mov v1.b[3], v0.b[0]
-; CHECK-GI-NEXT: mov v0.b[4], v0.b[0]
-; CHECK-GI-NEXT: mov v1.b[4], v0.b[0]
-; CHECK-GI-NEXT: mov v0.b[5], v0.b[0]
-; CHECK-GI-NEXT: mov v1.b[5], v0.b[0]
-; CHECK-GI-NEXT: mov v0.b[6], v0.b[0]
-; CHECK-GI-NEXT: mov v1.b[6], v0.b[0]
-; CHECK-GI-NEXT: mov v0.b[7], v0.b[0]
-; CHECK-GI-NEXT: mov v1.b[7], v0.b[0]
; CHECK-GI-NEXT: neg v0.8b, v0.8b
; CHECK-GI-NEXT: ushl v0.8b, v1.8b, v0.8b
; CHECK-GI-NEXT: umov w0, v0.b[0]
diff --git a/llvm/test/CodeGen/AArch64/shufflevector.ll b/llvm/test/CodeGen/AArch64/shufflevector.ll
index b408bc1c389767..d79f3ae11167f3 100644
--- a/llvm/test/CodeGen/AArch64/shufflevector.ll
+++ b/llvm/test/CodeGen/AArch64/shufflevector.ll
@@ -210,8 +210,8 @@ define i32 @shufflevector_v4i8(<4 x i8> %a, <4 x i8> %b){
; CHECK-GI-LABEL: shufflevector_v4i8:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: mov h2, v0.h[1]
; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-GI-NEXT: mov h2, v0.h[1]
; CHECK-GI-NEXT: mov h3, v1.h[1]
; CHECK-GI-NEXT: adrp x8, .LCPI15_0
; CHECK-GI-NEXT: mov h4, v0.h[2]
@@ -224,14 +224,6 @@ define i32 @shufflevector_v4i8(<4 x i8> %a, <4 x i8> %b){
; CHECK-GI-NEXT: mov v1.b[2], v2.b[0]
; CHECK-GI-NEXT: mov v0.b[3], v5.b[0]
; CHECK-GI-NEXT: mov v1.b[3], v6.b[0]
-; CHECK-GI-NEXT: mov v0.b[4], v0.b[0]
-; CHECK-GI-NEXT: mov v1.b[4], v0.b[0]
-; CHECK-GI-NEXT: mov v0.b[5], v0.b[0]
-; CHECK-GI-NEXT: mov v1.b[5], v0.b[0]
-; CHECK-GI-NEXT: mov v0.b[6], v0.b[0]
-; CHECK-GI-NEXT: mov v1.b[6], v0.b[0]
-; CHECK-GI-NEXT: mov v0.b[7], v0.b[0]
-; CHECK-GI-NEXT: mov v1.b[7], v0.b[0]
; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI15_0]
; CHECK-GI-NEXT: tbl v0.16b, { v0.16b }, v1.16b
@@ -287,16 +279,12 @@ define i32 @shufflevector_v2i16(<2 x i16> %a, <2 x i16> %b){
; CHECK-GI-LABEL: shufflevector_v2i16:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: mov s2, v0.s[1]
; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-GI-NEXT: mov s2, v0.s[1]
; CHECK-GI-NEXT: mov s3, v1.s[1]
; CHECK-GI-NEXT: adrp x8, .LCPI17_0
; CHECK-GI-NEXT: mov v0.h[1], v2.h[0]
; CHECK-GI-NEXT: mov v1.h[1], v3.h[0]
-; CHECK-GI-NEXT: mov v0.h[2], v0.h[0]
-; CHECK-GI-NEXT: mov v1.h[2], v0.h[0]
-; CHECK-GI-NEXT: mov v0.h[3], v0.h[0]
-; CHECK-GI-NEXT: mov v1.h[3], v0.h[0]
; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI17_0]
; CHECK-GI-NEXT: tbl v0.16b, { v0.16b }, v1.16b
@@ -516,16 +504,6 @@ define <3 x i8> @shufflevector_v3i8(<3 x i8> %a, <3 x i8> %b) {
; CHECK-GI-NEXT: mov v0.b[2], v1.b[0]
; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI30_0]
; CHECK-GI-NEXT: mov v2.b[2], v3.b[0]
-; CHECK-GI-NEXT: mov v0.b[3], v0.b[0]
-; CHECK-GI-NEXT: mov v2.b[3], v0.b[0]
-; CHECK-GI-NEXT: mov v0.b[4], v0.b[0]
-; CHECK-GI-NEXT: mov v2.b[4], v0.b[0]
-; CHECK-GI-NEXT: mov v0.b[5], v0.b[0]
-; CHECK-GI-NEXT: mov v2.b[5], v0.b[0]
-; CHECK-GI-NEXT: mov v0.b[6], v0.b[0]
-; CHECK-GI-NEXT: mov v2.b[6], v0.b[0]
-; CHECK-GI-NEXT: mov v0.b[7], v0.b[0]
-; CHECK-GI-NEXT: mov v2.b[7], v0.b[0]
; CHECK-GI-NEXT: mov v0.d[1], v2.d[0]
; CHECK-GI-NEXT: tbl v0.16b, { v0.16b }, v1.16b
; CHECK-GI-NEXT: mov b1, v0.b[1]
diff --git a/llvm/test/CodeGen/AArch64/xtn.ll b/llvm/test/CodeGen/AArch64/xtn.ll
index 21982fadbe8036..3c86f4bf9eb213 100644
--- a/llvm/test/CodeGen/AArch64/xtn.ll
+++ b/llvm/test/CodeGen/AArch64/xtn.ll
@@ -298,7 +298,6 @@ define <3 x i16> @xtn_v3i32_v3i16(<3 x i32> %a) {
; CHECK-GI-NEXT: mov s2, v0.s[2]
; CHECK-GI-NEXT: mov v0.h[1], v1.h[0]
; CHECK-GI-NEXT: mov v0.h[2], v2.h[0]
-; CHECK-GI-NEXT: mov v0.h[3], v0.h[0]
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
entry:
@@ -327,7 +326,6 @@ define <3 x i16> @xtn_v3i64_v3i16(<3 x i64> %a) {
; CHECK-GI-NEXT: mov v0.h[1], v1.h[0]
; CHECK-GI-NEXT: fmov s1, w8
; CHECK-GI-NEXT: mov v0.h[2], v1.h[0]
-; CHECK-GI-NEXT: mov v0.h[3], v0.h[0]
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
entry:
@@ -353,7 +351,6 @@ define <3 x i32> @xtn_v3i64_v3i32(<3 x i64> %a) {
; CHECK-GI-NEXT: fmov x8, d2
; CHECK-GI-NEXT: mov v0.s[1], w9
; CHECK-GI-NEXT: mov v0.s[2], w8
-; CHECK-GI-NEXT: mov v0.s[3], w8
; CHECK-GI-NEXT: ret
entry:
%arg1 = trunc <3 x i64> %a to <3 x i32>
diff --git a/llvm/test/CodeGen/AArch64/zext.ll b/llvm/test/CodeGen/AArch64/zext.ll
index e513340f5b18ad..54b29be2132cdd 100644
--- a/llvm/test/CodeGen/AArch64/zext.ll
+++ b/llvm/test/CodeGen/AArch64/zext.ll
@@ -249,10 +249,8 @@ define <3 x i16> @zext_v3i8_v3i16(<3 x i8> %a) {
; CHECK-GI-NEXT: mov v2.16b, v1.16b
; CHECK-GI-NEXT: mov v0.s[2], w2
; CHECK-GI-NEXT: mov v2.h[1], v1.h[0]
-; CHECK-GI-NEXT: mov v0.s[3], w8
-; CHECK-GI-NEXT: mov v2.h[2], v1.h[0]
; CHECK-GI-NEXT: xtn v0.4h, v0.4s
-; CHECK-GI-NEXT: mov v2.h[3], v0.h[0]
+; CHECK-GI-NEXT: mov v2.h[2], v1.h[0]
; CHECK-GI-NEXT: and v0.8b, v0.8b, v2.8b
; CHECK-GI-NEXT: ret
entry:
@@ -280,8 +278,6 @@ define <3 x i32> @zext_v3i8_v3i32(<3 x i8> %a) {
; CHECK-GI-NEXT: mov v1.s[1], w8
; CHECK-GI-NEXT: mov v0.s[2], w2
; CHECK-GI-NEXT: mov v1.s[2], w8
-; CHECK-GI-NEXT: mov v0.s[3], w8
-; CHECK-GI-NEXT: mov v1.s[3], w8
; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-GI-NEXT: ret
entry:
@@ -341,7 +337,6 @@ define <3 x i32> @zext_v3i16_v3i32(<3 x i16> %a) {
; CHECK-GI-NEXT: umov w8, v0.h[2]
; CHECK-GI-NEXT: mov v1.s[1], w9
; CHECK-GI-NEXT: mov v1.s[2], w8
-; CHECK-GI-NEXT: mov v1.s[3], w8
; CHECK-GI-NEXT: mov v0.16b, v1.16b
; CHECK-GI-NEXT: ret
entry:
@@ -420,10 +415,8 @@ define <3 x i16> @zext_v3i10_v3i16(<3 x i10> %a) {
; CHECK-GI-NEXT: mov v2.16b, v1.16b
; CHECK-GI-NEXT: mov v0.s[2], w2
; CHECK-GI-NEXT: mov v2.h[1], v1.h[0]
-; CHECK-GI-NEXT: mov v0.s[3], w8
-; CHECK-GI-NEXT: mov v2.h[2], v1.h[0]
; CHECK-GI-NEXT: xtn v0.4h, v0.4s
-; CHECK-GI-NEXT: mov v2.h[3], v0.h[0]
+; CHECK-GI-NEXT: mov v2.h[2], v1.h[0]
; CHECK-GI-NEXT: and v0.8b, v0.8b, v2.8b
; CHECK-GI-NEXT: ret
entry:
@@ -451,8 +444,6 @@ define <3 x i32> @zext_v3i10_v3i32(<3 x i10> %a) {
; CHECK-GI-NEXT: mov v1.s[1], w8
; CHECK-GI-NEXT: mov v0.s[2], w2
; CHECK-GI-NEXT: mov v1.s[2], w8
-; CHECK-GI-NEXT: mov v0.s[3], w8
-; CHECK-GI-NEXT: mov v1.s[3], w8
; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-GI-NEXT: ret
entry:
>From de50c22faf96413fed9bce985b3e92631a9103d5 Mon Sep 17 00:00:00 2001
From: Dhruv Chawla <dhruvc at nvidia.com>
Date: Fri, 8 Mar 2024 15:56:17 +0530
Subject: [PATCH 2/5] Rephrase comments
---
.../AArch64/GISel/AArch64InstructionSelector.cpp | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index 9ddf3eda453092..8e18b825b90a2e 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -5976,14 +5976,15 @@ bool AArch64InstructionSelector::selectBuildVector(MachineInstr &I,
RegOp.setReg(Reg);
RBI.constrainGenericRegister(DstReg, *RC, MRI);
} else if (PrevMI) {
- // We don't need a subregister copy. Save a copy by re-using the
- // destination register on the final insert.
+ // PrevMI is not nullptr, so we have generated inserts and don't need a
+ // subregister copy. Save a copy by re-using the destination register on the
+ // final insert.
PrevMI->getOperand(0).setReg(I.getOperand(0).getReg());
constrainSelectedInstRegOperands(*PrevMI, TII, TRI, RBI);
} else {
- // All the operands (other than the first one) to the G_BUILD_VECTOR were
- // undef, so PrevMI is nullptr. Emit a copy from the vector made from the
- // first operand to the destination register.
+ // All the operands (except the first one) to the G_BUILD_VECTOR were
+ // undef, so PrevMI is nullptr. Emit a copy to the destination register
+ // from the first operand.
const TargetRegisterClass *RC =
getRegClassForTypeOnBank(DstTy, *RBI.getRegBank(DstVec, MRI, TRI));
Register DstReg = I.getOperand(0).getReg();
>From 6611121445a215eed610336d7d559cb1265a7b10 Mon Sep 17 00:00:00 2001
From: Dhruv Chawla <dhruvc at nvidia.com>
Date: Mon, 11 Mar 2024 13:44:28 +0530
Subject: [PATCH 3/5] Rebase and update test
---
llvm/test/CodeGen/AArch64/fptrunc.ll | 22 ++++++++++++++--------
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/fptrunc.ll b/llvm/test/CodeGen/AArch64/fptrunc.ll
index 61dddd442976f8..9d0672d1c95ea1 100644
--- a/llvm/test/CodeGen/AArch64/fptrunc.ll
+++ b/llvm/test/CodeGen/AArch64/fptrunc.ll
@@ -81,14 +81,20 @@ entry:
}
define <2 x half> @fptrunc_v2f64_v2f16(<2 x double> %a) {
-; CHECK-LABEL: fptrunc_v2f64_v2f16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: mov d1, v0.d[1]
-; CHECK-NEXT: fcvt h0, d0
-; CHECK-NEXT: fcvt h1, d1
-; CHECK-NEXT: mov v0.h[1], v1.h[0]
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: fptrunc_v2f64_v2f16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fcvtxn v0.2s, v0.2d
+; CHECK-SD-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: fptrunc_v2f64_v2f16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: fcvt h0, d0
+; CHECK-GI-NEXT: fcvt h1, d1
+; CHECK-GI-NEXT: mov v0.h[1], v1.h[0]
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: ret
entry:
%c = fptrunc <2 x double> %a to <2 x half>
ret <2 x half> %c
>From f271f3bb0184db92be8419b59e2f623eaeb41cc6 Mon Sep 17 00:00:00 2001
From: Dhruv Chawla <dhruvc at nvidia.com>
Date: Mon, 11 Mar 2024 19:47:07 +0530
Subject: [PATCH 4/5] Refactor code to fold two branches into one
---
.../GISel/AArch64InstructionSelector.cpp | 35 +++++++++++--------
.../GlobalISel/select-build-vector.mir | 4 +--
2 files changed, 23 insertions(+), 16 deletions(-)
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index 8e18b825b90a2e..b45e1b0b2ca36c 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -5934,7 +5934,7 @@ bool AArch64InstructionSelector::selectBuildVector(MachineInstr &I,
// Keep track of the last MI we inserted. Later on, we might be able to save
// a copy using it.
- MachineInstr *PrevMI = nullptr;
+ MachineInstr *PrevMI = ScalarToVec;
for (unsigned i = 2, e = DstSize / EltSize + 1; i < e; ++i) {
// Note that if we don't do a subregister copy, we can end up making an
// extra register.
@@ -5975,21 +5975,28 @@ bool AArch64InstructionSelector::selectBuildVector(MachineInstr &I,
MachineOperand &RegOp = I.getOperand(1);
RegOp.setReg(Reg);
RBI.constrainGenericRegister(DstReg, *RC, MRI);
- } else if (PrevMI) {
- // PrevMI is not nullptr, so we have generated inserts and don't need a
- // subregister copy. Save a copy by re-using the destination register on the
- // final insert.
+ } else {
+ // We either have a vector with all elements (except the first one) undef or
+ // at least one non-undef non-first element. In the first case, we need to
+ // constrain the output register ourselves as we may have generated an
+ // INSERT_SUBREG operation which is a generic operation for which the
+ // output regclass cannot be automatically chosen.
+ //
+ // In the second case, there is no need to do this as it may generate an
+ // instruction like INSvi32gpr where the regclass can be automatically
+ // chosen.
+ //
+ // Also, we save a copy by re-using the destination register on the final
+ // insert.
PrevMI->getOperand(0).setReg(I.getOperand(0).getReg());
constrainSelectedInstRegOperands(*PrevMI, TII, TRI, RBI);
- } else {
- // All the operands (except the first one) to the G_BUILD_VECTOR were
- // undef, so PrevMI is nullptr. Emit a copy to the destination register
- // from the first operand.
- const TargetRegisterClass *RC =
- getRegClassForTypeOnBank(DstTy, *RBI.getRegBank(DstVec, MRI, TRI));
- Register DstReg = I.getOperand(0).getReg();
- MIB.buildInstr(TargetOpcode::COPY, {DstReg}, {}).addReg(DstVec, 0);
- RBI.constrainGenericRegister(DstReg, *RC, MRI);
+
+ Register DstReg = PrevMI->getOperand(0).getReg();
+ if (PrevMI == ScalarToVec && DstReg.isVirtual()) {
+ const TargetRegisterClass *RC =
+ getRegClassForTypeOnBank(DstTy, *RBI.getRegBank(DstVec, MRI, TRI));
+ RBI.constrainGenericRegister(DstReg, *RC, MRI);
+ }
}
I.eraseFromParent();
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir
index 9e3f65cbe218d1..71a2bd2ddcc6eb 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir
@@ -267,8 +267,8 @@ body: |
; CHECK: liveins: $w0
; CHECK: %val:gpr32all = COPY $w0
; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
- ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %val, %subreg.ssub
- ; CHECK: $q0 = COPY [[INSERT_SUBREG]]
+ ; CHECK: %bv:fpr128 = INSERT_SUBREG [[DEF]], %val, %subreg.ssub
+ ; CHECK: $q0 = COPY %bv
; CHECK: RET_ReallyLR implicit $q0
%val:gpr(s32) = COPY $w0
%undef:gpr(s32) = G_IMPLICIT_DEF
>From 1353c0824dfa5f11bd42bd7ffe8709c83285ff9b Mon Sep 17 00:00:00 2001
From: Dhruv Chawla <dhruvc at nvidia.com>
Date: Tue, 12 Mar 2024 09:25:23 +0530
Subject: [PATCH 5/5] Refactor function call
---
llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index b45e1b0b2ca36c..7a49422c064b7c 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -5940,7 +5940,7 @@ bool AArch64InstructionSelector::selectBuildVector(MachineInstr &I,
// extra register.
Register OpReg = I.getOperand(i).getReg();
// Do not emit inserts for undefs
- if (!getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, OpReg, MRI)) {
+ if (!getOpcodeDef<GImplicitDef>(OpReg, MRI)) {
PrevMI = &*emitLaneInsert(std::nullopt, DstVec, OpReg, i - 1, RB, MIB);
DstVec = PrevMI->getOperand(0).getReg();
}
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