[lld] [llvm] [RISCV] Support RISCV Atomics ABI attributes (PR #84597)
Paul Kirth via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 8 19:17:13 PST 2024
https://github.com/ilovepi updated https://github.com/llvm/llvm-project/pull/84597
>From 714784926146c6b7873c3c702be9b87024861130 Mon Sep 17 00:00:00 2001
From: Paul Kirth <paulkirth at google.com>
Date: Fri, 8 Mar 2024 19:11:48 -0800
Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=?UTF-8?q?itial=20version?=
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Created using spr 1.3.4
---
lld/ELF/Arch/RISCV.cpp | 90 +++++++++++++
lld/test/ELF/riscv-attributes.s | 126 ++++++++++++++++++
.../llvm/Support/RISCVAttributeParser.h | 1 +
llvm/include/llvm/Support/RISCVAttributes.h | 13 ++
llvm/lib/Support/RISCVAttributeParser.cpp | 18 ++-
llvm/lib/Support/RISCVAttributes.cpp | 1 +
.../MCTargetDesc/RISCVTargetStreamer.cpp | 7 +
llvm/lib/Target/RISCV/RISCVFeatures.td | 6 +-
llvm/test/CodeGen/RISCV/atomic-load-store.ll | 16 +--
llvm/test/CodeGen/RISCV/attributes.ll | 10 +-
llvm/test/CodeGen/RISCV/forced-atomics.ll | 12 +-
llvm/test/MC/RISCV/attribute.s | 3 +
llvm/test/MC/RISCV/invalid-attribute.s | 3 +
13 files changed, 287 insertions(+), 19 deletions(-)
diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp
index 4798c86f7d1b61..e44583fb80fd31 100644
--- a/lld/ELF/Arch/RISCV.cpp
+++ b/lld/ELF/Arch/RISCV.cpp
@@ -1084,10 +1084,88 @@ static void mergeArch(RISCVISAInfo::OrderedExtensionMap &mergedExts,
}
}
+static void mergeAtomic(DenseMap<unsigned, unsigned> &intAttr,
+ const InputSectionBase *oldSection,
+ const InputSectionBase *newSection,
+ unsigned int oldTag,
+ unsigned int newTag) {
+ using RISCVAttrs::RISCVAtomicAbiTag::AtomicABI;
+ llvm::errs() << "oldTag=" << oldTag << ", newTag=" << newTag <<"\n";
+ // Same tags stay the same, and UNKNOWN is compatible with anything
+ if (oldTag == newTag || newTag == AtomicABI::UNKNOWN)
+ return;
+
+ auto attr = RISCVAttrs::ATOMIC_ABI;
+ switch (oldTag) {
+ case AtomicABI::UNKNOWN:
+ intAttr[attr] = newTag;
+ return;
+ case AtomicABI::A6C:
+ switch (newTag) {
+ case AtomicABI::A6S:
+ intAttr[attr] = AtomicABI::A6C;
+ return;
+ case AtomicABI::A7:
+ errorOrWarn(toString(oldSection) + " has atomic_abi=" + Twine(oldTag) +
+ " but " + toString(newSection) +
+ " has atomic_abi=" + Twine(newTag));
+ return;
+ };
+
+ case AtomicABI::A6S:
+ switch (newTag) {
+ case AtomicABI::A6C:
+ intAttr[attr] = AtomicABI::A6C;
+ return;
+ case AtomicABI::A7:
+ intAttr[attr] = AtomicABI::A7;
+ return;
+ };
+
+ case AtomicABI::A7:
+ switch (newTag) {
+ case AtomicABI::A6S:
+ intAttr[attr] = AtomicABI::A7;
+ return;
+ case AtomicABI::A6C:
+ errorOrWarn(toString(oldSection) + " has atomic_abi=" + Twine(oldTag) +
+ " but " + toString(newSection) +
+ " has atomic_abi=" + Twine(newTag));
+ return;
+ };
+ default:
+ llvm_unreachable("unknown AtomicABI");
+ };
+}
+
+static void mergeX3RegUse(DenseMap<unsigned, unsigned> &intAttr,
+ const InputSectionBase *oldSection,
+ const InputSectionBase *newSection,
+ unsigned int oldTag,
+ unsigned int newTag) {
+ // X3/GP register usage ar incompatible and cannot be merged, with the
+ // exception of the UNKNOWN or 0 value
+ using RISCVAttrs::RISCVX3RegUse::X3RegUsage;
+ auto attr = RISCVAttrs::X3_REG_USAGE;
+ if (newTag == X3RegUsage::UNKNOWN)
+ return;
+ if (oldTag == X3RegUsage::UNKNOWN)
+ intAttr[attr] = newTag;
+ if (oldTag != newTag) {
+ errorOrWarn(toString(oldSection) + " has x3_reg_usage=" + Twine(oldTag) +
+ " but " + toString(newSection) +
+ " has x3_reg_usage=" + Twine(newTag));
+ return;
+ }
+ // TODO: do we need to check the tags are < 2047?
+}
+
static RISCVAttributesSection *
mergeAttributesSection(const SmallVector<InputSectionBase *, 0> §ions) {
RISCVISAInfo::OrderedExtensionMap exts;
const InputSectionBase *firstStackAlign = nullptr;
+ const InputSectionBase *firstAtomicAbi = nullptr;
+ const InputSectionBase *firstX3RegUse = nullptr;
unsigned firstStackAlignValue = 0, xlen = 0;
bool hasArch = false;
@@ -1134,6 +1212,18 @@ mergeAttributesSection(const SmallVector<InputSectionBase *, 0> §ions) {
case RISCVAttrs::PRIV_SPEC_MINOR:
case RISCVAttrs::PRIV_SPEC_REVISION:
break;
+
+ case llvm::RISCVAttrs::AttrType::ATOMIC_ABI:
+ if (auto i = parser.getAttributeValue(tag.attr)) {
+ auto r = merged.intAttr.try_emplace(tag.attr, *i);
+ if (r.second) {
+ firstAtomicAbi = sec;
+ } else {
+ mergeAtomic(merged.intAttr, firstAtomicAbi, sec, r.first->getSecond(), *i);
+ llvm::errs() << "Merged Attr = " <<merged.intAttr[tag.attr] << "\n";
+ }
+ }
+ continue;
}
// Fallback for deprecated priv_spec* and other unknown attributes: retain
diff --git a/lld/test/ELF/riscv-attributes.s b/lld/test/ELF/riscv-attributes.s
index d0ce0941269ec4..964fec43b52847 100644
--- a/lld/test/ELF/riscv-attributes.s
+++ b/lld/test/ELF/riscv-attributes.s
@@ -44,6 +44,30 @@
# RUN: not ld.lld a.o b.o c.o diff_stack_align.o -o /dev/null 2>&1 | FileCheck %s --check-prefix=STACK_ALIGN --implicit-check-not=error:
# STACK_ALIGN: error: diff_stack_align.o:(.riscv.attributes) has stack_align=32 but a.o:(.riscv.attributes) has stack_align=16
+## merging atomic_abi values for A6C and A7 lead to an error.
+# RUN: llvm-mc -filetype=obj -triple=riscv64 atomic_abi_A6C.s -o atomic_abi_A6C.o
+# RUN: llvm-mc -filetype=obj -triple=riscv64 atomic_abi_A7.s -o atomic_abi_A7.o
+# RUN: not ld.lld atomic_abi_A6C.o atomic_abi_A7.o -o /dev/null 2>&1 | FileCheck %s --check-prefix=ATOMIC_ABI_ERROR --implicit-check-not=error:
+# ATOMIC_ABI_ERROR: error: atomic_abi_A6C.o:(.riscv.attributes) has atomic_abi=1 but atomic_abi_A7.o:(.riscv.attributes) has atomic_abi=3
+
+
+# RUN: llvm-mc -filetype=obj -triple=riscv64 atomic_abi_A6S.s -o atomic_abi_A6S.o
+# RUN: ld.lld atomic_abi_A6S.o atomic_abi_A6C.o -o atomic_abi_A6C_A6S
+# RUN: llvm-readobj -A atomic_abi_A6C_A6S | FileCheck %s --check-prefix=A6C_A6S
+
+# RUN: ld.lld atomic_abi_A6S.o atomic_abi_A7.o -o atomic_abi_A6S_A7
+# RUN: llvm-readobj -A atomic_abi_A6S_A7 | FileCheck %s --check-prefix=A6S_A7
+
+# RUN: llvm-mc -filetype=obj -triple=riscv64 atomic_abi_unknown.s -o atomic_abi_unknown.o
+# RUN: ld.lld atomic_abi_unknown.o atomic_abi_A6C.o -o atomic_abi_A6C_unknown
+# RUN: llvm-readobj -A atomic_abi_A6C_unknown | FileCheck %s --check-prefixes=UNKNOWN_A6C
+
+# RUN: ld.lld atomic_abi_unknown.o atomic_abi_A6S.o -o atomic_abi_A6S_unknown
+# RUN: llvm-readobj -A atomic_abi_A6S_unknown | FileCheck %s --check-prefix=UNKNOWN_A6S
+
+# RUN: ld.lld atomic_abi_unknown.o atomic_abi_A7.o -o atomic_abi_A7_unknown
+# RUN: llvm-readobj -A atomic_abi_A7_unknown | FileCheck %s --check-prefix=UNKNOWN_A7
+
## The deprecated priv_spec is not handled as GNU ld does.
## Differing priv_spec attributes lead to an absent attribute.
# RUN: llvm-mc -filetype=obj -triple=riscv64 diff_priv_spec.s -o diff_priv_spec.o
@@ -286,6 +310,108 @@
.attribute priv_spec, 3
.attribute priv_spec_minor, 3
+#--- atomic_abi_unknown.s
+.attribute atomic_abi, 0
+
+#--- atomic_abi_A6C.s
+.attribute atomic_abi, 1
+
+#--- atomic_abi_A6S.s
+.attribute atomic_abi, 2
+
+#--- atomic_abi_A7.s
+.attribute atomic_abi, 3
+
+# UNKNOWN_A6C: BuildAttributes {
+# UNKNOWN_A6C: FormatVersion: 0x41
+# UNKNOWN_A6C: Section 1 {
+# UNKNOWN_A6C: SectionLength: 17
+# UNKNOWN_A6C: Vendor: riscv
+# UNKNOWN_A6C: Tag: Tag_File (0x1)
+# UNKNOWN_A6C: Size: 7
+# UNKNOWN_A6C: FileAttributes {
+# UNKNOWN_A6C: Attribute {
+# UNKNOWN_A6C: Tag: 14
+# UNKNOWN_A6C: Value: 1
+# UNKNOWN_A6C: TagName: atomic_abi
+# UNKNOWN_A6C: Description: Atomic ABI is 1
+# UNKNOWN_A6C: }
+# UNKNOWN_A6C: }
+# UNKNOWN_A6C: }
+# UNKNOWN_A6C: }
+
+# UNKNOWN_A6S: BuildAttributes {
+# UNKNOWN_A6S: FormatVersion: 0x41
+# UNKNOWN_A6S: Section 1 {
+# UNKNOWN_A6S: SectionLength: 17
+# UNKNOWN_A6S: Vendor: riscv
+# UNKNOWN_A6S: Tag: Tag_File (0x1)
+# UNKNOWN_A6S: Size: 7
+# UNKNOWN_A6S: FileAttributes {
+# UNKNOWN_A6S: Attribute {
+# UNKNOWN_A6S: Tag: 14
+# UNKNOWN_A6S: Value: 2
+# UNKNOWN_A6S: TagName: atomic_abi
+# UNKNOWN_A6S: Description: Atomic ABI is 2
+# UNKNOWN_A6S: }
+# UNKNOWN_A6S: }
+# UNKNOWN_A6S: }
+# UNKNOWN_A6S: }
+
+# UNKNOWN_A7: BuildAttributes {
+# UNKNOWN_A7: FormatVersion: 0x41
+# UNKNOWN_A7: Section 1 {
+# UNKNOWN_A7: SectionLength: 17
+# UNKNOWN_A7: Vendor: riscv
+# UNKNOWN_A7: Tag: Tag_File (0x1)
+# UNKNOWN_A7: Size: 7
+# UNKNOWN_A7: FileAttributes {
+# UNKNOWN_A7: Attribute {
+# UNKNOWN_A7: Tag: 14
+# UNKNOWN_A7: Value: 3
+# UNKNOWN_A7: TagName: atomic_abi
+# UNKNOWN_A7: Description: Atomic ABI is 3
+# UNKNOWN_A7: }
+# UNKNOWN_A7: }
+# UNKNOWN_A7: }
+# UNKNOWN_A7: }
+
+# A6C_A6S: BuildAttributes {
+# A6C_A6S: FormatVersion: 0x41
+# A6C_A6S: Section 1 {
+# A6C_A6S: SectionLength: 17
+# A6C_A6S: Vendor: riscv
+# A6C_A6S: Tag: Tag_File (0x1)
+# A6C_A6S: Size: 7
+# A6C_A6S: FileAttributes {
+# A6C_A6S: Attribute {
+# A6C_A6S: Tag: 14
+# A6C_A6S: Value: 1
+# A6C_A6S: TagName: atomic_abi
+# A6C_A6S: Description: Atomic ABI is 1
+# A6C_A6S: }
+# A6C_A6S: }
+# A6C_A6S: }
+# A6C_A6S: }
+
+# A6S_A7: BuildAttributes {
+# A6S_A7: FormatVersion: 0x41
+# A6S_A7: Section 1 {
+# A6S_A7: SectionLength: 17
+# A6S_A7: Vendor: riscv
+# A6S_A7: Tag: Tag_File (0x1)
+# A6S_A7: Size: 7
+# A6S_A7: FileAttributes {
+# A6S_A7: Attribute {
+# A6S_A7: Tag: 14
+# A6S_A7: Value: 3
+# A6S_A7: TagName: atomic_abi
+# A6S_A7: Description: Atomic ABI is 3
+# A6S_A7: }
+# A6S_A7: }
+# A6S_A7: }
+# A6S_A7: }
+
#--- unknown13.s
.attribute 13, "0"
#--- unknown13a.s
diff --git a/llvm/include/llvm/Support/RISCVAttributeParser.h b/llvm/include/llvm/Support/RISCVAttributeParser.h
index 305adffbe851e7..9f295504de959e 100644
--- a/llvm/include/llvm/Support/RISCVAttributeParser.h
+++ b/llvm/include/llvm/Support/RISCVAttributeParser.h
@@ -24,6 +24,7 @@ class RISCVAttributeParser : public ELFAttributeParser {
Error unalignedAccess(unsigned tag);
Error stackAlign(unsigned tag);
+ Error atomicAbi(unsigned tag);
public:
RISCVAttributeParser(ScopedPrinter *sw)
diff --git a/llvm/include/llvm/Support/RISCVAttributes.h b/llvm/include/llvm/Support/RISCVAttributes.h
index 18f5a84d21f250..5def890a727355 100644
--- a/llvm/include/llvm/Support/RISCVAttributes.h
+++ b/llvm/include/llvm/Support/RISCVAttributes.h
@@ -32,8 +32,21 @@ enum AttrType : unsigned {
PRIV_SPEC = 8,
PRIV_SPEC_MINOR = 10,
PRIV_SPEC_REVISION = 12,
+ ATOMIC_ABI = 14,
};
+namespace RISCVAtomicAbiTag {
+enum AtomicABI : unsigned {
+ // Values for Tag_RISCV_atomic_abi
+ // Defined at
+ // https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#tag_riscv_atomic_abi-14-uleb128version
+ UNKNOWN = 0,
+ A6C = 1,
+ A6S = 2,
+ A7 = 3,
+};
+} // namespace RISCVAtomicAbiTag
+
enum { NOT_ALLOWED = 0, ALLOWED = 1 };
} // namespace RISCVAttrs
diff --git a/llvm/lib/Support/RISCVAttributeParser.cpp b/llvm/lib/Support/RISCVAttributeParser.cpp
index 7ce4b6ab161cd3..b9515134181edb 100644
--- a/llvm/lib/Support/RISCVAttributeParser.cpp
+++ b/llvm/lib/Support/RISCVAttributeParser.cpp
@@ -36,7 +36,23 @@ const RISCVAttributeParser::DisplayHandler
{
RISCVAttrs::UNALIGNED_ACCESS,
&RISCVAttributeParser::unalignedAccess,
- }};
+ },
+ {
+ RISCVAttrs::ATOMIC_ABI,
+ &RISCVAttributeParser::atomicAbi,
+ },
+ {
+ RISCVAttrs::X3_REG_USAGE,
+ &RISCVAttributeParser::x3RegUsage,
+ },
+};
+
+Error RISCVAttributeParser::atomicAbi(unsigned Tag) {
+ uint64_t Value = de.getULEB128(cursor);
+ std::string Description = "Atomic ABI is " + utostr(Value);
+ printAttribute(Tag, Value, Description);
+ return Error::success();
+}
Error RISCVAttributeParser::unalignedAccess(unsigned tag) {
static const char *strings[] = {"No unaligned access", "Unaligned access"};
diff --git a/llvm/lib/Support/RISCVAttributes.cpp b/llvm/lib/Support/RISCVAttributes.cpp
index 9e629760d3d842..dc70d65acba063 100644
--- a/llvm/lib/Support/RISCVAttributes.cpp
+++ b/llvm/lib/Support/RISCVAttributes.cpp
@@ -18,6 +18,7 @@ static constexpr TagNameItem tagData[] = {
{PRIV_SPEC, "Tag_priv_spec"},
{PRIV_SPEC_MINOR, "Tag_priv_spec_minor"},
{PRIV_SPEC_REVISION, "Tag_priv_spec_revision"},
+ {ATOMIC_ABI, "Tag_atomic_abi"},
};
constexpr TagNameMap RISCVAttributeTags{tagData};
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
index 4a4b1e13c2b9ec..3f4d6921841a27 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
@@ -75,6 +75,13 @@ void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI,
auto &ISAInfo = *ParseResult;
emitTextAttribute(RISCVAttrs::ARCH, ISAInfo->toString());
}
+
+ if (STI.hasFeature(RISCV::FeatureStdExtA)) {
+ unsigned AtomicABITag = STI.hasFeature(RISCV::FeatureTrailingSeqCstFence)
+ ? RISCVAttrs::RISCVAtomicAbiTag::AtomicABI::A6S
+ : RISCVAttrs::RISCVAtomicAbiTag::AtomicABI::A6C;
+ emitAttribute(RISCVAttrs::ATOMIC_ABI, AtomicABITag);
+ }
}
// This part is for ascii assembly output
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 83619ccb24baa3..e3ce527b84a985 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1154,10 +1154,10 @@ foreach i = {1-31} in
def FeatureSaveRestore : SubtargetFeature<"save-restore", "EnableSaveRestore",
"true", "Enable save/restore.">;
-def FeatureTrailingSeqCstFence : SubtargetFeature<"seq-cst-trailing-fence",
+def FeatureTrailingSeqCstFence : SubtargetFeature<"no-seq-cst-trailing-fence",
"EnableSeqCstTrailingFence",
- "true",
- "Enable trailing fence for seq-cst store.">;
+ "false",
+ "Disable trailing fence for seq-cst store.">;
def FeatureFastUnalignedAccess
: SubtargetFeature<"fast-unaligned-access", "HasFastUnalignedAccess",
diff --git a/llvm/test/CodeGen/RISCV/atomic-load-store.ll b/llvm/test/CodeGen/RISCV/atomic-load-store.ll
index 2d1fc21cda89b0..30680957ecbc6b 100644
--- a/llvm/test/CodeGen/RISCV/atomic-load-store.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-load-store.ll
@@ -1,26 +1,26 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
-; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+a,+no-seq-cst-trailing-fence -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-WMO %s
-; RUN: llc -mtriple=riscv32 -mattr=+a,+experimental-ztso -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+a,+no-seq-cst-trailing-fence,+experimental-ztso -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-TSO %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s
-; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+a,+no-seq-cst-trailing-fence -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-WMO %s
-; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-ztso -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+a,+no-seq-cst-trailing-fence,+experimental-ztso -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-TSO %s
-; RUN: llc -mtriple=riscv32 -mattr=+a,+seq-cst-trailing-fence -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-WMO-TRAILING-FENCE %s
-; RUN: llc -mtriple=riscv32 -mattr=+a,+experimental-ztso,+seq-cst-trailing-fence -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+a,+experimental-ztso -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-TSO-TRAILING-FENCE %s
-; RUN: llc -mtriple=riscv64 -mattr=+a,+seq-cst-trailing-fence -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-WMO-TRAILING-FENCE %s
-; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-ztso,+seq-cst-trailing-fence -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-ztso -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-TSO-TRAILING-FENCE %s
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index cc332df271043f..95bce2ae8a071a 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -128,7 +128,8 @@
; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s
; RUN: llc -mtriple=riscv64 -mattr=+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV64ZMMUL %s
; RUN: llc -mtriple=riscv64 -mattr=+m,+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV64MZMMUL %s
-; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefixes=CHECK,RV64A %s
+; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefixes=CHECK,RV64A,A6C %s
+; RUN: llc -mtriple=riscv64 -mattr=+a,+no-seq-cst-trailing-fence %s -o - | FileCheck --check-prefixes=CHECK,RV64A,A6S %s
; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefixes=CHECK,RV64F %s
; RUN: llc -mtriple=riscv64 -mattr=+d %s -o - | FileCheck --check-prefixes=CHECK,RV64D %s
; RUN: llc -mtriple=riscv64 -mattr=+c %s -o - | FileCheck --check-prefixes=CHECK,RV64C %s
@@ -512,3 +513,10 @@ define i32 @addi(i32 %a) {
%1 = add i32 %a, 1
ret i32 %1
}
+
+define i8 @atomic_load_i8_seq_cst(ptr %a) nounwind {
+ %1 = load atomic i8, ptr %a seq_cst, align 1
+ ret i8 %1
+; A6S: .attribute 14, 2
+; A6C: .attribute 14, 1
+}
diff --git a/llvm/test/CodeGen/RISCV/forced-atomics.ll b/llvm/test/CodeGen/RISCV/forced-atomics.ll
index f6a53a9d76dd35..96d3eede524510 100644
--- a/llvm/test/CodeGen/RISCV/forced-atomics.ll
+++ b/llvm/test/CodeGen/RISCV/forced-atomics.ll
@@ -1,12 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+seq-cst-trailing-fence < %s | FileCheck %s --check-prefixes=RV32,RV32-NO-ATOMIC
+; RUN: llc -mtriple=riscv32 -mattr=+no-seq-cst-trailing-fence < %s | FileCheck %s --check-prefixes=RV32,RV32-NO-ATOMIC
; RUN: llc -mtriple=riscv32 < %s | FileCheck %s --check-prefixes=RV32,RV32-NO-ATOMIC
-; RUN: llc -mtriple=riscv32 -mattr=+forced-atomics < %s | FileCheck %s --check-prefixes=RV32,RV32-ATOMIC
-; RUN: llc -mtriple=riscv32 -mattr=+forced-atomics,+seq-cst-trailing-fence < %s | FileCheck %s --check-prefixes=RV32,RV32-ATOMIC-TRAILING
+; RUN: llc -mtriple=riscv32 -mattr=+forced-atomics,+no-seq-cst-trailing-fence < %s | FileCheck %s --check-prefixes=RV32,RV32-ATOMIC
+; RUN: llc -mtriple=riscv32 -mattr=+forced-atomics < %s | FileCheck %s --check-prefixes=RV32,RV32-ATOMIC-TRAILING
; RUN: llc -mtriple=riscv64 < %s | FileCheck %s --check-prefixes=RV64,RV64-NO-ATOMIC
-; RUN: llc -mtriple=riscv64 -mattr=+seq-cst-trailing-fence < %s | FileCheck %s --check-prefixes=RV64,RV64-NO-ATOMIC
-; RUN: llc -mtriple=riscv64 -mattr=+forced-atomics < %s | FileCheck %s --check-prefixes=RV64,RV64-ATOMIC
-; RUN: llc -mtriple=riscv64 -mattr=+forced-atomics,+seq-cst-trailing-fence < %s | FileCheck %s --check-prefixes=RV64,RV64-ATOMIC-TRAILING
+; RUN: llc -mtriple=riscv64 -mattr=+no-seq-cst-trailing-fence < %s | FileCheck %s --check-prefixes=RV64,RV64-NO-ATOMIC
+; RUN: llc -mtriple=riscv64 -mattr=+forced-atomics,+no-seq-cst-trailing-fence < %s | FileCheck %s --check-prefixes=RV64,RV64-ATOMIC
+; RUN: llc -mtriple=riscv64 -mattr=+forced-atomics < %s | FileCheck %s --check-prefixes=RV64,RV64-ATOMIC-TRAILING
define i8 @load8(ptr %p) nounwind {
; RV32-NO-ATOMIC-LABEL: load8:
diff --git a/llvm/test/MC/RISCV/attribute.s b/llvm/test/MC/RISCV/attribute.s
index 56f0cb1daf176f..0a9d86da55261c 100644
--- a/llvm/test/MC/RISCV/attribute.s
+++ b/llvm/test/MC/RISCV/attribute.s
@@ -24,3 +24,6 @@
.attribute priv_spec_revision, 0
# CHECK: attribute 12, 0
+.attribute atomic_abi, 0
+# CHECK: attribute 14, 0
+
diff --git a/llvm/test/MC/RISCV/invalid-attribute.s b/llvm/test/MC/RISCV/invalid-attribute.s
index 1d732af83cda35..2ebf7ddc9aff85 100644
--- a/llvm/test/MC/RISCV/invalid-attribute.s
+++ b/llvm/test/MC/RISCV/invalid-attribute.s
@@ -33,3 +33,6 @@
.attribute arch, 30
# CHECK: [[@LINE-1]]:18: error: expected string constant
+
+.attribute atomic_abi, "16"
+# CHECK: [[@LINE-1]]:24: error: expected numeric constant
>From 2b14f068e24fd1c4649f5d1f728be675488806ac Mon Sep 17 00:00:00 2001
From: Paul Kirth <paulkirth at google.com>
Date: Fri, 8 Mar 2024 19:17:02 -0800
Subject: [PATCH 2/2] Fix formatting
Created using spr 1.3.4
---
lld/ELF/Arch/RISCV.cpp | 20 +++++++++----------
.../MCTargetDesc/RISCVTargetStreamer.cpp | 4 ++--
2 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp
index e44583fb80fd31..70f28ea8ec9ed8 100644
--- a/lld/ELF/Arch/RISCV.cpp
+++ b/lld/ELF/Arch/RISCV.cpp
@@ -1086,11 +1086,10 @@ static void mergeArch(RISCVISAInfo::OrderedExtensionMap &mergedExts,
static void mergeAtomic(DenseMap<unsigned, unsigned> &intAttr,
const InputSectionBase *oldSection,
- const InputSectionBase *newSection,
- unsigned int oldTag,
+ const InputSectionBase *newSection, unsigned int oldTag,
unsigned int newTag) {
using RISCVAttrs::RISCVAtomicAbiTag::AtomicABI;
- llvm::errs() << "oldTag=" << oldTag << ", newTag=" << newTag <<"\n";
+ llvm::errs() << "oldTag=" << oldTag << ", newTag=" << newTag << "\n";
// Same tags stay the same, and UNKNOWN is compatible with anything
if (oldTag == newTag || newTag == AtomicABI::UNKNOWN)
return;
@@ -1139,10 +1138,9 @@ static void mergeAtomic(DenseMap<unsigned, unsigned> &intAttr,
}
static void mergeX3RegUse(DenseMap<unsigned, unsigned> &intAttr,
- const InputSectionBase *oldSection,
- const InputSectionBase *newSection,
- unsigned int oldTag,
- unsigned int newTag) {
+ const InputSectionBase *oldSection,
+ const InputSectionBase *newSection,
+ unsigned int oldTag, unsigned int newTag) {
// X3/GP register usage ar incompatible and cannot be merged, with the
// exception of the UNKNOWN or 0 value
using RISCVAttrs::RISCVX3RegUse::X3RegUsage;
@@ -1159,7 +1157,7 @@ static void mergeX3RegUse(DenseMap<unsigned, unsigned> &intAttr,
}
// TODO: do we need to check the tags are < 2047?
}
-
+
static RISCVAttributesSection *
mergeAttributesSection(const SmallVector<InputSectionBase *, 0> §ions) {
RISCVISAInfo::OrderedExtensionMap exts;
@@ -1219,8 +1217,10 @@ mergeAttributesSection(const SmallVector<InputSectionBase *, 0> §ions) {
if (r.second) {
firstAtomicAbi = sec;
} else {
- mergeAtomic(merged.intAttr, firstAtomicAbi, sec, r.first->getSecond(), *i);
- llvm::errs() << "Merged Attr = " <<merged.intAttr[tag.attr] << "\n";
+ mergeAtomic(merged.intAttr, firstAtomicAbi, sec,
+ r.first->getSecond(), *i);
+ llvm::errs() << "Merged Attr = " << merged.intAttr[tag.attr]
+ << "\n";
}
}
continue;
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
index 3f4d6921841a27..9a2621516b3468 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
@@ -78,8 +78,8 @@ void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI,
if (STI.hasFeature(RISCV::FeatureStdExtA)) {
unsigned AtomicABITag = STI.hasFeature(RISCV::FeatureTrailingSeqCstFence)
- ? RISCVAttrs::RISCVAtomicAbiTag::AtomicABI::A6S
- : RISCVAttrs::RISCVAtomicAbiTag::AtomicABI::A6C;
+ ? RISCVAttrs::RISCVAtomicAbiTag::AtomicABI::A6S
+ : RISCVAttrs::RISCVAtomicAbiTag::AtomicABI::A6C;
emitAttribute(RISCVAttrs::ATOMIC_ABI, AtomicABITag);
}
}
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