[llvm] [RISCV][NFC] Add generateMCInstSeq in RISCVMatInt (PR #84462)
Sacha Coppey via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 8 09:30:42 PST 2024
https://github.com/Zeavee updated https://github.com/llvm/llvm-project/pull/84462
>From 18f03c91be2673e08ca79c6316e4bc477a741f13 Mon Sep 17 00:00:00 2001
From: Sacha Coppey <sacha.coppey at oracle.com>
Date: Fri, 8 Mar 2024 11:59:01 +0100
Subject: [PATCH 1/3] Add generateMCInstSeq in RISCVMatInt
---
.../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 31 ++------------
.../Target/RISCV/MCTargetDesc/RISCVMatInt.cpp | 41 +++++++++++++++++++
.../Target/RISCV/MCTargetDesc/RISCVMatInt.h | 6 +++
3 files changed, 51 insertions(+), 27 deletions(-)
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index d83979a873f2a3..78a6dd210bbcb6 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -3081,34 +3081,11 @@ void RISCVAsmParser::emitToStreamer(MCStreamer &S, const MCInst &Inst) {
void RISCVAsmParser::emitLoadImm(MCRegister DestReg, int64_t Value,
MCStreamer &Out) {
- RISCVMatInt::InstSeq Seq = RISCVMatInt::generateInstSeq(Value, getSTI());
-
- MCRegister SrcReg = RISCV::X0;
- for (const RISCVMatInt::Inst &Inst : Seq) {
- switch (Inst.getOpndKind()) {
- case RISCVMatInt::Imm:
- emitToStreamer(Out,
- MCInstBuilder(Inst.getOpcode()).addReg(DestReg).addImm(Inst.getImm()));
- break;
- case RISCVMatInt::RegX0:
- emitToStreamer(
- Out, MCInstBuilder(Inst.getOpcode()).addReg(DestReg).addReg(SrcReg).addReg(
- RISCV::X0));
- break;
- case RISCVMatInt::RegReg:
- emitToStreamer(
- Out, MCInstBuilder(Inst.getOpcode()).addReg(DestReg).addReg(SrcReg).addReg(
- SrcReg));
- break;
- case RISCVMatInt::RegImm:
- emitToStreamer(
- Out, MCInstBuilder(Inst.getOpcode()).addReg(DestReg).addReg(SrcReg).addImm(
- Inst.getImm()));
- break;
- }
+ SmallVector<MCInst, 8> Seq =
+ RISCVMatInt::generateMCInstSeq(Value, getSTI(), DestReg);
- // Only the first instruction has X0 as its source.
- SrcReg = DestReg;
+ for (MCInst &Inst : Seq) {
+ emitToStreamer(Out, Inst);
}
}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
index 4358a5b878e631..8ebdcd577fab66 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
@@ -9,6 +9,7 @@
#include "RISCVMatInt.h"
#include "MCTargetDesc/RISCVMCTargetDesc.h"
#include "llvm/ADT/APInt.h"
+#include "llvm/MC/MCInstBuilder.h"
#include "llvm/Support/MathExtras.h"
using namespace llvm;
@@ -436,6 +437,46 @@ InstSeq generateInstSeq(int64_t Val, const MCSubtargetInfo &STI) {
return Res;
}
+SmallVector<MCInst, 8>
+generateMCInstSeq(int64_t Val, const MCSubtargetInfo &STI, MCRegister DestReg) {
+ RISCVMatInt::InstSeq Seq = RISCVMatInt::generateInstSeq(Val, STI);
+
+ SmallVector<MCInst, 8> Instructions;
+
+ MCRegister SrcReg = RISCV::X0;
+ for (RISCVMatInt::Inst &Inst : Seq) {
+ switch (Inst.getOpndKind()) {
+ case RISCVMatInt::Imm:
+ Instructions.push_back(MCInstBuilder(Inst.getOpcode())
+ .addReg(DestReg)
+ .addImm(Inst.getImm()));
+ break;
+ case RISCVMatInt::RegX0:
+ Instructions.push_back(MCInstBuilder(Inst.getOpcode())
+ .addReg(DestReg)
+ .addReg(SrcReg)
+ .addReg(RISCV::X0));
+ break;
+ case RISCVMatInt::RegReg:
+ Instructions.push_back(MCInstBuilder(Inst.getOpcode())
+ .addReg(DestReg)
+ .addReg(SrcReg)
+ .addReg(SrcReg));
+ break;
+ case RISCVMatInt::RegImm:
+ Instructions.push_back(MCInstBuilder(Inst.getOpcode())
+ .addReg(DestReg)
+ .addReg(SrcReg)
+ .addImm(Inst.getImm()));
+ break;
+ }
+
+ // Only the first instruction has X0 as its source.
+ SrcReg = DestReg;
+ }
+ return Instructions;
+}
+
InstSeq generateTwoRegInstSeq(int64_t Val, const MCSubtargetInfo &STI,
unsigned &ShiftAmt, unsigned &AddOpc) {
int64_t LoVal = SignExtend64<32>(Val);
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h
index 780f685463f300..70b1b9e492093f 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h
@@ -10,6 +10,8 @@
#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_MATINT_H
#include "llvm/ADT/SmallVector.h"
+#include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include <cstdint>
@@ -48,6 +50,10 @@ using InstSeq = SmallVector<Inst, 8>;
// instruction selection.
InstSeq generateInstSeq(int64_t Val, const MCSubtargetInfo &STI);
+// Helper to generate the generateInstSeq instruction sequence using MCInsts
+SmallVector<MCInst, 8>
+generateMCInstSeq(int64_t Val, const MCSubtargetInfo &STI, MCRegister DestReg);
+
// Helper to generate an instruction sequence that can materialize the given
// immediate value into a register using an additional temporary register. This
// handles cases where the constant can be generated by (ADD (SLLI X, C), X) or
>From cd3858692c232df8655a677ba0b02d9438fbcb7e Mon Sep 17 00:00:00 2001
From: Sacha Coppey <sacha.coppey at oracle.com>
Date: Fri, 8 Mar 2024 13:02:39 +0100
Subject: [PATCH 2/3] Replace SmallVector by SmallVectorImpl and pass it in the
parameters
---
.../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 4 +-
.../Target/RISCV/MCTargetDesc/RISCVMatInt.cpp | 37 +++++++++----------
.../Target/RISCV/MCTargetDesc/RISCVMatInt.h | 4 +-
3 files changed, 21 insertions(+), 24 deletions(-)
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 78a6dd210bbcb6..d62e56eea3555a 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -3081,8 +3081,8 @@ void RISCVAsmParser::emitToStreamer(MCStreamer &S, const MCInst &Inst) {
void RISCVAsmParser::emitLoadImm(MCRegister DestReg, int64_t Value,
MCStreamer &Out) {
- SmallVector<MCInst, 8> Seq =
- RISCVMatInt::generateMCInstSeq(Value, getSTI(), DestReg);
+ SmallVector<MCInst, 8> Seq;
+ RISCVMatInt::generateMCInstSeq(Value, getSTI(), DestReg, Seq);
for (MCInst &Inst : Seq) {
emitToStreamer(Out, Inst);
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
index 8ebdcd577fab66..c3bae152993ea4 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
@@ -437,44 +437,41 @@ InstSeq generateInstSeq(int64_t Val, const MCSubtargetInfo &STI) {
return Res;
}
-SmallVector<MCInst, 8>
-generateMCInstSeq(int64_t Val, const MCSubtargetInfo &STI, MCRegister DestReg) {
+void generateMCInstSeq(int64_t Val, const MCSubtargetInfo &STI,
+ MCRegister DestReg, SmallVectorImpl<MCInst> &Insts) {
RISCVMatInt::InstSeq Seq = RISCVMatInt::generateInstSeq(Val, STI);
- SmallVector<MCInst, 8> Instructions;
-
MCRegister SrcReg = RISCV::X0;
for (RISCVMatInt::Inst &Inst : Seq) {
switch (Inst.getOpndKind()) {
case RISCVMatInt::Imm:
- Instructions.push_back(MCInstBuilder(Inst.getOpcode())
- .addReg(DestReg)
- .addImm(Inst.getImm()));
+ Insts.push_back(MCInstBuilder(Inst.getOpcode())
+ .addReg(DestReg)
+ .addImm(Inst.getImm()));
break;
case RISCVMatInt::RegX0:
- Instructions.push_back(MCInstBuilder(Inst.getOpcode())
- .addReg(DestReg)
- .addReg(SrcReg)
- .addReg(RISCV::X0));
+ Insts.push_back(MCInstBuilder(Inst.getOpcode())
+ .addReg(DestReg)
+ .addReg(SrcReg)
+ .addReg(RISCV::X0));
break;
case RISCVMatInt::RegReg:
- Instructions.push_back(MCInstBuilder(Inst.getOpcode())
- .addReg(DestReg)
- .addReg(SrcReg)
- .addReg(SrcReg));
+ Insts.push_back(MCInstBuilder(Inst.getOpcode())
+ .addReg(DestReg)
+ .addReg(SrcReg)
+ .addReg(SrcReg));
break;
case RISCVMatInt::RegImm:
- Instructions.push_back(MCInstBuilder(Inst.getOpcode())
- .addReg(DestReg)
- .addReg(SrcReg)
- .addImm(Inst.getImm()));
+ Insts.push_back(MCInstBuilder(Inst.getOpcode())
+ .addReg(DestReg)
+ .addReg(SrcReg)
+ .addImm(Inst.getImm()));
break;
}
// Only the first instruction has X0 as its source.
SrcReg = DestReg;
}
- return Instructions;
}
InstSeq generateTwoRegInstSeq(int64_t Val, const MCSubtargetInfo &STI,
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h
index 70b1b9e492093f..13d552dd329bfc 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h
@@ -51,8 +51,8 @@ using InstSeq = SmallVector<Inst, 8>;
InstSeq generateInstSeq(int64_t Val, const MCSubtargetInfo &STI);
// Helper to generate the generateInstSeq instruction sequence using MCInsts
-SmallVector<MCInst, 8>
-generateMCInstSeq(int64_t Val, const MCSubtargetInfo &STI, MCRegister DestReg);
+void generateMCInstSeq(int64_t Val, const MCSubtargetInfo &STI,
+ MCRegister DestReg, SmallVectorImpl<MCInst> &Insts);
// Helper to generate an instruction sequence that can materialize the given
// immediate value into a register using an additional temporary register. This
>From 3b2524ce93b0894372c03dba70464afb6b21f32c Mon Sep 17 00:00:00 2001
From: Sacha Coppey <sacha.coppey at oracle.com>
Date: Fri, 8 Mar 2024 18:30:16 +0100
Subject: [PATCH 3/3] Remove MCInst import
---
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h
index 13d552dd329bfc..dd8fc421649745 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h
@@ -10,7 +10,6 @@
#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_MATINT_H
#include "llvm/ADT/SmallVector.h"
-#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include <cstdint>
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