[llvm] [RISCV][NFC] Add helpers for RVV register classes (PR #84144)
Wang Pengcheng via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 6 22:10:50 PST 2024
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84144
>From 1d7ca79a9880a27d6f829bae9ab105d826387216 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: Wed, 6 Mar 2024 17:10:06 +0800
Subject: [PATCH 1/4] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=?UTF-8?q?itial=20version?=
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Created using spr 1.3.4
---
llvm/lib/Target/RISCV/RISCVRegisterInfo.h | 22 ++++++++++++++++++--
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 18 +++-------------
2 files changed, 23 insertions(+), 17 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
index e46fe8ecb900fc..f5b4cac7dffd74 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
@@ -110,13 +110,31 @@ struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
return RC;
}
- bool doesRegClassHavePseudoInitUndef(
- const TargetRegisterClass *RC) const override {
+ bool isRVVRegClass(const TargetRegisterClass *RC) const {
return RISCV::VRRegClass.hasSubClassEq(RC) ||
RISCV::VRM2RegClass.hasSubClassEq(RC) ||
RISCV::VRM4RegClass.hasSubClassEq(RC) ||
RISCV::VRM8RegClass.hasSubClassEq(RC);
}
+
+ bool isRVVSegmentRegClass(const TargetRegisterClass *RC) const {
+ return RISCV::VRN2M1RegClass.hasSubClassEq(RC) ||
+ RISCV::VRN2M2RegClass.hasSubClassEq(RC) ||
+ RISCV::VRN2M4RegClass.hasSubClassEq(RC) ||
+ RISCV::VRN3M1RegClass.hasSubClassEq(RC) ||
+ RISCV::VRN3M2RegClass.hasSubClassEq(RC) ||
+ RISCV::VRN4M1RegClass.hasSubClassEq(RC) ||
+ RISCV::VRN4M2RegClass.hasSubClassEq(RC) ||
+ RISCV::VRN5M1RegClass.hasSubClassEq(RC) ||
+ RISCV::VRN6M1RegClass.hasSubClassEq(RC) ||
+ RISCV::VRN7M1RegClass.hasSubClassEq(RC) ||
+ RISCV::VRN8M1RegClass.hasSubClassEq(RC);
+ }
+
+ bool doesRegClassHavePseudoInitUndef(
+ const TargetRegisterClass *RC) const override {
+ return isRVVRegClass(RC);
+ }
};
}
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 6fe0abaccb9d98..e499f77fb7772b 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -14,6 +14,7 @@
#include "MCTargetDesc/RISCVBaseInfo.h"
#include "RISCV.h"
#include "RISCVMachineFunctionInfo.h"
+#include "RISCVRegisterInfo.h"
#include "RISCVTargetObjectFile.h"
#include "RISCVTargetTransformInfo.h"
#include "TargetInfo/RISCVTargetInfo.h"
@@ -278,21 +279,8 @@ class RVVRegisterRegAlloc : public RegisterRegAllocBase<RVVRegisterRegAlloc> {
static bool onlyAllocateRVVReg(const TargetRegisterInfo &TRI,
const TargetRegisterClass &RC) {
- return RISCV::VRRegClass.hasSubClassEq(&RC) ||
- RISCV::VRM2RegClass.hasSubClassEq(&RC) ||
- RISCV::VRM4RegClass.hasSubClassEq(&RC) ||
- RISCV::VRM8RegClass.hasSubClassEq(&RC) ||
- RISCV::VRN2M1RegClass.hasSubClassEq(&RC) ||
- RISCV::VRN2M2RegClass.hasSubClassEq(&RC) ||
- RISCV::VRN2M4RegClass.hasSubClassEq(&RC) ||
- RISCV::VRN3M1RegClass.hasSubClassEq(&RC) ||
- RISCV::VRN3M2RegClass.hasSubClassEq(&RC) ||
- RISCV::VRN4M1RegClass.hasSubClassEq(&RC) ||
- RISCV::VRN4M2RegClass.hasSubClassEq(&RC) ||
- RISCV::VRN5M1RegClass.hasSubClassEq(&RC) ||
- RISCV::VRN6M1RegClass.hasSubClassEq(&RC) ||
- RISCV::VRN7M1RegClass.hasSubClassEq(&RC) ||
- RISCV::VRN8M1RegClass.hasSubClassEq(&RC);
+ auto &RegInfo = static_cast<const RISCVRegisterInfo &>(TRI);
+ return RegInfo.isRVVRegClass(&RC) || RegInfo.isRVVSegmentRegClass(&RC);
}
static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
>From f7a62072bacac6a28a8895e6a351daa8c5ab2d31 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: Wed, 6 Mar 2024 17:15:47 +0800
Subject: [PATCH 2/4] Clean includes
Created using spr 1.3.4
---
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index e499f77fb7772b..12d030855a029c 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -14,7 +14,6 @@
#include "MCTargetDesc/RISCVBaseInfo.h"
#include "RISCV.h"
#include "RISCVMachineFunctionInfo.h"
-#include "RISCVRegisterInfo.h"
#include "RISCVTargetObjectFile.h"
#include "RISCVTargetTransformInfo.h"
#include "TargetInfo/RISCVTargetInfo.h"
>From a770aac59b3f29ed3134bd5a3624d52c34c77e09 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: Wed, 6 Mar 2024 17:30:42 +0800
Subject: [PATCH 3/4] Rename
Created using spr 1.3.4
---
llvm/lib/Target/RISCV/RISCVRegisterInfo.h | 14 +++++++++-----
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 3 +--
2 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
index f5b4cac7dffd74..e877ddc8e66d3b 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
@@ -110,14 +110,19 @@ struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
return RC;
}
- bool isRVVRegClass(const TargetRegisterClass *RC) const {
+ bool doesRegClassHavePseudoInitUndef(
+ const TargetRegisterClass *RC) const override {
+ return isVRRegClass(RC);
+ }
+
+ bool isVRRegClass(const TargetRegisterClass *RC) const {
return RISCV::VRRegClass.hasSubClassEq(RC) ||
RISCV::VRM2RegClass.hasSubClassEq(RC) ||
RISCV::VRM4RegClass.hasSubClassEq(RC) ||
RISCV::VRM8RegClass.hasSubClassEq(RC);
}
- bool isRVVSegmentRegClass(const TargetRegisterClass *RC) const {
+ bool isVRNRegClass(const TargetRegisterClass *RC) const {
return RISCV::VRN2M1RegClass.hasSubClassEq(RC) ||
RISCV::VRN2M2RegClass.hasSubClassEq(RC) ||
RISCV::VRN2M4RegClass.hasSubClassEq(RC) ||
@@ -131,9 +136,8 @@ struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
RISCV::VRN8M1RegClass.hasSubClassEq(RC);
}
- bool doesRegClassHavePseudoInitUndef(
- const TargetRegisterClass *RC) const override {
- return isRVVRegClass(RC);
+ bool isRVVRegClass(const TargetRegisterClass *RC) const {
+ return isVRRegClass(RC) || isVRNRegClass(RC);
}
};
}
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 12d030855a029c..9d62863a8bb4a8 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -278,8 +278,7 @@ class RVVRegisterRegAlloc : public RegisterRegAllocBase<RVVRegisterRegAlloc> {
static bool onlyAllocateRVVReg(const TargetRegisterInfo &TRI,
const TargetRegisterClass &RC) {
- auto &RegInfo = static_cast<const RISCVRegisterInfo &>(TRI);
- return RegInfo.isRVVRegClass(&RC) || RegInfo.isRVVSegmentRegClass(&RC);
+ return static_cast<const RISCVRegisterInfo &>(TRI).isRVVRegClass(&RC);
}
static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
>From 0ae3fcb55a0fbaa622f3fe7a7ed57131ca87e08b Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: Thu, 7 Mar 2024 14:10:39 +0800
Subject: [PATCH 4/4] Change to static methods
Created using spr 1.3.4
---
llvm/lib/Target/RISCV/RISCVRegisterInfo.h | 6 +++---
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
index e877ddc8e66d3b..943c4f2627cf2f 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
@@ -115,14 +115,14 @@ struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
return isVRRegClass(RC);
}
- bool isVRRegClass(const TargetRegisterClass *RC) const {
+ static bool isVRRegClass(const TargetRegisterClass *RC) {
return RISCV::VRRegClass.hasSubClassEq(RC) ||
RISCV::VRM2RegClass.hasSubClassEq(RC) ||
RISCV::VRM4RegClass.hasSubClassEq(RC) ||
RISCV::VRM8RegClass.hasSubClassEq(RC);
}
- bool isVRNRegClass(const TargetRegisterClass *RC) const {
+ static bool isVRNRegClass(const TargetRegisterClass *RC) {
return RISCV::VRN2M1RegClass.hasSubClassEq(RC) ||
RISCV::VRN2M2RegClass.hasSubClassEq(RC) ||
RISCV::VRN2M4RegClass.hasSubClassEq(RC) ||
@@ -136,7 +136,7 @@ struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
RISCV::VRN8M1RegClass.hasSubClassEq(RC);
}
- bool isRVVRegClass(const TargetRegisterClass *RC) const {
+ static bool isRVVRegClass(const TargetRegisterClass *RC) {
return isVRRegClass(RC) || isVRNRegClass(RC);
}
};
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 9d62863a8bb4a8..ae1a6f179a49e3 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -278,7 +278,7 @@ class RVVRegisterRegAlloc : public RegisterRegAllocBase<RVVRegisterRegAlloc> {
static bool onlyAllocateRVVReg(const TargetRegisterInfo &TRI,
const TargetRegisterClass &RC) {
- return static_cast<const RISCVRegisterInfo &>(TRI).isRVVRegClass(&RC);
+ return RISCVRegisterInfo::isRVVRegClass(&RC);
}
static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
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