[llvm] [llvm] Support fixed point multiplication on AArch64 (PR #84237)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 6 13:08:03 PST 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-selectiondag
Author: None (PiJoules)
<details>
<summary>Changes</summary>
Prior to this, fixed point multiplication would lead to this assertion error on AArhc64, armv8, and armv7.
```
_Accum f(_Accum x, _Accum y) { return x * y; }
// ./bin/clang++ -ffixed-point /tmp/test2.cc -c -S -o - -target aarch64 -O3
clang++: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:10245: void llvm::TargetLowering::forceExpandWideMUL(SelectionDAG &, const SDLoc &, bool, EVT, const SDValue, const SDValue, const SDValue, const SDValue, SDValue &, SDValue &) const: Assertion `Ret.getOpcode() == ISD::MERGE_VALUES && "Ret value is a collection of constituent nodes holding result."' failed.
```
This path into forceExpandWideMUL should only be taken if we don't support [US]MUL_LOHI or MULH[US] for the operand size (32 in this case). But we should also check if we can just leverage regular wide multiplication. That is, extend the operands from 32 to 64, do a regular 64-bit mul, then trunc and shift. These ops are certainly available on aarch64 but for wider types.
---
Full diff: https://github.com/llvm/llvm-project/pull/84237.diff
5 Files Affected:
- (modified) llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp (+12)
- (added) llvm/test/CodeGen/AArch64/smul_fix.ll (+93)
- (added) llvm/test/CodeGen/AArch64/smul_fix_sat.ll (+148)
- (added) llvm/test/CodeGen/AArch64/umul_fix.ll (+101)
- (added) llvm/test/CodeGen/AArch64/umul_fix_sat.ll (+146)
``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index a639cba5e35a80..96bdd7bf06d027 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -10345,6 +10345,7 @@ TargetLowering::expandFixedPointMul(SDNode *Node, SelectionDAG &DAG) const {
SDValue Lo, Hi;
unsigned LoHiOp = Signed ? ISD::SMUL_LOHI : ISD::UMUL_LOHI;
unsigned HiOp = Signed ? ISD::MULHS : ISD::MULHU;
+ EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VTSize * 2);
if (isOperationLegalOrCustom(LoHiOp, VT)) {
SDValue Result = DAG.getNode(LoHiOp, dl, DAG.getVTList(VT, VT), LHS, RHS);
Lo = Result.getValue(0);
@@ -10352,6 +10353,17 @@ TargetLowering::expandFixedPointMul(SDNode *Node, SelectionDAG &DAG) const {
} else if (isOperationLegalOrCustom(HiOp, VT)) {
Lo = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
Hi = DAG.getNode(HiOp, dl, VT, LHS, RHS);
+ } else if (isOperationLegalOrCustom(ISD::MUL, WideVT)) {
+ // Try for a multiplication using a wider type.
+ unsigned Ext = Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
+ SDValue LHSExt = DAG.getNode(Ext, dl, WideVT, LHS);
+ SDValue RHSExt = DAG.getNode(Ext, dl, WideVT, RHS);
+ SDValue Res = DAG.getNode(ISD::MUL, dl, WideVT, LHSExt, RHSExt);
+ Lo = DAG.getNode(ISD::TRUNCATE, dl, VT, Res);
+ SDValue Shifted =
+ DAG.getNode(ISD::SRA, dl, WideVT, Res,
+ DAG.getShiftAmountConstant(VTSize, WideVT, dl));
+ Hi = DAG.getNode(ISD::TRUNCATE, dl, VT, Shifted);
} else if (VT.isVector()) {
return SDValue();
} else {
diff --git a/llvm/test/CodeGen/AArch64/smul_fix.ll b/llvm/test/CodeGen/AArch64/smul_fix.ll
new file mode 100644
index 00000000000000..35faa3e5b8f931
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/smul_fix.ll
@@ -0,0 +1,93 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s
+
+declare i4 @llvm.smul.fix.i4 (i4, i4, i32)
+declare i32 @llvm.smul.fix.i32 (i32, i32, i32)
+declare i64 @llvm.smul.fix.i64 (i64, i64, i32)
+
+define i32 @func(i32 %x, i32 %y) nounwind {
+; CHECK-LABEL: func:
+; CHECK: // %bb.0:
+; CHECK-NEXT: smull x8, w0, w1
+; CHECK-NEXT: lsr x9, x8, #32
+; CHECK-NEXT: extr w0, w9, w8, #2
+; CHECK-NEXT: ret
+ %tmp = call i32 @llvm.smul.fix.i32(i32 %x, i32 %y, i32 2)
+ ret i32 %tmp
+}
+
+define i64 @func2(i64 %x, i64 %y) {
+; CHECK-LABEL: func2:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mul x8, x0, x1
+; CHECK-NEXT: smulh x9, x0, x1
+; CHECK-NEXT: extr x0, x9, x8, #2
+; CHECK-NEXT: ret
+ %tmp = call i64 @llvm.smul.fix.i64(i64 %x, i64 %y, i32 2)
+ ret i64 %tmp
+}
+
+define i4 @func3(i4 %x, i4 %y) nounwind {
+; CHECK-LABEL: func3:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sbfx w8, w1, #0, #4
+; CHECK-NEXT: sbfx w9, w0, #0, #4
+; CHECK-NEXT: smull x8, w9, w8
+; CHECK-NEXT: lsr x9, x8, #32
+; CHECK-NEXT: extr w0, w9, w8, #2
+; CHECK-NEXT: ret
+ %tmp = call i4 @llvm.smul.fix.i4(i4 %x, i4 %y, i32 2)
+ ret i4 %tmp
+}
+
+;; These result in regular integer multiplication
+define i32 @func4(i32 %x, i32 %y) nounwind {
+; CHECK-LABEL: func4:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mul w0, w0, w1
+; CHECK-NEXT: ret
+ %tmp = call i32 @llvm.smul.fix.i32(i32 %x, i32 %y, i32 0)
+ ret i32 %tmp
+}
+
+define i64 @func5(i64 %x, i64 %y) {
+; CHECK-LABEL: func5:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mul x0, x0, x1
+; CHECK-NEXT: ret
+ %tmp = call i64 @llvm.smul.fix.i64(i64 %x, i64 %y, i32 0)
+ ret i64 %tmp
+}
+
+define i4 @func6(i4 %x, i4 %y) nounwind {
+; CHECK-LABEL: func6:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sbfx w8, w1, #0, #4
+; CHECK-NEXT: sbfx w9, w0, #0, #4
+; CHECK-NEXT: mul w0, w9, w8
+; CHECK-NEXT: ret
+ %tmp = call i4 @llvm.smul.fix.i4(i4 %x, i4 %y, i32 0)
+ ret i4 %tmp
+}
+
+define i64 @func7(i64 %x, i64 %y) nounwind {
+; CHECK-LABEL: func7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mul x8, x0, x1
+; CHECK-NEXT: smulh x9, x0, x1
+; CHECK-NEXT: extr x0, x9, x8, #32
+; CHECK-NEXT: ret
+ %tmp = call i64 @llvm.smul.fix.i64(i64 %x, i64 %y, i32 32)
+ ret i64 %tmp
+}
+
+define i64 @func8(i64 %x, i64 %y) nounwind {
+; CHECK-LABEL: func8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mul x8, x0, x1
+; CHECK-NEXT: smulh x9, x0, x1
+; CHECK-NEXT: extr x0, x9, x8, #63
+; CHECK-NEXT: ret
+ %tmp = call i64 @llvm.smul.fix.i64(i64 %x, i64 %y, i32 63)
+ ret i64 %tmp
+}
diff --git a/llvm/test/CodeGen/AArch64/smul_fix_sat.ll b/llvm/test/CodeGen/AArch64/smul_fix_sat.ll
new file mode 100644
index 00000000000000..b78ae76aa4f645
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/smul_fix_sat.ll
@@ -0,0 +1,148 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s
+
+declare i4 @llvm.smul.fix.sat.i4 (i4, i4, i32)
+declare i32 @llvm.smul.fix.sat.i32 (i32, i32, i32)
+declare i64 @llvm.smul.fix.sat.i64 (i64, i64, i32)
+
+define i32 @func(i32 %x, i32 %y) nounwind {
+; CHECK-LABEL: func:
+; CHECK: // %bb.0:
+; CHECK-NEXT: smull x9, w0, w1
+; CHECK-NEXT: mov w8, #2147483647 // =0x7fffffff
+; CHECK-NEXT: lsr x10, x9, #32
+; CHECK-NEXT: extr w9, w10, w9, #2
+; CHECK-NEXT: cmp w10, #1
+; CHECK-NEXT: csel w8, w8, w9, gt
+; CHECK-NEXT: cmn w10, #2
+; CHECK-NEXT: mov w9, #-2147483648 // =0x80000000
+; CHECK-NEXT: csel w0, w9, w8, lt
+; CHECK-NEXT: ret
+ %tmp = call i32 @llvm.smul.fix.sat.i32(i32 %x, i32 %y, i32 2)
+ ret i32 %tmp
+}
+
+define i64 @func2(i64 %x, i64 %y) nounwind {
+; CHECK-LABEL: func2:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mul x9, x0, x1
+; CHECK-NEXT: mov x8, #9223372036854775807 // =0x7fffffffffffffff
+; CHECK-NEXT: smulh x10, x0, x1
+; CHECK-NEXT: extr x9, x10, x9, #2
+; CHECK-NEXT: cmp x10, #1
+; CHECK-NEXT: csel x8, x8, x9, gt
+; CHECK-NEXT: cmn x10, #2
+; CHECK-NEXT: mov x9, #-9223372036854775808 // =0x8000000000000000
+; CHECK-NEXT: csel x0, x9, x8, lt
+; CHECK-NEXT: ret
+ %tmp = call i64 @llvm.smul.fix.sat.i64(i64 %x, i64 %y, i32 2)
+ ret i64 %tmp
+}
+
+define i4 @func3(i4 %x, i4 %y) nounwind {
+; CHECK-LABEL: func3:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sbfx w9, w1, #0, #4
+; CHECK-NEXT: lsl w10, w0, #28
+; CHECK-NEXT: mov w8, #2147483647 // =0x7fffffff
+; CHECK-NEXT: smull x9, w10, w9
+; CHECK-NEXT: lsr x10, x9, #32
+; CHECK-NEXT: extr w9, w10, w9, #2
+; CHECK-NEXT: cmp w10, #1
+; CHECK-NEXT: csel w8, w8, w9, gt
+; CHECK-NEXT: cmn w10, #2
+; CHECK-NEXT: mov w9, #-2147483648 // =0x80000000
+; CHECK-NEXT: csel w8, w9, w8, lt
+; CHECK-NEXT: asr w0, w8, #28
+; CHECK-NEXT: ret
+ %tmp = call i4 @llvm.smul.fix.sat.i4(i4 %x, i4 %y, i32 2)
+ ret i4 %tmp
+}
+
+;; These result in regular integer multiplication with a saturation check.
+define i32 @func4(i32 %x, i32 %y) nounwind {
+; CHECK-LABEL: func4:
+; CHECK: // %bb.0:
+; CHECK-NEXT: smull x9, w0, w1
+; CHECK-NEXT: eor w10, w0, w1
+; CHECK-NEXT: mov w8, #-2147483648 // =0x80000000
+; CHECK-NEXT: cmp w10, #0
+; CHECK-NEXT: cinv w8, w8, ge
+; CHECK-NEXT: cmp x9, w9, sxtw
+; CHECK-NEXT: csel w0, w8, w9, ne
+; CHECK-NEXT: ret
+ %tmp = call i32 @llvm.smul.fix.sat.i32(i32 %x, i32 %y, i32 0)
+ ret i32 %tmp
+}
+
+define i64 @func5(i64 %x, i64 %y) {
+; CHECK-LABEL: func5:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mul x9, x0, x1
+; CHECK-NEXT: eor x11, x0, x1
+; CHECK-NEXT: mov x8, #-9223372036854775808 // =0x8000000000000000
+; CHECK-NEXT: cmp x11, #0
+; CHECK-NEXT: smulh x10, x0, x1
+; CHECK-NEXT: cinv x8, x8, ge
+; CHECK-NEXT: cmp x10, x9, asr #63
+; CHECK-NEXT: csel x0, x8, x9, ne
+; CHECK-NEXT: ret
+ %tmp = call i64 @llvm.smul.fix.sat.i64(i64 %x, i64 %y, i32 0)
+ ret i64 %tmp
+}
+
+define i4 @func6(i4 %x, i4 %y) nounwind {
+; CHECK-LABEL: func6:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sbfx w9, w1, #0, #4
+; CHECK-NEXT: lsl w10, w0, #28
+; CHECK-NEXT: mov w8, #-2147483648 // =0x80000000
+; CHECK-NEXT: smull x11, w10, w9
+; CHECK-NEXT: eor w9, w10, w9
+; CHECK-NEXT: cmp w9, #0
+; CHECK-NEXT: cinv w8, w8, ge
+; CHECK-NEXT: cmp x11, w11, sxtw
+; CHECK-NEXT: csel w8, w8, w11, ne
+; CHECK-NEXT: asr w0, w8, #28
+; CHECK-NEXT: ret
+ %tmp = call i4 @llvm.smul.fix.sat.i4(i4 %x, i4 %y, i32 0)
+ ret i4 %tmp
+}
+
+define i64 @func7(i64 %x, i64 %y) nounwind {
+; CHECK-LABEL: func7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mul x9, x0, x1
+; CHECK-NEXT: mov w8, #2147483647 // =0x7fffffff
+; CHECK-NEXT: mov x11, #-2147483648 // =0xffffffff80000000
+; CHECK-NEXT: smulh x10, x0, x1
+; CHECK-NEXT: extr x9, x10, x9, #32
+; CHECK-NEXT: cmp x10, x8
+; CHECK-NEXT: mov x8, #9223372036854775807 // =0x7fffffffffffffff
+; CHECK-NEXT: csel x8, x8, x9, gt
+; CHECK-NEXT: cmp x10, x11
+; CHECK-NEXT: mov x9, #-9223372036854775808 // =0x8000000000000000
+; CHECK-NEXT: csel x0, x9, x8, lt
+; CHECK-NEXT: ret
+ %tmp = call i64 @llvm.smul.fix.sat.i64(i64 %x, i64 %y, i32 32)
+ ret i64 %tmp
+}
+
+define i64 @func8(i64 %x, i64 %y) nounwind {
+; CHECK-LABEL: func8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mul x9, x0, x1
+; CHECK-NEXT: mov x8, #4611686018427387903 // =0x3fffffffffffffff
+; CHECK-NEXT: mov x11, #-4611686018427387904 // =0xc000000000000000
+; CHECK-NEXT: smulh x10, x0, x1
+; CHECK-NEXT: extr x9, x10, x9, #63
+; CHECK-NEXT: cmp x10, x8
+; CHECK-NEXT: mov x8, #9223372036854775807 // =0x7fffffffffffffff
+; CHECK-NEXT: csel x8, x8, x9, gt
+; CHECK-NEXT: cmp x10, x11
+; CHECK-NEXT: mov x9, #-9223372036854775808 // =0x8000000000000000
+; CHECK-NEXT: csel x0, x9, x8, lt
+; CHECK-NEXT: ret
+ %tmp = call i64 @llvm.smul.fix.sat.i64(i64 %x, i64 %y, i32 63)
+ ret i64 %tmp
+}
diff --git a/llvm/test/CodeGen/AArch64/umul_fix.ll b/llvm/test/CodeGen/AArch64/umul_fix.ll
new file mode 100644
index 00000000000000..ed887af1ed6986
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/umul_fix.ll
@@ -0,0 +1,101 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s
+
+declare i4 @llvm.umul.fix.i4 (i4, i4, i32)
+declare i32 @llvm.umul.fix.i32 (i32, i32, i32)
+declare i64 @llvm.umul.fix.i64 (i64, i64, i32)
+
+define i32 @func(i32 %x, i32 %y) nounwind {
+; CHECK-LABEL: func:
+; CHECK: // %bb.0:
+; CHECK-NEXT: umull x8, w0, w1
+; CHECK-NEXT: lsr x9, x8, #32
+; CHECK-NEXT: extr w0, w9, w8, #2
+; CHECK-NEXT: ret
+ %tmp = call i32 @llvm.umul.fix.i32(i32 %x, i32 %y, i32 2)
+ ret i32 %tmp
+}
+
+define i64 @func2(i64 %x, i64 %y) nounwind {
+; CHECK-LABEL: func2:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mul x8, x0, x1
+; CHECK-NEXT: umulh x9, x0, x1
+; CHECK-NEXT: extr x0, x9, x8, #2
+; CHECK-NEXT: ret
+ %tmp = call i64 @llvm.umul.fix.i64(i64 %x, i64 %y, i32 2)
+ ret i64 %tmp
+}
+
+define i4 @func3(i4 %x, i4 %y) nounwind {
+; CHECK-LABEL: func3:
+; CHECK: // %bb.0:
+; CHECK-NEXT: and w8, w1, #0xf
+; CHECK-NEXT: and w9, w0, #0xf
+; CHECK-NEXT: mul w8, w9, w8
+; CHECK-NEXT: lsr w0, w8, #2
+; CHECK-NEXT: ret
+ %tmp = call i4 @llvm.umul.fix.i4(i4 %x, i4 %y, i32 2)
+ ret i4 %tmp
+}
+
+;; These result in regular integer multiplication
+define i32 @func4(i32 %x, i32 %y) nounwind {
+; CHECK-LABEL: func4:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mul w0, w0, w1
+; CHECK-NEXT: ret
+ %tmp = call i32 @llvm.umul.fix.i32(i32 %x, i32 %y, i32 0)
+ ret i32 %tmp
+}
+
+define i64 @func5(i64 %x, i64 %y) nounwind {
+; CHECK-LABEL: func5:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mul x0, x0, x1
+; CHECK-NEXT: ret
+ %tmp = call i64 @llvm.umul.fix.i64(i64 %x, i64 %y, i32 0)
+ ret i64 %tmp
+}
+
+define i4 @func6(i4 %x, i4 %y) nounwind {
+; CHECK-LABEL: func6:
+; CHECK: // %bb.0:
+; CHECK-NEXT: and w8, w1, #0xf
+; CHECK-NEXT: and w9, w0, #0xf
+; CHECK-NEXT: mul w0, w9, w8
+; CHECK-NEXT: ret
+ %tmp = call i4 @llvm.umul.fix.i4(i4 %x, i4 %y, i32 0)
+ ret i4 %tmp
+}
+
+define i64 @func7(i64 %x, i64 %y) nounwind {
+; CHECK-LABEL: func7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mul x8, x0, x1
+; CHECK-NEXT: umulh x9, x0, x1
+; CHECK-NEXT: extr x0, x9, x8, #32
+; CHECK-NEXT: ret
+ %tmp = call i64 @llvm.umul.fix.i64(i64 %x, i64 %y, i32 32)
+ ret i64 %tmp
+}
+
+define i64 @func8(i64 %x, i64 %y) nounwind {
+; CHECK-LABEL: func8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mul x8, x0, x1
+; CHECK-NEXT: umulh x9, x0, x1
+; CHECK-NEXT: extr x0, x9, x8, #63
+; CHECK-NEXT: ret
+ %tmp = call i64 @llvm.umul.fix.i64(i64 %x, i64 %y, i32 63)
+ ret i64 %tmp
+}
+
+define i64 @func9(i64 %x, i64 %y) nounwind {
+; CHECK-LABEL: func9:
+; CHECK: // %bb.0:
+; CHECK-NEXT: umulh x0, x0, x1
+; CHECK-NEXT: ret
+ %tmp = call i64 @llvm.umul.fix.i64(i64 %x, i64 %y, i32 64)
+ ret i64 %tmp
+}
diff --git a/llvm/test/CodeGen/AArch64/umul_fix_sat.ll b/llvm/test/CodeGen/AArch64/umul_fix_sat.ll
new file mode 100644
index 00000000000000..c81618203afad8
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/umul_fix_sat.ll
@@ -0,0 +1,146 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s
+
+declare i4 @llvm.umul.fix.sat.i4 (i4, i4, i32)
+declare i32 @llvm.umul.fix.sat.i32 (i32, i32, i32)
+declare i64 @llvm.umul.fix.sat.i64 (i64, i64, i32)
+
+define i32 @func(i32 %x, i32 %y) nounwind {
+; CHECK-LABEL: func:
+; CHECK: // %bb.0:
+; CHECK-NEXT: umull x8, w0, w1
+; CHECK-NEXT: lsr x9, x8, #32
+; CHECK-NEXT: extr w8, w9, w8, #2
+; CHECK-NEXT: cmp w9, #3
+; CHECK-NEXT: csinv w0, w8, wzr, ls
+; CHECK-NEXT: ret
+ %tmp = call i32 @llvm.umul.fix.sat.i32(i32 %x, i32 %y, i32 2)
+ ret i32 %tmp
+}
+
+define i64 @func2(i64 %x, i64 %y) nounwind {
+; CHECK-LABEL: func2:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mul x8, x0, x1
+; CHECK-NEXT: umulh x9, x0, x1
+; CHECK-NEXT: extr x8, x9, x8, #2
+; CHECK-NEXT: cmp x9, #3
+; CHECK-NEXT: csinv x0, x8, xzr, ls
+; CHECK-NEXT: ret
+ %tmp = call i64 @llvm.umul.fix.sat.i64(i64 %x, i64 %y, i32 2)
+ ret i64 %tmp
+}
+
+define i4 @func3(i4 %x, i4 %y) nounwind {
+; CHECK-LABEL: func3:
+; CHECK: // %bb.0:
+; CHECK-NEXT: lsl w8, w0, #28
+; CHECK-NEXT: and w9, w1, #0xf
+; CHECK-NEXT: umull x8, w8, w9
+; CHECK-NEXT: lsr x9, x8, #32
+; CHECK-NEXT: extr w8, w9, w8, #2
+; CHECK-NEXT: cmp w9, #3
+; CHECK-NEXT: csinv w8, w8, wzr, ls
+; CHECK-NEXT: lsr w0, w8, #28
+; CHECK-NEXT: ret
+ %tmp = call i4 @llvm.umul.fix.sat.i4(i4 %x, i4 %y, i32 2)
+ ret i4 %tmp
+}
+
+;; These result in regular integer multiplication with a saturation check.
+define i32 @func4(i32 %x, i32 %y) nounwind {
+; CHECK-LABEL: func4:
+; CHECK: // %bb.0:
+; CHECK-NEXT: umull x8, w0, w1
+; CHECK-NEXT: tst x8, #0xffffffff00000000
+; CHECK-NEXT: csinv w0, w8, wzr, eq
+; CHECK-NEXT: ret
+ %tmp = call i32 @llvm.umul.fix.sat.i32(i32 %x, i32 %y, i32 0)
+ ret i32 %tmp
+}
+
+define i64 @func5(i64 %x, i64 %y) {
+; CHECK-LABEL: func5:
+; CHECK: // %bb.0:
+; CHECK-NEXT: umulh x8, x0, x1
+; CHECK-NEXT: mul x9, x0, x1
+; CHECK-NEXT: cmp xzr, x8
+; CHECK-NEXT: csinv x0, x9, xzr, eq
+; CHECK-NEXT: ret
+ %tmp = call i64 @llvm.umul.fix.sat.i64(i64 %x, i64 %y, i32 0)
+ ret i64 %tmp
+}
+
+define i4 @func6(i4 %x, i4 %y) nounwind {
+; CHECK-LABEL: func6:
+; CHECK: // %bb.0:
+; CHECK-NEXT: lsl w8, w0, #28
+; CHECK-NEXT: and w9, w1, #0xf
+; CHECK-NEXT: umull x8, w8, w9
+; CHECK-NEXT: tst x8, #0xffffffff00000000
+; CHECK-NEXT: csinv w8, w8, wzr, eq
+; CHECK-NEXT: lsr w0, w8, #28
+; CHECK-NEXT: ret
+ %tmp = call i4 @llvm.umul.fix.sat.i4(i4 %x, i4 %y, i32 0)
+ ret i4 %tmp
+}
+
+define <4 x i32> @vec2(<4 x i32> %x, <4 x i32> %y) nounwind {
+; CHECK-LABEL: vec2:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, v1.s[1]
+; CHECK-NEXT: mov w9, v0.s[1]
+; CHECK-NEXT: fmov w10, s0
+; CHECK-NEXT: mov w11, v0.s[2]
+; CHECK-NEXT: mov w13, v0.s[3]
+; CHECK-NEXT: mov w12, v1.s[3]
+; CHECK-NEXT: umull x8, w9, w8
+; CHECK-NEXT: fmov w9, s1
+; CHECK-NEXT: umull x9, w10, w9
+; CHECK-NEXT: tst x8, #0xffffffff00000000
+; CHECK-NEXT: mov w10, v1.s[2]
+; CHECK-NEXT: csinv w8, w8, wzr, eq
+; CHECK-NEXT: tst x9, #0xffffffff00000000
+; CHECK-NEXT: csinv w9, w9, wzr, eq
+; CHECK-NEXT: fmov s0, w9
+; CHECK-NEXT: umull x9, w11, w10
+; CHECK-NEXT: mov v0.s[1], w8
+; CHECK-NEXT: tst x9, #0xffffffff00000000
+; CHECK-NEXT: csinv w8, w9, wzr, eq
+; CHECK-NEXT: umull x9, w13, w12
+; CHECK-NEXT: mov v0.s[2], w8
+; CHECK-NEXT: tst x9, #0xffffffff00000000
+; CHECK-NEXT: csinv w8, w9, wzr, eq
+; CHECK-NEXT: mov v0.s[3], w8
+; CHECK-NEXT: ret
+ %tmp = call <4 x i32> @llvm.umul.fix.sat.v4i32(<4 x i32> %x, <4 x i32> %y, i32 0)
+ ret <4 x i32> %tmp
+}
+
+define i64 @func7(i64 %x, i64 %y) nounwind {
+; CHECK-LABEL: func7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mul x9, x0, x1
+; CHECK-NEXT: mov w8, #-1 // =0xffffffff
+; CHECK-NEXT: umulh x10, x0, x1
+; CHECK-NEXT: extr x9, x10, x9, #32
+; CHECK-NEXT: cmp x10, x8
+; CHECK-NEXT: csinv x0, x9, xzr, ls
+; CHECK-NEXT: ret
+ %tmp = call i64 @llvm.umul.fix.sat.i64(i64 %x, i64 %y, i32 32)
+ ret i64 %tmp
+}
+
+define i64 @func8(i64 %x, i64 %y) nounwind {
+; CHECK-LABEL: func8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mul x9, x0, x1
+; CHECK-NEXT: mov x8, #9223372036854775807 // =0x7fffffffffffffff
+; CHECK-NEXT: umulh x10, x0, x1
+; CHECK-NEXT: extr x9, x10, x9, #63
+; CHECK-NEXT: cmp x10, x8
+; CHECK-NEXT: csinv x0, x9, xzr, ls
+; CHECK-NEXT: ret
+ %tmp = call i64 @llvm.umul.fix.sat.i64(i64 %x, i64 %y, i32 63)
+ ret i64 %tmp
+}
``````````
</details>
https://github.com/llvm/llvm-project/pull/84237
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