[llvm] [ARM][TableGen][MC] Change the ARM mnemonic operands to be optional for ASM parsing (PR #83436)

[Sergei Barannikov via llvm-commits]

================
@@ -12811,11 +12930,24 @@ unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
     if (hasV8Ops() && Op.isReg() && Op.getReg() == ARM::SP)
       return Match_Success;
     return Match_rGPR;
-  case MCK_GPRPair:
-    if (Op.isReg() &&
-        MRI->getRegClass(ARM::GPRRegClassID).contains(Op.getReg()))
+  // If trying to match a VecListDPair with a Q register, convert Q to list
+  case MCK_VecListDPair:
+    if (Op.isQReg() && !hasMVE()) {
+      auto DPair = getDRegFromQReg(Op.getReg());
+      DPair = MRI->getMatchingSuperReg(
+          DPair, ARM::dsub_0, &ARMMCRegisterClasses[ARM::DPairRegClassID]);
+      Op.setVecListDPair(DPair);
----------------
s-barannikov wrote:

> The functions needed for this conversion comes from the MCRegisterInfo object MRI which is a member of the ARMAsmParser class. This isn't available for at ARMOperand::addXXXOperand so this is quite challenging. 

This is a known issue, and you correctly guessed one way to overcome it. It would be better if addXXXOperand methods were members of AsmParser instance, where everything that is needed is available, but they are not, and it is difficult to change now.

> do you think it is wrong if this stays here or is it a matter of preference?

I guess it can stay here, but "mutate it at your own risc". Once the operand is mutated, it can no longer be matched as non-mutated.


https://github.com/llvm/llvm-project/pull/83436