[llvm] be3eeea - [AArch64] Use SHLLv4i16 to shift+widen BF16 to F32.

[David Majnemer via llvm-commits]

Author: David Majnemer
Date: 2024-03-04T20:43:08Z
New Revision: be3eeea7beb7dc701554a67773669c91367e7a81

URL: https://github.com/llvm/llvm-project/commit/be3eeea7beb7dc701554a67773669c91367e7a81
DIFF: https://github.com/llvm/llvm-project/commit/be3eeea7beb7dc701554a67773669c91367e7a81.diff

LOG: [AArch64] Use SHLLv4i16 to shift+widen BF16 to F32.

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64InstrInfo.td

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 2f3aaf86d376f6..f8c6d9019ef6e1 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -7730,8 +7730,7 @@ def : Pat<(v2i64 (sext   (v2i32 V64:$Rn))), (SSHLLv2i32_shift V64:$Rn, (i32 0))>
 def : Pat<(v2i64 (zext   (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
 def : Pat<(v2i64 (anyext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
 // Vector bf16 -> fp32 is implemented morally as a zext + shift.
-def : Pat<(v4f32 (any_fpextend (v4bf16 V64:$Rn))),
-          (USHLLv4i16_shift V64:$Rn, (i32 16))>;
+def : Pat<(v4f32 (any_fpextend (v4bf16 V64:$Rn))), (SHLLv4i16 V64:$Rn)>;
 // Also match an extend from the upper half of a 128 bit source register.
 def : Pat<(v8i16 (anyext (v8i8 (extract_high_v16i8 (v16i8 V128:$Rn)) ))),
           (USHLLv16i8_shift V128:$Rn, (i32 0))>;