[llvm] [AArch64][GlobalISel] Legalize Insert vector element (PR #81453)

[David Green via llvm-commits]

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@@ -2121,6 +2120,36 @@ bool AArch64InstructionSelector::preISelLower(MachineInstr &I) {
     }
     return false;
   }
+  case TargetOpcode::G_INSERT_VECTOR_ELT: {
+    // The tablegen patterns for integer insert_vector_elts with small elements
+    // will expect the operand to be legalized to a i32 type. This extends the
+    // types of i8 and i16 element inserts, so that the existing tablegen
+    // patterns can apply.
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davemgreen wrote:

If it can avoid this manual selection of the ANYEXT then it sounds good. There didn't seem to be anything already like it in AArch64, but I've added something for it. Thanks.

https://github.com/llvm/llvm-project/pull/81453