[llvm] [LTO] Set default Darwin CPU to apple-a7 for AArch64 (PR #81540)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 23 21:14:13 PST 2024
https://github.com/AtariDreams updated https://github.com/llvm/llvm-project/pull/81540
>From 96ff9e5ae3f906306cdcd7ab7e3857d393803dc7 Mon Sep 17 00:00:00 2001
From: Rose <83477269+AtariDreams at users.noreply.github.com>
Date: Mon, 12 Feb 2024 16:31:12 -0500
Subject: [PATCH] [LTO] Set default Darwin CPU to apple-a7 for AArch64
Use apple-a7 as default for AArch64 Darwin targets that are not arm64e, as apple-a7 is the first AArch64 CPU that can run Darwin.
---
llvm/include/llvm/TargetParser/ARMTargetParser.def | 2 +-
llvm/lib/LTO/LTOCodeGenerator.cpp | 2 +-
llvm/lib/LTO/LTOModule.cpp | 2 +-
llvm/lib/LTO/ThinLTOCodeGenerator.cpp | 2 +-
llvm/lib/Object/MachOObjectFile.cpp | 4 ++--
llvm/lib/Target/ARM/ARM.td | 2 +-
llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir | 2 +-
llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir | 2 +-
llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir | 2 +-
llvm/test/CodeGen/AArch64/arm64-collect-loh.ll | 2 +-
llvm/test/CodeGen/AArch64/arm64-vecCmpBr.ll | 4 ++--
llvm/test/CodeGen/AArch64/machine-outliner-remarks.ll | 2 +-
llvm/test/CodeGen/AArch64/machine-outliner.ll | 4 ++--
llvm/test/CodeGen/AArch64/print-mrs-system-register.ll | 2 +-
llvm/test/CodeGen/ARM/print-memb-operand.ll | 2 +-
15 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/llvm/include/llvm/TargetParser/ARMTargetParser.def b/llvm/include/llvm/TargetParser/ARMTargetParser.def
index 1797a1b238d349..6c7c974e2c27d7 100644
--- a/llvm/include/llvm/TargetParser/ARMTargetParser.def
+++ b/llvm/include/llvm/TargetParser/ARMTargetParser.def
@@ -350,7 +350,7 @@ ARM_CPU_NAME("neoverse-n2", ARMV9A, FK_NEON_FP_ARMV8, false,
ARM::AEK_SB))
ARM_CPU_NAME("neoverse-v1", ARMV8_4A, FK_CRYPTO_NEON_FP_ARMV8, false,
(ARM::AEK_RAS | ARM::AEK_FP16 | ARM::AEK_BF16 | ARM::AEK_DOTPROD))
-ARM_CPU_NAME("cyclone", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
+ARM_CPU_NAME("apple-a7", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
ARM_CPU_NAME("exynos-m3", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
ARM_CPU_NAME("exynos-m4", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
(ARM::AEK_FP16 | ARM::AEK_DOTPROD))
diff --git a/llvm/lib/LTO/LTOCodeGenerator.cpp b/llvm/lib/LTO/LTOCodeGenerator.cpp
index 52d8fff14be9ce..a31e07eaf952bb 100644
--- a/llvm/lib/LTO/LTOCodeGenerator.cpp
+++ b/llvm/lib/LTO/LTOCodeGenerator.cpp
@@ -419,7 +419,7 @@ bool LTOCodeGenerator::determineTarget() {
Config.CPU = "apple-a12";
else if (Triple.getArch() == llvm::Triple::aarch64 ||
Triple.getArch() == llvm::Triple::aarch64_32)
- Config.CPU = "cyclone";
+ Config.CPU = "apple-a7";
}
// If data-sections is not explicitly set or unset, set data-sections by
diff --git a/llvm/lib/LTO/LTOModule.cpp b/llvm/lib/LTO/LTOModule.cpp
index f839fe944e18f7..7f92ef1b9621e6 100644
--- a/llvm/lib/LTO/LTOModule.cpp
+++ b/llvm/lib/LTO/LTOModule.cpp
@@ -226,7 +226,7 @@ LTOModule::makeLTOModule(MemoryBufferRef Buffer, const TargetOptions &options,
CPU = "apple-a12";
else if (Triple.getArch() == llvm::Triple::aarch64 ||
Triple.getArch() == llvm::Triple::aarch64_32)
- CPU = "cyclone";
+ CPU = "apple-a7";
}
TargetMachine *target = march->createTargetMachine(TripleStr, CPU, FeatureStr,
diff --git a/llvm/lib/LTO/ThinLTOCodeGenerator.cpp b/llvm/lib/LTO/ThinLTOCodeGenerator.cpp
index 535faf5f780474..201a7877329b39 100644
--- a/llvm/lib/LTO/ThinLTOCodeGenerator.cpp
+++ b/llvm/lib/LTO/ThinLTOCodeGenerator.cpp
@@ -548,7 +548,7 @@ static void initTMBuilder(TargetMachineBuilder &TMBuilder,
TMBuilder.MCpu = "yonah";
else if (TheTriple.getArch() == llvm::Triple::aarch64 ||
TheTriple.getArch() == llvm::Triple::aarch64_32)
- TMBuilder.MCpu = "cyclone";
+ TMBuilder.MCpu = "apple-a7";
}
TMBuilder.TheTriple = std::move(TheTriple);
}
diff --git a/llvm/lib/Object/MachOObjectFile.cpp b/llvm/lib/Object/MachOObjectFile.cpp
index 1cfd0a069463e9..599bc75f91afd4 100644
--- a/llvm/lib/Object/MachOObjectFile.cpp
+++ b/llvm/lib/Object/MachOObjectFile.cpp
@@ -2797,7 +2797,7 @@ Triple MachOObjectFile::getArchTriple(uint32_t CPUType, uint32_t CPUSubType,
switch (CPUSubType & ~MachO::CPU_SUBTYPE_MASK) {
case MachO::CPU_SUBTYPE_ARM64_ALL:
if (McpuDefault)
- *McpuDefault = "cyclone";
+ *McpuDefault = "apple-a7";
if (ArchFlag)
*ArchFlag = "arm64";
return Triple("arm64-apple-darwin");
@@ -2814,7 +2814,7 @@ Triple MachOObjectFile::getArchTriple(uint32_t CPUType, uint32_t CPUSubType,
switch (CPUSubType & ~MachO::CPU_SUBTYPE_MASK) {
case MachO::CPU_SUBTYPE_ARM64_32_V8:
if (McpuDefault)
- *McpuDefault = "cyclone";
+ *McpuDefault = "apple-a7";
if (ArchFlag)
*ArchFlag = "arm64_32";
return Triple("arm64_32-apple-darwin");
diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td
index 877781568307dc..a4d9485b3dee7d 100644
--- a/llvm/lib/Target/ARM/ARM.td
+++ b/llvm/lib/Target/ARM/ARM.td
@@ -1684,7 +1684,7 @@ def : ProcNoItin<"neoverse-n2", [ARMv9a,
FeatureBF16,
FeatureMatMulInt8]>;
-def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift,
+def : ProcessorModel<"apple-a7", SwiftModel, [ARMv8a, ProcSwift,
FeatureHasRetAddrStack,
FeatureNEONForFP,
FeatureVFP4,
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir
index 0a22c7d1f94bb0..43025f9abf2fa4 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir
@@ -56,7 +56,7 @@
}
- attributes #0 = { nounwind ssp uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "frame-pointer"="all" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="cyclone" "target-features"="+aes,+crypto,+fp-armv8,+neon,+sha2,+zcm,+zcz" "unsafe-fp-math"="false" "use-soft-float"="false" }
+ attributes #0 = { nounwind ssp uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "frame-pointer"="all" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="apple-a7" "target-features"="+aes,+crypto,+fp-armv8,+neon,+sha2,+zcm,+zcz" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { argmemonly nounwind }
attributes #2 = { optsize }
attributes #3 = { minsize }
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir
index f31b64ece89572..b6f73f3eb8d5b5 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir
@@ -47,7 +47,7 @@
ret void
}
- attributes #0 = { nounwind ssp uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "frame-pointer"="all" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="cyclone" "target-features"="+aes,+crypto,+fp-armv8,+neon,+sha2,+zcm,+zcz" "unsafe-fp-math"="false" "use-soft-float"="false" }
+ attributes #0 = { nounwind ssp uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "frame-pointer"="all" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="apple-a7" "target-features"="+aes,+crypto,+fp-armv8,+neon,+sha2,+zcm,+zcz" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { argmemonly nounwind }
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir
index 00c7fc4cab3ab0..e05f8ef87464fd 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir
@@ -50,7 +50,7 @@
declare void @llvm.stackprotector(ptr, ptr) #2
- attributes #0 = { nounwind ssp uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "frame-pointer"="all" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="cyclone" "target-features"="+aes,+crypto,+fp-armv8,+neon,+sha2,+zcm,+zcz" "unsafe-fp-math"="false" "use-soft-float"="false" }
+ attributes #0 = { nounwind ssp uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "frame-pointer"="all" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="apple-a7" "target-features"="+aes,+crypto,+fp-armv8,+neon,+sha2,+zcm,+zcz" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { argmemonly nounwind }
...
diff --git a/llvm/test/CodeGen/AArch64/arm64-collect-loh.ll b/llvm/test/CodeGen/AArch64/arm64-collect-loh.ll
index 1b9db8b70a1fb4..e1cd3c74c42529 100644
--- a/llvm/test/CodeGen/AArch64/arm64-collect-loh.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-collect-loh.ll
@@ -680,4 +680,4 @@ if.end.i:
}
declare void @callee(ptr nocapture readonly, ...)
-attributes #0 = { "target-cpu"="cyclone" }
+attributes #0 = { "target-cpu"="apple-a7" }
diff --git a/llvm/test/CodeGen/AArch64/arm64-vecCmpBr.ll b/llvm/test/CodeGen/AArch64/arm64-vecCmpBr.ll
index 37d2085c495a22..4d64c461326b63 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vecCmpBr.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vecCmpBr.ll
@@ -199,8 +199,8 @@ declare i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8>) #2
declare i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8>) #2
-attributes #0 = { nounwind ssp "target-cpu"="cyclone" }
-attributes #1 = { "target-cpu"="cyclone" }
+attributes #0 = { nounwind ssp "target-cpu"="apple-a7" }
+attributes #1 = { "target-cpu"="apple-a7" }
attributes #2 = { nounwind readnone }
attributes #3 = { nounwind }
attributes #4 = { nobuiltin nounwind }
diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-remarks.ll b/llvm/test/CodeGen/AArch64/machine-outliner-remarks.ll
index a9fc850ecd816a..72a380b1180471 100644
--- a/llvm/test/CodeGen/AArch64/machine-outliner-remarks.ll
+++ b/llvm/test/CodeGen/AArch64/machine-outliner-remarks.ll
@@ -102,7 +102,7 @@ define void @bar() #0 !dbg !27 {
ret void
}
-attributes #0 = { noredzone nounwind ssp uwtable minsize "frame-pointer"="none" "target-cpu"="cyclone" }
+attributes #0 = { noredzone nounwind ssp uwtable minsize "frame-pointer"="none" "target-cpu"="apple-a7" }
!llvm.dbg.cu = !{!0}
!llvm.module.flags = !{!3, !4, !5, !6}
diff --git a/llvm/test/CodeGen/AArch64/machine-outliner.ll b/llvm/test/CodeGen/AArch64/machine-outliner.ll
index e6c5c94b00b556..6ccb3074aadf34 100644
--- a/llvm/test/CodeGen/AArch64/machine-outliner.ll
+++ b/llvm/test/CodeGen/AArch64/machine-outliner.ll
@@ -11,7 +11,7 @@
; TARGET_FEATURES-SAME: minsize
; TARGET_FEATURES-SAME: nounwind
; TARGET_FEATURES-SAME: optsize
-; TARGET_FEATURES-SAME: "target-cpu"="cyclone"
+; TARGET_FEATURES-SAME: "target-cpu"="apple-a7"
; TARGET_FEATURES-SAME: "target-features"="+sse"
define linkonce_odr void @fish() #0 {
@@ -105,4 +105,4 @@ define void @dog() #0 {
; CHECK-DAG: add sp, sp, #32
; CHECK-DAG: ret
-attributes #0 = { nounwind noredzone "target-cpu"="cyclone" "target-features"="+sse" }
+attributes #0 = { nounwind noredzone "target-cpu"="apple-a7" "target-features"="+sse" }
diff --git a/llvm/test/CodeGen/AArch64/print-mrs-system-register.ll b/llvm/test/CodeGen/AArch64/print-mrs-system-register.ll
index 3411ed6161bdbd..1a8af34aa3c11d 100644
--- a/llvm/test/CodeGen/AArch64/print-mrs-system-register.ll
+++ b/llvm/test/CodeGen/AArch64/print-mrs-system-register.ll
@@ -8,4 +8,4 @@ entry:
ret void
}
-attributes #0 = { "target-cpu"="cyclone" }
+attributes #0 = { "target-cpu"="apple-a7" }
diff --git a/llvm/test/CodeGen/ARM/print-memb-operand.ll b/llvm/test/CodeGen/ARM/print-memb-operand.ll
index 7748efb3a08aba..517112ee119992 100644
--- a/llvm/test/CodeGen/ARM/print-memb-operand.ll
+++ b/llvm/test/CodeGen/ARM/print-memb-operand.ll
@@ -9,4 +9,4 @@ define void @test2() #0 {
declare void @llvm.arm.dmb(i32)
-attributes #0 = { "target-cpu"="cyclone" }
+attributes #0 = { "target-cpu"="apple-a7" }
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