[llvm] [X86] Resolve FIXME: Add FPCW as a rounding control register (PR #82452)

[via llvm-commits]

https://github.com/AtariDreams updated https://github.com/llvm/llvm-project/pull/82452

>From 9b94d86190d1fdb288955dedf59987a2ed32f876 Mon Sep 17 00:00:00 2001
From: Rose <83477269+AtariDreams at users.noreply.github.com>
Date: Wed, 21 Feb 2024 14:53:23 -0500
Subject: [PATCH 1/2] [X86] Insert wait if instruction right before call is a
 waiting one

The reason adding fpcr broke tests is because that caused LLVM to no longer kill the instruction before a call, which prevented LLVM from treating x87 as an operand, which meant the call was not eligible for a wait before it as a result.

This patch now has LLVM add wait to the end of a x87 instruction is a call is immediately after.
---
 llvm/lib/Target/X86/X86InsertWait.cpp | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/X86/X86InsertWait.cpp b/llvm/lib/Target/X86/X86InsertWait.cpp
index 69a3d32a931498..10f141abe9c786 100644
--- a/llvm/lib/Target/X86/X86InsertWait.cpp
+++ b/llvm/lib/Target/X86/X86InsertWait.cpp
@@ -115,7 +115,8 @@ bool WaitInsert::runOnMachineFunction(MachineFunction &MF) {
       // If the following instruction is an X87 instruction and isn't an X87
       // non-waiting control instruction, we can omit insert wait instruction.
       MachineBasicBlock::iterator AfterMI = std::next(MI);
-      if (AfterMI != MBB.end() && X86::isX87Instruction(*AfterMI) &&
+      if (AfterMI != MBB.end() && !AfterMI->isCall() &&
+          X86::isX87Instruction(*AfterMI) &&
           !isX87NonWaitingControlInstruction(*AfterMI))
         continue;
 

>From 4b4552e6050a0fe6c096f906963a9b77f6a302f3 Mon Sep 17 00:00:00 2001
From: Rose <83477269+AtariDreams at users.noreply.github.com>
Date: Tue, 20 Feb 2024 20:41:40 -0500
Subject: [PATCH 2/2] [X86] Resolve FIXME: Add FPCW as a rounding control
 register

To prevent tests from breaking, another fix had to be made: Now, we check if the instruction after a waiting instruction is a call, and if so, we insert the wait.
---
 llvm/lib/Target/X86/X86ISelLoweringCall.cpp | 4 +---
 llvm/lib/Target/X86/X86RegisterInfo.td      | 6 +++---
 2 files changed, 4 insertions(+), 6 deletions(-)

diff --git a/llvm/lib/Target/X86/X86ISelLoweringCall.cpp b/llvm/lib/Target/X86/X86ISelLoweringCall.cpp
index be8275c92e11ae..c7ef11aede886a 100644
--- a/llvm/lib/Target/X86/X86ISelLoweringCall.cpp
+++ b/llvm/lib/Target/X86/X86ISelLoweringCall.cpp
@@ -670,9 +670,7 @@ const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
 }
 
 ArrayRef<MCPhysReg> X86TargetLowering::getRoundingControlRegisters() const {
-  // FIXME: We should def X86::FPCW for x87 as well. But it affects a lot of lit
-  // tests at the moment, which is not what we expected.
-  static const MCPhysReg RCRegs[] = {X86::MXCSR};
+  static const MCPhysReg RCRegs[] = {X86::FPCW, X86::MXCSR};
   return RCRegs;
 }
 
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.td b/llvm/lib/Target/X86/X86RegisterInfo.td
index 166024bf3b53fe..e9b86361bbd8ec 100644
--- a/llvm/lib/Target/X86/X86RegisterInfo.td
+++ b/llvm/lib/Target/X86/X86RegisterInfo.td
@@ -445,12 +445,12 @@ def ST5 : X86Reg<"st(5)", 5>, DwarfRegNum<[38, 17, 16]>;
 def ST6 : X86Reg<"st(6)", 6>, DwarfRegNum<[39, 18, 17]>;
 def ST7 : X86Reg<"st(7)", 7>, DwarfRegNum<[40, 19, 18]>;
 
-// Floating-point status word
-def FPSW : X86Reg<"fpsr", 0>;
-
 // Floating-point control word
 def FPCW : X86Reg<"fpcr", 0>;
 
+// Floating-point status word
+def FPSW : X86Reg<"fpsr", 0>;
+
 // SIMD Floating-point control register.
 // Note: We only model the "Uses" of the control bits: current rounding modes,
 // DAZ, FTZ and exception masks. We don't model the "Defs" of flag bits.