[llvm] [RISCV][TTI] Cost a subvector extract at a register boundary with exact vlen (PR #82405)

[Philip Reames via llvm-commits]

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@@ -436,6 +436,22 @@ InstructionCost RISCVTTIImpl::getShuffleCost(TTI::ShuffleKind Kind,
     if (Index == 0)
       return TTI::TCC_Free;
 
+    // If we're extracting a subvector of at most m1 size at a sub-register
+    // boundary - which unfortunately we need exact vlen to identity - this is
+    // a subregister extract at worst and thus won't require a vslidedown.
+    // TODO: Extend for aligned m2, m4 subvector extracts
+    // TODO: Extend for misalgined (but contained) extracts
+    // TODO: Extend for scalable subvector types
+    if (std::pair<InstructionCost, MVT> SubLT = getTypeLegalizationCost(SubTp);
+        SubLT.second.isValid() && SubLT.second.isFixedLengthVector()) {
+      const unsigned MinVLen = ST->getRealMinVLen();
+      const unsigned MaxVLen = ST->getRealMaxVLen();
+      if (MinVLen == MaxVLen &&
+          SubLT.second.getScalarSizeInBits() * Index % MinVLen == 0 &&
+          SubLT.second.getSizeInBits() <= MinVLen)
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preames wrote:

> For extending it to m2+, checking that the extract is LMUL aligned is the same as checking that the index is a multiple of the number of elements, so you could do something like:

I'll explore this in a follow up after auditing the testing for the >= m2 case.  

https://github.com/llvm/llvm-project/pull/82405