[llvm] f723260 - [TableGen] Stop using make_pair and make_tuple. NFC. (#81730)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 14 05:16:24 PST 2024
Author: Jay Foad
Date: 2024-02-14T13:16:20Z
New Revision: f723260a80baee08394093fa06777dcc55b3ee4a
URL: https://github.com/llvm/llvm-project/commit/f723260a80baee08394093fa06777dcc55b3ee4a
DIFF: https://github.com/llvm/llvm-project/commit/f723260a80baee08394093fa06777dcc55b3ee4a.diff
LOG: [TableGen] Stop using make_pair and make_tuple. NFC. (#81730)
These are unnecessary since C++17.
Added:
Modified:
llvm/utils/TableGen/AsmMatcherEmitter.cpp
llvm/utils/TableGen/AsmWriterEmitter.cpp
llvm/utils/TableGen/CTagsEmitter.cpp
llvm/utils/TableGen/CodeEmitterGen.cpp
llvm/utils/TableGen/CodeGenDAGPatterns.cpp
llvm/utils/TableGen/CodeGenHwModes.cpp
llvm/utils/TableGen/CodeGenInstAlias.cpp
llvm/utils/TableGen/CodeGenInstruction.cpp
llvm/utils/TableGen/CodeGenInstruction.h
llvm/utils/TableGen/CodeGenRegisters.cpp
llvm/utils/TableGen/CodeGenRegisters.h
llvm/utils/TableGen/CodeGenSchedule.cpp
llvm/utils/TableGen/CodeGenTarget.cpp
llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
llvm/utils/TableGen/DAGISelMatcherGen.cpp
llvm/utils/TableGen/DAGISelMatcherOpt.cpp
llvm/utils/TableGen/DFAEmitter.cpp
llvm/utils/TableGen/DXILEmitter.cpp
llvm/utils/TableGen/DecoderEmitter.cpp
llvm/utils/TableGen/FastISelEmitter.cpp
llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
llvm/utils/TableGen/GlobalISelEmitter.cpp
llvm/utils/TableGen/GlobalISelMatchTable.cpp
llvm/utils/TableGen/GlobalISelMatchTable.h
llvm/utils/TableGen/InfoByHwMode.cpp
llvm/utils/TableGen/InfoByHwMode.h
llvm/utils/TableGen/IntrinsicEmitter.cpp
llvm/utils/TableGen/OptParserEmitter.cpp
llvm/utils/TableGen/SearchableTableEmitter.cpp
llvm/utils/TableGen/SequenceToOffsetTable.h
llvm/utils/TableGen/WebAssemblyDisassemblerEmitter.cpp
llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp
llvm/utils/TableGen/X86DisassemblerTables.cpp
llvm/utils/TableGen/X86FoldTablesEmitter.cpp
Removed:
################################################################################
diff --git a/llvm/utils/TableGen/AsmMatcherEmitter.cpp b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
index 2c2c39a3ef54ff..3fcf2d87cc36ae 100644
--- a/llvm/utils/TableGen/AsmMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
@@ -1277,7 +1277,7 @@ void AsmMatcherInfo::buildRegisterClasses(
if (!ContainingSet.empty()) {
RegisterSets.insert(ContainingSet);
- RegisterMap.insert(std::make_pair(CGR.TheDef, ContainingSet));
+ RegisterMap.insert(std::pair(CGR.TheDef, ContainingSet));
}
}
@@ -1298,7 +1298,7 @@ void AsmMatcherInfo::buildRegisterClasses(
CI->DiagnosticType = "";
CI->IsOptional = false;
CI->DefaultMethod = ""; // unused
- RegisterSetClasses.insert(std::make_pair(RS, CI));
+ RegisterSetClasses.insert(std::pair(RS, CI));
++Index;
}
@@ -1340,7 +1340,7 @@ void AsmMatcherInfo::buildRegisterClasses(
if (!CI->DiagnosticString.empty() && CI->DiagnosticType.empty())
CI->DiagnosticType = RC.getName();
- RegisterClassClasses.insert(std::make_pair(Def, CI));
+ RegisterClassClasses.insert(std::pair(Def, CI));
}
// Populate the map for individual registers.
@@ -2193,7 +2193,7 @@ emitConvertFuncs(CodeGenTarget &Target, StringRef ClassName,
ConversionRow.push_back(SrcOp2);
// Also create an 'enum' for this combination of tied operands.
- auto Key = std::make_tuple(TiedOp, SrcOp1, SrcOp2);
+ auto Key = std::tuple(TiedOp, SrcOp1, SrcOp2);
TiedOperandsEnumMap.emplace(Key, TiedTupleName);
break;
}
@@ -2342,9 +2342,9 @@ emitConvertFuncs(CodeGenTarget &Target, StringRef ClassName,
// For a tied operand, emit a reference to the TiedAsmOperandTable
// that contains the operand to copy, and the parsed operands to
// check for their tied constraints.
- auto Key = std::make_tuple((uint8_t)ConversionTable[Row][i + 1],
- (uint8_t)ConversionTable[Row][i + 2],
- (uint8_t)ConversionTable[Row][i + 3]);
+ auto Key = std::tuple((uint8_t)ConversionTable[Row][i + 1],
+ (uint8_t)ConversionTable[Row][i + 2],
+ (uint8_t)ConversionTable[Row][i + 3]);
auto TiedOpndEnum = TiedOperandsEnumMap.find(Key);
assert(TiedOpndEnum != TiedOperandsEnumMap.end() &&
"No record for tied operand pair");
@@ -2812,7 +2812,7 @@ emitMnemonicAliasVariant(raw_ostream &OS, const AsmMatcherInfo &Info,
MatchCode += "return;";
- Cases.push_back(std::make_pair(AliasEntry.first, MatchCode));
+ Cases.push_back(std::pair(AliasEntry.first, MatchCode));
}
StringMatcher("Mnemonic", Cases, OS).Emit(Indent);
}
@@ -2979,7 +2979,7 @@ emitCustomOperandParsing(raw_ostream &OS, CodeGenTarget &Target,
"std::end(OperandMatchTable),\n";
OS << " Mnemonic, LessOpcodeOperand());\n\n";
} else {
- OS << " auto MnemonicRange = std::make_pair(std::begin(OperandMatchTable),"
+ OS << " auto MnemonicRange = std::pair(std::begin(OperandMatchTable),"
" std::end(OperandMatchTable));\n";
OS << " if (!Mnemonic.empty())\n";
OS << " MnemonicRange =\n";
@@ -3154,7 +3154,7 @@ static void emitMnemonicChecker(raw_ostream &OS, CodeGenTarget &Target,
OS << " auto MnemonicRange = "
"std::equal_range(Start, End, Mnemonic, LessOpcode());\n\n";
} else {
- OS << " auto MnemonicRange = std::make_pair(Start, End);\n";
+ OS << " auto MnemonicRange = std::pair(Start, End);\n";
OS << " unsigned SIndex = Mnemonic.empty() ? 0 : 1;\n";
OS << " if (!Mnemonic.empty())\n";
OS << " MnemonicRange = "
@@ -3629,7 +3629,7 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
OS << " auto MnemonicRange = "
"std::equal_range(Start, End, Mnemonic, LessOpcode());\n\n";
} else {
- OS << " auto MnemonicRange = std::make_pair(Start, End);\n";
+ OS << " auto MnemonicRange = std::pair(Start, End);\n";
OS << " unsigned SIndex = Mnemonic.empty() ? 0 : 1;\n";
OS << " if (!Mnemonic.empty())\n";
OS << " MnemonicRange = "
diff --git a/llvm/utils/TableGen/AsmWriterEmitter.cpp b/llvm/utils/TableGen/AsmWriterEmitter.cpp
index c05991fdbb1667..a27061ee585a59 100644
--- a/llvm/utils/TableGen/AsmWriterEmitter.cpp
+++ b/llvm/utils/TableGen/AsmWriterEmitter.cpp
@@ -144,13 +144,12 @@ static void EmitInstructions(std::vector<AsmWriterInst> &Insts, raw_ostream &O,
O << " switch (MI->getOpcode()) {\n";
O << " default: llvm_unreachable(\"Unexpected opcode.\");\n";
std::vector<std::pair<std::string, AsmWriterOperand>> OpsToPrint;
- OpsToPrint.push_back(
- std::make_pair(FirstInst.CGI->Namespace.str() +
- "::" + FirstInst.CGI->TheDef->getName().str(),
- FirstInst.Operands[i]));
+ OpsToPrint.push_back(std::pair(FirstInst.CGI->Namespace.str() + "::" +
+ FirstInst.CGI->TheDef->getName().str(),
+ FirstInst.Operands[i]));
for (const AsmWriterInst &AWI : SimilarInsts) {
- OpsToPrint.push_back(std::make_pair(
+ OpsToPrint.push_back(std::pair(
AWI.CGI->Namespace.str() + "::" + AWI.CGI->TheDef->getName().str(),
AWI.Operands[i]));
}
@@ -722,7 +721,7 @@ class IAPrinter {
void addOperand(StringRef Op, int OpIdx, int PrintMethodIdx = -1) {
assert(OpIdx >= 0 && OpIdx < 0xFE && "Idx out of range");
assert(PrintMethodIdx >= -1 && PrintMethodIdx < 0xFF && "Idx out of range");
- OpMap[Op] = std::make_pair(OpIdx, PrintMethodIdx);
+ OpMap[Op] = std::pair(OpIdx, PrintMethodIdx);
}
unsigned getNumMIOps() { return NumMIOps; }
@@ -753,7 +752,7 @@ class IAPrinter {
Next = I;
}
- return std::make_pair(StringRef(Start, I - Start), Next);
+ return std::pair(StringRef(Start, I - Start), Next);
}
std::string formatAliasString(uint32_t &UnescapedSize) {
@@ -858,7 +857,7 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
const DagInit *DI = R->getValueAsDag("ResultInst");
AliasMap[getQualifiedName(DI->getOperatorAsDef(R->getLoc()))].insert(
- std::make_pair(CodeGenInstAlias(R, Target), Priority));
+ std::pair(CodeGenInstAlias(R, Target), Priority));
}
// A map of which conditions need to be met for each instruction operand
diff --git a/llvm/utils/TableGen/CTagsEmitter.cpp b/llvm/utils/TableGen/CTagsEmitter.cpp
index bda18936dc771d..e21dc36a6e959a 100644
--- a/llvm/utils/TableGen/CTagsEmitter.cpp
+++ b/llvm/utils/TableGen/CTagsEmitter.cpp
@@ -40,8 +40,8 @@ class Tag {
Line = LineAndColumn.first;
}
int operator<(const Tag &B) const {
- return std::make_tuple(Id, BufferIdentifier, Line) <
- std::make_tuple(B.Id, B.BufferIdentifier, B.Line);
+ return std::tuple(Id, BufferIdentifier, Line) <
+ std::tuple(B.Id, B.BufferIdentifier, B.Line);
}
void emit(raw_ostream &OS) const {
OS << Id << "\t" << BufferIdentifier << "\t" << Line << "\n";
diff --git a/llvm/utils/TableGen/CodeEmitterGen.cpp b/llvm/utils/TableGen/CodeEmitterGen.cpp
index d7020d1d78b0aa..d80761d5fe35d2 100644
--- a/llvm/utils/TableGen/CodeEmitterGen.cpp
+++ b/llvm/utils/TableGen/CodeEmitterGen.cpp
@@ -300,11 +300,11 @@ CodeEmitterGen::getInstructionCases(Record *R, CodeGenTarget &Target) {
append(" }\n");
}
append(" }\n");
- return std::make_pair(std::move(Case), std::move(BitOffsetCase));
+ return std::pair(std::move(Case), std::move(BitOffsetCase));
}
}
addInstructionCasesForEncoding(R, R, Target, Case, BitOffsetCase);
- return std::make_pair(std::move(Case), std::move(BitOffsetCase));
+ return std::pair(std::move(Case), std::move(BitOffsetCase));
}
void CodeEmitterGen::addInstructionCasesForEncoding(
diff --git a/llvm/utils/TableGen/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/CodeGenDAGPatterns.cpp
index a9046e09a62976..ca6aa4b251e9b2 100644
--- a/llvm/utils/TableGen/CodeGenDAGPatterns.cpp
+++ b/llvm/utils/TableGen/CodeGenDAGPatterns.cpp
@@ -530,24 +530,24 @@ bool TypeInfer::EnforceSmallerThan(TypeSetByHwMode &Small, TypeSetByHwMode &Big,
auto LT = [](MVT A, MVT B) -> bool {
// Always treat non-scalable MVTs as smaller than scalable MVTs for the
// purposes of ordering.
- auto ASize = std::make_tuple(A.isScalableVector(), A.getScalarSizeInBits(),
- A.getSizeInBits().getKnownMinValue());
- auto BSize = std::make_tuple(B.isScalableVector(), B.getScalarSizeInBits(),
- B.getSizeInBits().getKnownMinValue());
+ auto ASize = std::tuple(A.isScalableVector(), A.getScalarSizeInBits(),
+ A.getSizeInBits().getKnownMinValue());
+ auto BSize = std::tuple(B.isScalableVector(), B.getScalarSizeInBits(),
+ B.getSizeInBits().getKnownMinValue());
return ASize < BSize;
};
auto SameKindLE = [](MVT A, MVT B) -> bool {
// This function is used when removing elements: when a vector is compared
// to a non-vector or a scalable vector to any non-scalable MVT, it should
// return false (to avoid removal).
- if (std::make_tuple(A.isVector(), A.isScalableVector()) !=
- std::make_tuple(B.isVector(), B.isScalableVector()))
+ if (std::tuple(A.isVector(), A.isScalableVector()) !=
+ std::tuple(B.isVector(), B.isScalableVector()))
return false;
- return std::make_tuple(A.getScalarSizeInBits(),
- A.getSizeInBits().getKnownMinValue()) <=
- std::make_tuple(B.getScalarSizeInBits(),
- B.getSizeInBits().getKnownMinValue());
+ return std::tuple(A.getScalarSizeInBits(),
+ A.getSizeInBits().getKnownMinValue()) <=
+ std::tuple(B.getScalarSizeInBits(),
+ B.getSizeInBits().getKnownMinValue());
};
for (unsigned M : Modes) {
@@ -751,8 +751,8 @@ bool TypeInfer::EnforceSameNumElts(TypeSetByHwMode &V, TypeSetByHwMode &W) {
namespace {
struct TypeSizeComparator {
bool operator()(const TypeSize &LHS, const TypeSize &RHS) const {
- return std::make_tuple(LHS.isScalable(), LHS.getKnownMinValue()) <
- std::make_tuple(RHS.isScalable(), RHS.getKnownMinValue());
+ return std::tuple(LHS.isScalable(), LHS.getKnownMinValue()) <
+ std::tuple(RHS.isScalable(), RHS.getKnownMinValue());
}
};
} // end anonymous namespace
@@ -2988,7 +2988,7 @@ TreePatternNodePtr TreePattern::ParseTreePattern(Init *TheInit,
// Check that the ComplexPattern uses are consistent: "(MY_PAT $a, $b)"
// and "(MY_PAT $b, $a)" should not be allowed in the same pattern;
// neither should "(MY_PAT_1 $a, $b)" and "(MY_PAT_2 $a, $b)".
- auto OperandId = std::make_pair(Operator, i);
+ auto OperandId = std::pair(Operator, i);
auto PrevOp = ComplexPatternOperands.find(Child->getName());
if (PrevOp != ComplexPatternOperands.end()) {
if (PrevOp->getValue() != OperandId)
@@ -3197,7 +3197,7 @@ void CodeGenDAGPatterns::ParseNodeInfo() {
while (!Nodes.empty()) {
Record *R = Nodes.back();
- SDNodes.insert(std::make_pair(R, SDNodeInfo(R, CGH)));
+ SDNodes.insert(std::pair(R, SDNodeInfo(R, CGH)));
Nodes.pop_back();
}
@@ -3217,7 +3217,7 @@ void CodeGenDAGPatterns::ParseNodeTransforms() {
Record *SDNode = XFormNode->getValueAsDef("Opcode");
StringRef Code = XFormNode->getValueAsString("XFormFunction");
SDNodeXForms.insert(
- std::make_pair(XFormNode, NodeXForm(SDNode, std::string(Code))));
+ std::pair(XFormNode, NodeXForm(SDNode, std::string(Code))));
Xforms.pop_back();
}
@@ -3227,7 +3227,7 @@ void CodeGenDAGPatterns::ParseComplexPatterns() {
std::vector<Record *> AMs =
Records.getAllDerivedDefinitions("ComplexPattern");
while (!AMs.empty()) {
- ComplexPatterns.insert(std::make_pair(AMs.back(), AMs.back()));
+ ComplexPatterns.insert(std::pair(AMs.back(), AMs.back()));
AMs.pop_back();
}
}
@@ -3340,7 +3340,7 @@ void CodeGenDAGPatterns::ParseDefaultOperands() {
std::vector<std::pair<Init *, StringInit *>> Ops;
for (unsigned op = 0, e = DefaultInfo->getNumArgs(); op != e; ++op)
Ops.push_back(
- std::make_pair(DefaultInfo->getArg(op), DefaultInfo->getArgName(op)));
+ std::pair(DefaultInfo->getArg(op), DefaultInfo->getArgName(op)));
DagInit *DI = DagInit::get(SomeSDNode, nullptr, Ops);
// Create a TreePattern to parse this.
diff --git a/llvm/utils/TableGen/CodeGenHwModes.cpp b/llvm/utils/TableGen/CodeGenHwModes.cpp
index 7c08c7516054ec..fec74d29c8bbbd 100644
--- a/llvm/utils/TableGen/CodeGenHwModes.cpp
+++ b/llvm/utils/TableGen/CodeGenHwModes.cpp
@@ -52,7 +52,7 @@ HwModeSelect::HwModeSelect(Record *R, CodeGenHwModes &CGH) {
}
for (unsigned i = 0, e = Modes.size(); i != e; ++i) {
unsigned ModeId = CGH.getHwModeId(Modes[i]);
- Items.push_back(std::make_pair(ModeId, Objects[i]));
+ Items.push_back(std::pair(ModeId, Objects[i]));
}
}
@@ -71,11 +71,11 @@ CodeGenHwModes::CodeGenHwModes(RecordKeeper &RK) : Records(RK) {
if (R->getName() == DefaultModeName)
continue;
Modes.emplace_back(R);
- ModeIds.insert(std::make_pair(R, Modes.size()));
+ ModeIds.insert(std::pair(R, Modes.size()));
}
for (Record *R : Records.getAllDerivedDefinitions("HwModeSelect")) {
- auto P = ModeSelects.emplace(std::make_pair(R, HwModeSelect(R, *this)));
+ auto P = ModeSelects.emplace(std::pair(R, HwModeSelect(R, *this)));
assert(P.second);
(void)P;
}
diff --git a/llvm/utils/TableGen/CodeGenInstAlias.cpp b/llvm/utils/TableGen/CodeGenInstAlias.cpp
index 8634d45eafc707..d217059542b1ad 100644
--- a/llvm/utils/TableGen/CodeGenInstAlias.cpp
+++ b/llvm/utils/TableGen/CodeGenInstAlias.cpp
@@ -227,7 +227,7 @@ CodeGenInstAlias::CodeGenInstAlias(Record *R, CodeGenTarget &T) : TheDef(R) {
InstOpRec->getValueAsDef("ParserMatchClass")
->getValueAsString("Name") != "Imm")) {
ResultOperands.push_back(ResOp);
- ResultInstOperandIndex.push_back(std::make_pair(i, -1));
+ ResultInstOperandIndex.push_back(std::pair(i, -1));
++AliasOpNo;
// Otherwise, we need to match each of the suboperands individually.
@@ -242,7 +242,7 @@ CodeGenInstAlias::CodeGenInstAlias(Record *R, CodeGenTarget &T) : TheDef(R) {
Result->getArgName(AliasOpNo)->getAsUnquotedString() + "." +
MIOI->getArgName(SubOp)->getAsUnquotedString(),
SubRec);
- ResultInstOperandIndex.push_back(std::make_pair(i, SubOp));
+ ResultInstOperandIndex.push_back(std::pair(i, SubOp));
}
++AliasOpNo;
}
@@ -260,7 +260,7 @@ CodeGenInstAlias::CodeGenInstAlias(Record *R, CodeGenTarget &T) : TheDef(R) {
if (tryAliasOpMatch(Result, AliasOpNo, SubRec, false, R->getLoc(), T,
ResOp)) {
ResultOperands.push_back(ResOp);
- ResultInstOperandIndex.push_back(std::make_pair(i, SubOp));
+ ResultInstOperandIndex.push_back(std::pair(i, SubOp));
++AliasOpNo;
} else {
PrintFatalError(
diff --git a/llvm/utils/TableGen/CodeGenInstruction.cpp b/llvm/utils/TableGen/CodeGenInstruction.cpp
index a569194ef23cbc..b00b95da5fc276 100644
--- a/llvm/utils/TableGen/CodeGenInstruction.cpp
+++ b/llvm/utils/TableGen/CodeGenInstruction.cpp
@@ -175,7 +175,7 @@ CGIOperandList::CGIOperandList(Record *R) : TheDef(R) {
}
OpInfo.SubOpNames[j] = SubArgName;
- SubOpAliases[SubArgName] = std::make_pair(i, j);
+ SubOpAliases[SubArgName] = std::pair(i, j);
}
} else if (!EncoderMethod.empty()) {
// If we have no explicit sub-op dag, but have an top-level encoder
@@ -276,7 +276,7 @@ CGIOperandList::ParseOperandName(StringRef Op, bool AllowWholeOp) {
Op + "'");
// Otherwise, return the operand.
- return std::make_pair(OpIdx, 0U);
+ return std::pair(OpIdx, 0U);
}
// Find the suboperand number involved.
@@ -289,13 +289,13 @@ CGIOperandList::ParseOperandName(StringRef Op, bool AllowWholeOp) {
// Find the operand with the right name.
for (unsigned i = 0, e = MIOpInfo->getNumArgs(); i != e; ++i)
if (MIOpInfo->getArgNameStr(i) == SubOpName)
- return std::make_pair(OpIdx, i);
+ return std::pair(OpIdx, i);
// Otherwise, didn't find it!
PrintFatalError(TheDef->getLoc(), TheDef->getName() +
": unknown suboperand name in '" + Op +
"'");
- return std::make_pair(0U, 0U);
+ return std::pair(0U, 0U);
}
static void ParseConstraint(StringRef CStr, CGIOperandList &Ops, Record *Rec) {
diff --git a/llvm/utils/TableGen/CodeGenInstruction.h b/llvm/utils/TableGen/CodeGenInstruction.h
index ca7b1e9f7f4a4f..11a3acd8e72335 100644
--- a/llvm/utils/TableGen/CodeGenInstruction.h
+++ b/llvm/utils/TableGen/CodeGenInstruction.h
@@ -205,7 +205,7 @@ class CGIOperandList {
for (unsigned i = 0;; ++i) {
assert(i < OperandList.size() && "Invalid flat operand #");
if (OperandList[i].MIOperandNo + OperandList[i].MINumOperands > Op)
- return std::make_pair(i, Op - OperandList[i].MIOperandNo);
+ return std::pair(i, Op - OperandList[i].MIOperandNo);
}
}
diff --git a/llvm/utils/TableGen/CodeGenRegisters.cpp b/llvm/utils/TableGen/CodeGenRegisters.cpp
index 7d266c8896d8e3..5890f0f40e4059 100644
--- a/llvm/utils/TableGen/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/CodeGenRegisters.cpp
@@ -281,13 +281,13 @@ CodeGenRegister::computeSubRegs(CodeGenRegBank &RegBank) {
CodeGenSubRegIndex *Idx = ExplicitSubRegIndices[i];
if (!SR->Artificial)
Idx->Artificial = false;
- if (!SubRegs.insert(std::make_pair(Idx, SR)).second)
+ if (!SubRegs.insert(std::pair(Idx, SR)).second)
PrintFatalError(TheDef->getLoc(), "SubRegIndex " + Idx->getName() +
" appears twice in Register " +
getName());
// Map explicit sub-registers first, so the names take precedence.
// The inherited sub-registers are mapped below.
- SubReg2Idx.insert(std::make_pair(SR, Idx));
+ SubReg2Idx.insert(std::pair(SR, Idx));
}
// Keep track of inherited subregs and how they can be reached.
@@ -327,7 +327,7 @@ CodeGenRegister::computeSubRegs(CodeGenRegBank &RegBank) {
if (SubRegs.count(Comp.second) || !Orphans.erase(SRI->second))
continue;
// We found a new name for the orphaned sub-register.
- SubRegs.insert(std::make_pair(Comp.second, SRI->second));
+ SubRegs.insert(std::pair(Comp.second, SRI->second));
Indices.push_back(Comp.second);
}
}
@@ -374,7 +374,7 @@ CodeGenRegister::computeSubRegs(CodeGenRegBank &RegBank) {
// Ensure that every sub-register has a unique name.
DenseMap<const CodeGenRegister *, CodeGenSubRegIndex *>::iterator Ins =
- SubReg2Idx.insert(std::make_pair(SubReg.second, SubReg.first)).first;
+ SubReg2Idx.insert(std::pair(SubReg.second, SubReg.first)).first;
if (Ins->second == SubReg.first)
continue;
// Trouble: Two
diff erent names for SubReg.second.
@@ -520,7 +520,7 @@ void CodeGenRegister::computeSecondarySubRegs(CodeGenRegBank &RegBank) {
// a sub-register with a concatenated sub-register index.
CodeGenSubRegIndex *Concat = RegBank.getConcatSubRegIndex(Parts);
std::pair<CodeGenSubRegIndex *, CodeGenRegister *> NewSubReg =
- std::make_pair(Concat, Cand);
+ std::pair(Concat, Cand);
if (!SubRegs.insert(NewSubReg).second)
continue;
@@ -528,7 +528,7 @@ void CodeGenRegister::computeSecondarySubRegs(CodeGenRegBank &RegBank) {
// We inserted a new subregister.
NewSubRegs.push_back(NewSubReg);
SubRegQueue.push(NewSubReg);
- SubReg2Idx.insert(std::make_pair(Cand, Concat));
+ SubReg2Idx.insert(std::pair(Cand, Concat));
}
}
@@ -1074,7 +1074,7 @@ CodeGenRegisterClass::getMatchingSubClassWithSubRegs(
BitVector SuperRegClassesBV(RegClasses.size());
RC.getSuperRegClasses(SubIdx, SuperRegClassesBV);
if (SuperRegClassesBV.any())
- SuperRegClasses.push_back(std::make_pair(&RC, SuperRegClassesBV));
+ SuperRegClasses.push_back(std::pair(&RC, SuperRegClassesBV));
}
llvm::stable_sort(SuperRegClasses,
[&](const std::pair<CodeGenRegisterClass *, BitVector> &A,
@@ -1110,14 +1110,14 @@ CodeGenRegisterClass::getMatchingSubClassWithSubRegs(
// aren't subregisters of SuperRegRC whereas GR32 has a direct 1:1
// mapping.
if (SuperRegRC->getMembers().size() >= SubRegRC->getMembers().size())
- return std::make_pair(ChosenSuperRegClass, SubRegRC);
+ return std::pair(ChosenSuperRegClass, SubRegRC);
}
}
// If we found a fit but it wasn't quite ideal because SubRegRC had excess
// registers, then we're done.
if (ChosenSuperRegClass)
- return std::make_pair(ChosenSuperRegClass, SubRegRC);
+ return std::pair(ChosenSuperRegClass, SubRegRC);
}
return std::nullopt;
@@ -1230,7 +1230,7 @@ CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records,
// entries? (or maybe there's a reason for it - I don't know much about this
// code, just drive-by refactoring)
RegistersByName.insert(
- std::make_pair(Reg.TheDef->getValueAsString("AsmName"), &Reg));
+ std::pair(Reg.TheDef->getValueAsString("AsmName"), &Reg));
// Precompute all sub-register maps.
// This will create Composite entries for all inferred sub-register indices.
@@ -1242,10 +1242,10 @@ CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records,
for (CodeGenSubRegIndex &SRI : SubRegIndices) {
SRI.computeConcatTransitiveClosure();
if (!SRI.ConcatenationOf.empty())
- ConcatIdx.insert(std::make_pair(
- SmallVector<CodeGenSubRegIndex *, 8>(SRI.ConcatenationOf.begin(),
- SRI.ConcatenationOf.end()),
- &SRI));
+ ConcatIdx.insert(
+ std::pair(SmallVector<CodeGenSubRegIndex *, 8>(
+ SRI.ConcatenationOf.begin(), SRI.ConcatenationOf.end()),
+ &SRI));
}
// Infer even more sub-registers by combining leading super-registers.
@@ -1336,12 +1336,12 @@ CodeGenRegister *CodeGenRegBank::getReg(Record *Def) {
void CodeGenRegBank::addToMaps(CodeGenRegisterClass *RC) {
if (Record *Def = RC->getDef())
- Def2RC.insert(std::make_pair(Def, RC));
+ Def2RC.insert(std::pair(Def, RC));
// Duplicate classes are rejected by insert().
// That's OK, we only care about the properties handled by CGRC::Key.
CodeGenRegisterClass::Key K(*RC);
- Key2RC.insert(std::make_pair(K, RC));
+ Key2RC.insert(std::pair(K, RC));
}
// Create a synthetic sub-class if it is missing.
@@ -1472,7 +1472,7 @@ void CodeGenRegBank::computeComposites() {
SmallSet<CompositePair, 4> UserDefined;
for (const CodeGenSubRegIndex &Idx : SubRegIndices)
for (auto P : Idx.getComposites())
- UserDefined.insert(std::make_pair(&Idx, P.first));
+ UserDefined.insert(std::pair(&Idx, P.first));
// Keep track of TopoSigs visited. We only need to visit each TopoSig once,
// and many registers will share TopoSigs on regular architectures.
diff --git a/llvm/utils/TableGen/CodeGenRegisters.h b/llvm/utils/TableGen/CodeGenRegisters.h
index fc5cd67e2d553d..61e8e7c857e921 100644
--- a/llvm/utils/TableGen/CodeGenRegisters.h
+++ b/llvm/utils/TableGen/CodeGenRegisters.h
@@ -111,8 +111,7 @@ class CodeGenSubRegIndex {
CodeGenSubRegIndex *addComposite(CodeGenSubRegIndex *A,
CodeGenSubRegIndex *B) {
assert(A && B);
- std::pair<CompMap::iterator, bool> Ins =
- Composed.insert(std::make_pair(A, B));
+ std::pair<CompMap::iterator, bool> Ins = Composed.insert(std::pair(A, B));
// Synthetic subreg indices that aren't contiguous (for instance ARM
// register tuples) don't have a bit range, so it's OK to let
// B->Offset == -1. For the other cases, accumulate the offset and set
@@ -706,7 +705,7 @@ class CodeGenRegBank {
// This function is only for use by CodeGenRegister::computeSuperRegs().
// Others should simply use Reg->getTopoSig().
unsigned getTopoSig(const TopoSigId &Id) {
- return TopoSigs.insert(std::make_pair(Id, TopoSigs.size())).first->second;
+ return TopoSigs.insert(std::pair(Id, TopoSigs.size())).first->second;
}
// Create a native register unit that is associated with one or two root
diff --git a/llvm/utils/TableGen/CodeGenSchedule.cpp b/llvm/utils/TableGen/CodeGenSchedule.cpp
index e56bf5bdee634b..b4c624703626c3 100644
--- a/llvm/utils/TableGen/CodeGenSchedule.cpp
+++ b/llvm/utils/TableGen/CodeGenSchedule.cpp
@@ -338,7 +338,7 @@ static void processSTIPredicate(STIPredicateFunction &Fn,
APInt DefaultProcMask(ProcModelMap.size(), 0);
APInt DefaultPredMask(NumUniquePredicates, 0);
for (std::pair<APInt, APInt> &MaskPair : OpcodeMasks)
- MaskPair = std::make_pair(DefaultProcMask, DefaultPredMask);
+ MaskPair = std::pair(DefaultProcMask, DefaultPredMask);
// Construct a OpcodeInfo object for every unique opcode declared by an
// InstructionEquivalenceClass definition.
@@ -564,7 +564,7 @@ void CodeGenSchedModels::collectProcModels() {
/// ProcessorItineraries.
void CodeGenSchedModels::addProcModel(Record *ProcDef) {
Record *ModelKey = getModelOrItinDef(ProcDef);
- if (!ProcModelMap.insert(std::make_pair(ModelKey, ProcModels.size())).second)
+ if (!ProcModelMap.insert(std::pair(ModelKey, ProcModels.size())).second)
return;
std::string Name = std::string(ModelKey->getName());
diff --git a/llvm/utils/TableGen/CodeGenTarget.cpp b/llvm/utils/TableGen/CodeGenTarget.cpp
index 8e2957efe85406..f26815c2f184fa 100644
--- a/llvm/utils/TableGen/CodeGenTarget.cpp
+++ b/llvm/utils/TableGen/CodeGenTarget.cpp
@@ -534,8 +534,8 @@ void CodeGenTarget::ComputeInstrsByEnum() const {
[](const CodeGenInstruction *Rec1, const CodeGenInstruction *Rec2) {
const auto &D1 = *Rec1->TheDef;
const auto &D2 = *Rec2->TheDef;
- return std::make_tuple(!D1.getValueAsBit("isPseudo"), D1.getName()) <
- std::make_tuple(!D2.getValueAsBit("isPseudo"), D2.getName());
+ return std::tuple(!D1.getValueAsBit("isPseudo"), D1.getName()) <
+ std::tuple(!D2.getValueAsBit("isPseudo"), D2.getName());
});
// Assign an enum value to each instruction according to the sorted order.
diff --git a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
index b475c98d30a6e0..533b8c42369029 100644
--- a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
@@ -73,7 +73,7 @@ class MatcherTableEmitter {
unsigned getPatternIdxFromTable(std::string &&P, std::string &&include_loc) {
const auto It = VecPatterns.find(P);
if (It == VecPatterns.end()) {
- VecPatterns.insert(make_pair(std::move(P), VecPatterns.size()));
+ VecPatterns.insert(std::pair(std::move(P), VecPatterns.size()));
VecIncludeStrings.push_back(std::move(include_loc));
return VecIncludeStrings.size() - 1;
}
diff --git a/llvm/utils/TableGen/DAGISelMatcherGen.cpp b/llvm/utils/TableGen/DAGISelMatcherGen.cpp
index 956cb5e4a65aad..e8bdabaa0c7e89 100644
--- a/llvm/utils/TableGen/DAGISelMatcherGen.cpp
+++ b/llvm/utils/TableGen/DAGISelMatcherGen.cpp
@@ -252,7 +252,7 @@ void MatcherGen::EmitLeafMatchCode(const TreePatternNode &N) {
if (LeafRec->isSubClassOf("Register")) {
AddMatcher(new RecordMatcher("physreg input " + LeafRec->getName().str(),
NextRecordedOperandNo));
- PhysRegInputs.push_back(std::make_pair(LeafRec, NextRecordedOperandNo++));
+ PhysRegInputs.push_back(std::pair(LeafRec, NextRecordedOperandNo++));
return;
}
@@ -272,7 +272,7 @@ void MatcherGen::EmitLeafMatchCode(const TreePatternNode &N) {
// Remember this ComplexPattern so that we can emit it after all the other
// structural matches are done.
unsigned InputOperand = VariableMap[N.getName()] - 1;
- MatchedComplexPatterns.push_back(std::make_pair(&N, InputOperand));
+ MatchedComplexPatterns.push_back(std::pair(&N, InputOperand));
return;
}
@@ -313,7 +313,7 @@ void MatcherGen::EmitOperatorMatchCode(const TreePatternNode &N,
}
if (recordUniqueNode(PatternName)) {
- auto NodeAndOpNum = std::make_pair(&N, NextRecordedOperandNo - 1);
+ auto NodeAndOpNum = std::pair(&N, NextRecordedOperandNo - 1);
MatchedComplexPatterns.push_back(NodeAndOpNum);
}
diff --git a/llvm/utils/TableGen/DAGISelMatcherOpt.cpp b/llvm/utils/TableGen/DAGISelMatcherOpt.cpp
index f786d41c88d7ce..047d285f9914e5 100644
--- a/llvm/utils/TableGen/DAGISelMatcherOpt.cpp
+++ b/llvm/utils/TableGen/DAGISelMatcherOpt.cpp
@@ -425,7 +425,7 @@ static void FactorNodes(std::unique_ptr<Matcher> &InputMatcherPtr) {
CheckOpcodeMatcher *COM = cast<CheckOpcodeMatcher>(OptionsToMatch[i]);
assert(Opcodes.insert(COM->getOpcode().getEnumName()).second &&
"Duplicate opcodes not factored?");
- Cases.push_back(std::make_pair(&COM->getOpcode(), COM->takeNext()));
+ Cases.push_back(std::pair(&COM->getOpcode(), COM->takeNext()));
delete COM;
}
@@ -462,7 +462,7 @@ static void FactorNodes(std::unique_ptr<Matcher> &InputMatcherPtr) {
}
Entry = Cases.size() + 1;
- Cases.push_back(std::make_pair(CTMTy, MatcherWithoutCTM));
+ Cases.push_back(std::pair(CTMTy, MatcherWithoutCTM));
}
// Make sure we recursively factor any scopes we may have created.
diff --git a/llvm/utils/TableGen/DFAEmitter.cpp b/llvm/utils/TableGen/DFAEmitter.cpp
index 0d22ad251fba41..ce8cc2a078d717 100644
--- a/llvm/utils/TableGen/DFAEmitter.cpp
+++ b/llvm/utils/TableGen/DFAEmitter.cpp
@@ -81,7 +81,7 @@ void DfaEmitter::visitDfaState(const DfaState &DS) {
sort(TI);
TI.erase(std::unique(TI.begin(), TI.end()), TI.end());
unsigned ToId = DfaStates.insert(NewStates);
- DfaTransitions.emplace(std::make_pair(FromId, A), std::make_pair(ToId, TI));
+ DfaTransitions.emplace(std::pair(FromId, A), std::pair(ToId, TI));
}
}
@@ -353,7 +353,7 @@ void CustomDfaEmitter::printActionType(raw_ostream &OS) { OS << TypeName; }
void CustomDfaEmitter::printActionValue(action_type A, raw_ostream &OS) {
const ActionTuple &AT = Actions[A];
if (AT.size() > 1)
- OS << "std::make_tuple(";
+ OS << "std::tuple(";
ListSeparator LS;
for (const auto &SingleAction : AT) {
OS << LS;
diff --git a/llvm/utils/TableGen/DXILEmitter.cpp b/llvm/utils/TableGen/DXILEmitter.cpp
index 3378a904ac404d..768e8052975b7f 100644
--- a/llvm/utils/TableGen/DXILEmitter.cpp
+++ b/llvm/utils/TableGen/DXILEmitter.cpp
@@ -245,7 +245,7 @@ static void emitDXILEnums(std::vector<DXILOperationDesc> &Ops,
std::vector<std::pair<std::string, std::string>> ClassVec;
for (auto &It : ClassMap) {
ClassVec.emplace_back(
- std::make_pair(It.getKey().str(), buildCategoryStr(It.second)));
+ std::pair(It.getKey().str(), buildCategoryStr(It.second)));
}
// Sort by Category + ClassName.
llvm::sort(ClassVec, [](std::pair<std::string, std::string> &A,
diff --git a/llvm/utils/TableGen/DecoderEmitter.cpp b/llvm/utils/TableGen/DecoderEmitter.cpp
index 2f28ccbe6d6ceb..02d9527fd9ed91 100644
--- a/llvm/utils/TableGen/DecoderEmitter.cpp
+++ b/llvm/utils/TableGen/DecoderEmitter.cpp
@@ -614,7 +614,7 @@ void Filter::recurse() {
// Delegates to an inferior filter chooser for further processing on this
// group of instructions whose segment values are variable.
- FilterChooserMap.insert(std::make_pair(
+ FilterChooserMap.insert(std::pair(
NO_FIXED_SEGMENTS_SENTINEL,
std::make_unique<FilterChooser>(Owner->AllInstructions,
VariableInstructions, Owner->Operands,
@@ -641,10 +641,10 @@ void Filter::recurse() {
// Delegates to an inferior filter chooser for further processing on this
// category of instructions.
- FilterChooserMap.insert(std::make_pair(
- Inst.first, std::make_unique<FilterChooser>(
- Owner->AllInstructions, Inst.second, Owner->Operands,
- BitValueArray, *Owner)));
+ FilterChooserMap.insert(
+ std::pair(Inst.first, std::make_unique<FilterChooser>(
+ Owner->AllInstructions, Inst.second,
+ Owner->Operands, BitValueArray, *Owner)));
}
}
@@ -1908,7 +1908,7 @@ void parseVarLenInstOperand(const Record &Def,
int TiedReg = TiedTo[OpSubOpPair.first];
if (TiedReg != -1) {
unsigned OpIdx = CGI.Operands.getFlattenedOperandNumber(
- std::make_pair(TiedReg, OpSubOpPair.second));
+ std::pair(TiedReg, OpSubOpPair.second));
Operands[OpIdx].addField(CurrBitPos, EncodingSegment.BitWidth, Offset);
}
}
@@ -2005,11 +2005,9 @@ populateInstruction(CodeGenTarget &Target, const Record &EncodingDef,
DagInit *Out = Def.getValueAsDag("OutOperandList");
DagInit *In = Def.getValueAsDag("InOperandList");
for (unsigned i = 0; i < Out->getNumArgs(); ++i)
- InOutOperands.push_back(
- std::make_pair(Out->getArg(i), Out->getArgNameStr(i)));
+ InOutOperands.push_back(std::pair(Out->getArg(i), Out->getArgNameStr(i)));
for (unsigned i = 0; i < In->getNumArgs(); ++i)
- InOutOperands.push_back(
- std::make_pair(In->getArg(i), In->getArgNameStr(i)));
+ InOutOperands.push_back(std::pair(In->getArg(i), In->getArgNameStr(i)));
// Search for tied operands, so that we can correctly instantiate
// operands that are not explicitly represented in the encoding.
@@ -2545,7 +2543,7 @@ void DecoderEmitter::run(raw_ostream &o) {
if (!NumberedEncodings[i].HwModeName.empty())
DecoderNamespace +=
std::string("_") + NumberedEncodings[i].HwModeName.str();
- OpcMap[std::make_pair(DecoderNamespace, Size)].emplace_back(
+ OpcMap[std::pair(DecoderNamespace, Size)].emplace_back(
i, IndexOfInstruction.find(Def)->second);
} else {
NumEncodingsOmitted++;
diff --git a/llvm/utils/TableGen/FastISelEmitter.cpp b/llvm/utils/TableGen/FastISelEmitter.cpp
index 00a165030d36bf..f04c6e3b3bf05d 100644
--- a/llvm/utils/TableGen/FastISelEmitter.cpp
+++ b/llvm/utils/TableGen/FastISelEmitter.cpp
@@ -595,7 +595,7 @@ void FastISelMap::collectPatterns(CodeGenDAGPatterns &CGP) {
int complexity = Pattern.getPatternComplexity(CGP);
auto inserted_simple_pattern = SimplePatternsCheck.insert(
- std::make_tuple(Operands, OpcodeName, VT, RetVT, PredicateCheck));
+ std::tuple(Operands, OpcodeName, VT, RetVT, PredicateCheck));
if (!inserted_simple_pattern.second) {
PrintFatalError(Pattern.getSrcRecord()->getLoc(),
"Duplicate predicate in FastISel table!");
diff --git a/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp b/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
index d9249cf627f21e..dee3cb4d71a403 100644
--- a/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
+++ b/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
@@ -2956,8 +2956,8 @@ GICombinerEmitter::buildMatchTable(MutableArrayRef<RuleMatcher> Rules) {
const Matcher *B) {
auto *L = static_cast<const RuleMatcher *>(A);
auto *R = static_cast<const RuleMatcher *>(B);
- return std::make_tuple(OpcodeOrder[L->getOpcode()], L->getNumOperands()) <
- std::make_tuple(OpcodeOrder[R->getOpcode()], R->getNumOperands());
+ return std::tuple(OpcodeOrder[L->getOpcode()], L->getNumOperands()) <
+ std::tuple(OpcodeOrder[R->getOpcode()], R->getNumOperands());
});
for (Matcher *Rule : InputRules)
diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp b/llvm/utils/TableGen/GlobalISelEmitter.cpp
index 13f2384efc9ce0..618cb2fedb9292 100644
--- a/llvm/utils/TableGen/GlobalISelEmitter.cpp
+++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp
@@ -2215,8 +2215,8 @@ GlobalISelEmitter::buildMatchTable(MutableArrayRef<RuleMatcher> Rules,
const Matcher *B) {
auto *L = static_cast<const RuleMatcher *>(A);
auto *R = static_cast<const RuleMatcher *>(B);
- return std::make_tuple(OpcodeOrder[L->getOpcode()], L->getNumOperands()) <
- std::make_tuple(OpcodeOrder[R->getOpcode()], R->getNumOperands());
+ return std::tuple(OpcodeOrder[L->getOpcode()], L->getNumOperands()) <
+ std::tuple(OpcodeOrder[R->getOpcode()], R->getNumOperands());
});
for (Matcher *Rule : InputRules)
diff --git a/llvm/utils/TableGen/GlobalISelMatchTable.cpp b/llvm/utils/TableGen/GlobalISelMatchTable.cpp
index d1bdc30849a7f6..45fb41b89f2787 100644
--- a/llvm/utils/TableGen/GlobalISelMatchTable.cpp
+++ b/llvm/utils/TableGen/GlobalISelMatchTable.cpp
@@ -408,18 +408,18 @@ bool LLTCodeGen::operator<(const LLTCodeGen &Other) const {
return Ty.getAddressSpace() < Other.Ty.getAddressSpace();
if (Ty.isVector() && Ty.getElementCount() != Other.Ty.getElementCount())
- return std::make_tuple(Ty.isScalable(),
- Ty.getElementCount().getKnownMinValue()) <
- std::make_tuple(Other.Ty.isScalable(),
- Other.Ty.getElementCount().getKnownMinValue());
+ return std::tuple(Ty.isScalable(),
+ Ty.getElementCount().getKnownMinValue()) <
+ std::tuple(Other.Ty.isScalable(),
+ Other.Ty.getElementCount().getKnownMinValue());
assert((!Ty.isVector() || Ty.isScalable() == Other.Ty.isScalable()) &&
"Unexpected mismatch of scalable property");
return Ty.isVector()
- ? std::make_tuple(Ty.isScalable(),
- Ty.getSizeInBits().getKnownMinValue()) <
- std::make_tuple(Other.Ty.isScalable(),
- Other.Ty.getSizeInBits().getKnownMinValue())
+ ? std::tuple(Ty.isScalable(),
+ Ty.getSizeInBits().getKnownMinValue()) <
+ std::tuple(Other.Ty.isScalable(),
+ Other.Ty.getSizeInBits().getKnownMinValue())
: Ty.getSizeInBits().getFixedValue() <
Other.Ty.getSizeInBits().getFixedValue();
}
@@ -720,8 +720,8 @@ void RuleMatcher::optimize() {
}
llvm::sort(EpilogueMatchers, [](const std::unique_ptr<PredicateMatcher> &L,
const std::unique_ptr<PredicateMatcher> &R) {
- return std::make_tuple(L->getKind(), L->getInsnVarID(), L->getOpIdx()) <
- std::make_tuple(R->getKind(), R->getInsnVarID(), R->getOpIdx());
+ return std::tuple(L->getKind(), L->getInsnVarID(), L->getOpIdx()) <
+ std::tuple(R->getKind(), R->getInsnVarID(), R->getOpIdx());
});
}
@@ -822,7 +822,7 @@ Error RuleMatcher::defineComplexSubOperand(StringRef SymbolicName,
}
ComplexSubOperands[SymbolicName] =
- std::make_tuple(ComplexPattern, RendererID, SubOperandID);
+ std::tuple(ComplexPattern, RendererID, SubOperandID);
ComplexSubOperandsParentName[SymbolicName] = ParentName;
return Error::success();
diff --git a/llvm/utils/TableGen/GlobalISelMatchTable.h b/llvm/utils/TableGen/GlobalISelMatchTable.h
index 635552fc890406..b1ab7da8db4461 100644
--- a/llvm/utils/TableGen/GlobalISelMatchTable.h
+++ b/llvm/utils/TableGen/GlobalISelMatchTable.h
@@ -232,7 +232,7 @@ class MatchTable {
unsigned allocateLabelID() { return CurrentLabelID++; }
void defineLabel(unsigned LabelID) {
- LabelMap.insert(std::make_pair(LabelID, CurrentSize));
+ LabelMap.insert(std::pair(LabelID, CurrentSize));
}
unsigned getLabelIndex(unsigned LabelID) const {
diff --git a/llvm/utils/TableGen/InfoByHwMode.cpp b/llvm/utils/TableGen/InfoByHwMode.cpp
index 6d9a35a68e138e..4a64421c013c5f 100644
--- a/llvm/utils/TableGen/InfoByHwMode.cpp
+++ b/llvm/utils/TableGen/InfoByHwMode.cpp
@@ -69,9 +69,9 @@ MVT &ValueTypeByHwMode::getOrCreateTypeForMode(unsigned Mode, MVT Type) {
// make a copy of it for Mode and return it.
auto D = Map.begin();
if (D != Map.end() && D->first == DefaultMode)
- return Map.insert(std::make_pair(Mode, D->second)).first->second;
+ return Map.insert(std::pair(Mode, D->second)).first->second;
// If default mode is not present either, use provided Type.
- return Map.insert(std::make_pair(Mode, Type)).first->second;
+ return Map.insert(std::pair(Mode, Type)).first->second;
}
StringRef ValueTypeByHwMode::getMVTName(MVT T) {
diff --git a/llvm/utils/TableGen/InfoByHwMode.h b/llvm/utils/TableGen/InfoByHwMode.h
index 5f532958414888..001509e5317f95 100644
--- a/llvm/utils/TableGen/InfoByHwMode.h
+++ b/llvm/utils/TableGen/InfoByHwMode.h
@@ -144,7 +144,7 @@ template <typename InfoT> struct InfoByHwMode {
assert(hasMode(Mode) || hasDefault());
InfoT I = get(Mode);
Map.clear();
- Map.insert(std::make_pair(DefaultMode, I));
+ Map.insert(std::pair(DefaultMode, I));
}
protected:
@@ -209,7 +209,7 @@ struct RegSizeInfoByHwMode : public InfoByHwMode<RegSizeInfo> {
void writeToStream(raw_ostream &OS) const;
void insertRegSizeForMode(unsigned Mode, RegSizeInfo Info) {
- Map.insert(std::make_pair(Mode, Info));
+ Map.insert(std::pair(Mode, Info));
}
};
diff --git a/llvm/utils/TableGen/IntrinsicEmitter.cpp b/llvm/utils/TableGen/IntrinsicEmitter.cpp
index f7ae5ed8a6b3cb..50a34eac7ca35a 100644
--- a/llvm/utils/TableGen/IntrinsicEmitter.cpp
+++ b/llvm/utils/TableGen/IntrinsicEmitter.cpp
@@ -637,7 +637,7 @@ void IntrinsicEmitter::EmitIntrinsicToBuiltinMap(
std::map<std::string, std::string> &BIM =
BuiltinMap[Ints[i].TargetPrefix];
- if (!BIM.insert(std::make_pair(BuiltinName, Ints[i].EnumName)).second)
+ if (!BIM.insert(std::pair(BuiltinName, Ints[i].EnumName)).second)
PrintFatalError(Ints[i].TheDef->getLoc(),
"Intrinsic '" + Ints[i].TheDef->getName() +
"': duplicate " + CompilerName + " builtin name!");
diff --git a/llvm/utils/TableGen/OptParserEmitter.cpp b/llvm/utils/TableGen/OptParserEmitter.cpp
index 0f081197b5b826..c25f6c59cab383 100644
--- a/llvm/utils/TableGen/OptParserEmitter.cpp
+++ b/llvm/utils/TableGen/OptParserEmitter.cpp
@@ -207,14 +207,14 @@ static void EmitOptParser(RecordKeeper &Records, raw_ostream &OS) {
typedef SmallVector<SmallString<2>, 2> PrefixKeyT;
typedef std::map<PrefixKeyT, std::string> PrefixesT;
PrefixesT Prefixes;
- Prefixes.insert(std::make_pair(PrefixKeyT(), "prefix_0"));
+ Prefixes.insert(std::pair(PrefixKeyT(), "prefix_0"));
unsigned CurPrefix = 0;
for (const Record &R : llvm::make_pointee_range(Opts)) {
std::vector<StringRef> RPrefixes = R.getValueAsListOfStrings("Prefixes");
PrefixKeyT PrefixKey(RPrefixes.begin(), RPrefixes.end());
unsigned NewPrefix = CurPrefix + 1;
std::string Prefix = (Twine("prefix_") + Twine(NewPrefix)).str();
- if (Prefixes.insert(std::make_pair(PrefixKey, Prefix)).second)
+ if (Prefixes.insert(std::pair(PrefixKey, Prefix)).second)
CurPrefix = NewPrefix;
}
diff --git a/llvm/utils/TableGen/SearchableTableEmitter.cpp b/llvm/utils/TableGen/SearchableTableEmitter.cpp
index 0cce798a27b4ab..5bab4ff188e8ed 100644
--- a/llvm/utils/TableGen/SearchableTableEmitter.cpp
+++ b/llvm/utils/TableGen/SearchableTableEmitter.cpp
@@ -608,7 +608,7 @@ void SearchableTableEmitter::collectEnumEntries(
Value = getInt(EntryRec, ValueField);
Enum.Entries.push_back(std::make_unique<GenericEnum::Entry>(Name, Value));
- Enum.EntryMap.insert(std::make_pair(EntryRec, Enum.Entries.back().get()));
+ Enum.EntryMap.insert(std::pair(EntryRec, Enum.Entries.back().get()));
}
if (ValueField.empty()) {
@@ -708,7 +708,7 @@ void SearchableTableEmitter::run(raw_ostream &OS) {
collectEnumEntries(*Enum, NameField, ValueField,
Records.getAllDerivedDefinitions(FilterClass));
- EnumMap.insert(std::make_pair(EnumRec, Enum.get()));
+ EnumMap.insert(std::pair(EnumRec, Enum.get()));
Enums.emplace_back(std::move(Enum));
}
@@ -773,7 +773,7 @@ void SearchableTableEmitter::run(raw_ostream &OS) {
});
}
- TableMap.insert(std::make_pair(TableRec, Table.get()));
+ TableMap.insert(std::pair(TableRec, Table.get()));
Tables.emplace_back(std::move(Table));
}
diff --git a/llvm/utils/TableGen/SequenceToOffsetTable.h b/llvm/utils/TableGen/SequenceToOffsetTable.h
index 7db39a9af72092..5766b682b58a38 100644
--- a/llvm/utils/TableGen/SequenceToOffsetTable.h
+++ b/llvm/utils/TableGen/SequenceToOffsetTable.h
@@ -87,7 +87,7 @@ class SequenceToOffsetTable {
if (I != Seqs.end() && isSuffix(Seq, I->first))
return;
- I = Seqs.insert(I, std::make_pair(Seq, 0u));
+ I = Seqs.insert(I, std::pair(Seq, 0u));
// The entry before I may be a suffix of Seq that can now be erased.
if (I != Seqs.begin() && isSuffix((--I)->first, Seq))
diff --git a/llvm/utils/TableGen/WebAssemblyDisassemblerEmitter.cpp b/llvm/utils/TableGen/WebAssemblyDisassemblerEmitter.cpp
index 2cf86d38a2120b..928129f24fcb49 100644
--- a/llvm/utils/TableGen/WebAssemblyDisassemblerEmitter.cpp
+++ b/llvm/utils/TableGen/WebAssemblyDisassemblerEmitter.cpp
@@ -80,7 +80,7 @@ void emitWebAssemblyDisassemblerTables(
}
}
// Set this instruction as the one to use.
- CGIP = std::make_pair(I, &CGI);
+ CGIP = std::pair(I, &CGI);
}
OS << "#include \"MCTargetDesc/WebAssemblyMCTargetDesc.h\"\n";
OS << "\n";
diff --git a/llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp b/llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp
index e4db995d47f7e6..b96d16b9797cf3 100644
--- a/llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp
+++ b/llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp
@@ -120,12 +120,11 @@ class IsMatch {
RecognizableInstrBase OldRI(*OldInst);
// Return false if any of the following fields of does not match.
- if (std::make_tuple(OldRI.IsCodeGenOnly, OldRI.OpMap, NewRI.OpPrefix,
- OldRI.HasVEX_4V, OldRI.HasVEX_L, OldRI.HasREX_W,
- OldRI.Form) !=
- std::make_tuple(NewRI.IsCodeGenOnly, NewRI.OpMap, OldRI.OpPrefix,
- NewRI.HasVEX_4V, NewRI.HasVEX_L, NewRI.HasREX_W,
- NewRI.Form))
+ if (std::tuple(OldRI.IsCodeGenOnly, OldRI.OpMap, NewRI.OpPrefix,
+ OldRI.HasVEX_4V, OldRI.HasVEX_L, OldRI.HasREX_W,
+ OldRI.Form) !=
+ std::tuple(NewRI.IsCodeGenOnly, NewRI.OpMap, OldRI.OpPrefix,
+ NewRI.HasVEX_4V, NewRI.HasVEX_L, NewRI.HasREX_W, NewRI.Form))
return false;
for (unsigned I = 0, E = OldInst->Operands.size(); I < E; ++I) {
@@ -219,7 +218,7 @@ void X86CompressEVEXTablesEmitter::run(raw_ostream &OS) {
if (!NewInst)
continue;
- Table.push_back(std::make_pair(Inst, NewInst));
+ Table.push_back(std::pair(Inst, NewInst));
auto Predicates = NewInst->TheDef->getValueAsListOfDefs("Predicates");
auto It = llvm::find_if(Predicates, [](const Record *R) {
StringRef Name = R->getName();
diff --git a/llvm/utils/TableGen/X86DisassemblerTables.cpp b/llvm/utils/TableGen/X86DisassemblerTables.cpp
index 588d9b22a772a3..a48b9cfe42e37f 100644
--- a/llvm/utils/TableGen/X86DisassemblerTables.cpp
+++ b/llvm/utils/TableGen/X86DisassemblerTables.cpp
@@ -845,7 +845,7 @@ void DisassemblerTables::emitInstructionInfo(raw_ostream &o,
for (auto Operand : InstructionSpecifiers[Index].operands) {
OperandEncoding Encoding = (OperandEncoding)Operand.encoding;
OperandType Type = (OperandType)Operand.type;
- OperandList.push_back(std::make_pair(Encoding, Type));
+ OperandList.push_back(std::pair(Encoding, Type));
}
unsigned &N = OperandSets[OperandList];
if (N != 0)
@@ -877,7 +877,7 @@ void DisassemblerTables::emitInstructionInfo(raw_ostream &o,
for (auto Operand : InstructionSpecifiers[index].operands) {
OperandEncoding Encoding = (OperandEncoding)Operand.encoding;
OperandType Type = (OperandType)Operand.type;
- OperandList.push_back(std::make_pair(Encoding, Type));
+ OperandList.push_back(std::pair(Encoding, Type));
}
o.indent(i * 2) << (OperandSets[OperandList] - 1) << ",\n";
diff --git a/llvm/utils/TableGen/X86FoldTablesEmitter.cpp b/llvm/utils/TableGen/X86FoldTablesEmitter.cpp
index 44c2817e1b5d68..1319042e48d060 100644
--- a/llvm/utils/TableGen/X86FoldTablesEmitter.cpp
+++ b/llvm/utils/TableGen/X86FoldTablesEmitter.cpp
@@ -171,8 +171,8 @@ class X86FoldTablesEmitter {
assert(LHS && RHS && "LHS and RHS shouldn't be nullptr");
const auto &D1 = *LHS->TheDef;
const auto &D2 = *RHS->TheDef;
- return std::make_tuple(!D1.getValueAsBit("isPseudo"), D1.getName()) <
- std::make_tuple(!D2.getValueAsBit("isPseudo"), D2.getName());
+ return std::tuple(!D1.getValueAsBit("isPseudo"), D1.getName()) <
+ std::tuple(!D2.getValueAsBit("isPseudo"), D2.getName());
}
};
@@ -372,22 +372,20 @@ class IsMatch {
return false;
// Return false if any of the following fields of does not match.
- if (std::make_tuple(RegRI.Encoding, RegRI.Opcode, RegRI.OpPrefix,
- RegRI.OpMap, RegRI.OpSize, RegRI.AdSize, RegRI.HasREX_W,
- RegRI.HasVEX_4V, RegRI.HasVEX_L, RegRI.IgnoresVEX_L,
- RegRI.IgnoresW, RegRI.HasEVEX_K, RegRI.HasEVEX_KZ,
- RegRI.HasEVEX_L2, RegRI.HasEVEX_NF,
- RegRec->getValueAsBit("hasEVEX_RC"),
- RegRec->getValueAsBit("hasLockPrefix"),
- RegRec->getValueAsBit("hasNoTrackPrefix")) !=
- std::make_tuple(MemRI.Encoding, MemRI.Opcode, MemRI.OpPrefix,
- MemRI.OpMap, MemRI.OpSize, MemRI.AdSize, MemRI.HasREX_W,
- MemRI.HasVEX_4V, MemRI.HasVEX_L, MemRI.IgnoresVEX_L,
- MemRI.IgnoresW, MemRI.HasEVEX_K, MemRI.HasEVEX_KZ,
- MemRI.HasEVEX_L2, MemRI.HasEVEX_NF,
- MemRec->getValueAsBit("hasEVEX_RC"),
- MemRec->getValueAsBit("hasLockPrefix"),
- MemRec->getValueAsBit("hasNoTrackPrefix")))
+ if (std::tuple(RegRI.Encoding, RegRI.Opcode, RegRI.OpPrefix, RegRI.OpMap,
+ RegRI.OpSize, RegRI.AdSize, RegRI.HasREX_W, RegRI.HasVEX_4V,
+ RegRI.HasVEX_L, RegRI.IgnoresVEX_L, RegRI.IgnoresW,
+ RegRI.HasEVEX_K, RegRI.HasEVEX_KZ, RegRI.HasEVEX_L2,
+ RegRI.HasEVEX_NF, RegRec->getValueAsBit("hasEVEX_RC"),
+ RegRec->getValueAsBit("hasLockPrefix"),
+ RegRec->getValueAsBit("hasNoTrackPrefix")) !=
+ std::tuple(MemRI.Encoding, MemRI.Opcode, MemRI.OpPrefix, MemRI.OpMap,
+ MemRI.OpSize, MemRI.AdSize, MemRI.HasREX_W, MemRI.HasVEX_4V,
+ MemRI.HasVEX_L, MemRI.IgnoresVEX_L, MemRI.IgnoresW,
+ MemRI.HasEVEX_K, MemRI.HasEVEX_KZ, MemRI.HasEVEX_L2,
+ MemRI.HasEVEX_NF, MemRec->getValueAsBit("hasEVEX_RC"),
+ MemRec->getValueAsBit("hasLockPrefix"),
+ MemRec->getValueAsBit("hasNoTrackPrefix")))
return false;
// Make sure the sizes of the operands of both instructions suit each other.
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