[llvm] goldsteinn/icmp lowbit mask (PR #81562)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 12 17:44:59 PST 2024
https://github.com/goldsteinn created https://github.com/llvm/llvm-project/pull/81562
- [InstCombine] Add tests for expanding `foldICmpWithLowBitMaskedVal`; NFC
- [InstCombine] Improve mask detection in `foldICmpWithLowBitMaskedVal`
- [InstCombine] Recognize `(icmp eq/ne (and X, ~Mask), 0)` pattern in `foldICmpWithLowBitMaskedVal`
>From b2a1e189c34215f71cae6ebddb4d4fe21c331f40 Mon Sep 17 00:00:00 2001
From: Noah Goldstein <goldstein.w.n at gmail.com>
Date: Wed, 13 Sep 2023 13:45:49 -0500
Subject: [PATCH 1/3] [InstCombine] Add tests for expanding
`foldICmpWithLowBitMaskedVal`; NFC
Differential Revision: https://reviews.llvm.org/D159057
---
.../InstCombine/icmp-and-lowbit-mask.ll | 650 ++++++++++++++++++
1 file changed, 650 insertions(+)
create mode 100644 llvm/test/Transforms/InstCombine/icmp-and-lowbit-mask.ll
diff --git a/llvm/test/Transforms/InstCombine/icmp-and-lowbit-mask.ll b/llvm/test/Transforms/InstCombine/icmp-and-lowbit-mask.ll
new file mode 100644
index 00000000000000..b98cdb50cf7859
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/icmp-and-lowbit-mask.ll
@@ -0,0 +1,650 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -passes=instcombine -S | FileCheck %s
+
+declare void @llvm.assume(i1)
+declare i8 @llvm.ctpop.i8(i8)
+declare i8 @llvm.umin.i8(i8, i8)
+declare i8 @llvm.umax.i8(i8, i8)
+declare i8 @llvm.smin.i8(i8, i8)
+declare i8 @llvm.smax.i8(i8, i8)
+declare i8 @llvm.bitreverse.i8(i8)
+declare void @use.i8(i8)
+declare void @use.i16(i16)
+define i1 @src_is_mask_zext(i16 %x_in, i8 %y) {
+; CHECK-LABEL: @src_is_mask_zext(
+; CHECK-NEXT: [[X:%.*]] = xor i16 [[X_IN:%.*]], 123
+; CHECK-NEXT: [[M_IN:%.*]] = lshr i8 -1, [[Y:%.*]]
+; CHECK-NEXT: [[MASK:%.*]] = zext i8 [[M_IN]] to i16
+; CHECK-NEXT: [[AND:%.*]] = and i16 [[X]], [[MASK]]
+; CHECK-NEXT: [[R:%.*]] = icmp eq i16 [[AND]], [[X]]
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %x = xor i16 %x_in, 123
+ %m_in = lshr i8 -1, %y
+ %mask = zext i8 %m_in to i16
+
+ %and = and i16 %x, %mask
+ %r = icmp eq i16 %and, %x
+ ret i1 %r
+}
+
+define i1 @src_is_mask_zext_fail_not_mask(i16 %x_in, i8 %y) {
+; CHECK-LABEL: @src_is_mask_zext_fail_not_mask(
+; CHECK-NEXT: [[X:%.*]] = xor i16 [[X_IN:%.*]], 123
+; CHECK-NEXT: [[M_IN:%.*]] = lshr i8 -2, [[Y:%.*]]
+; CHECK-NEXT: [[MASK:%.*]] = zext i8 [[M_IN]] to i16
+; CHECK-NEXT: [[AND:%.*]] = and i16 [[X]], [[MASK]]
+; CHECK-NEXT: [[R:%.*]] = icmp eq i16 [[AND]], [[X]]
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %x = xor i16 %x_in, 123
+ %m_in = lshr i8 -2, %y
+ %mask = zext i8 %m_in to i16
+
+ %and = and i16 %x, %mask
+ %r = icmp eq i16 %and, %x
+ ret i1 %r
+}
+
+define i1 @src_is_mask_sext(i16 %x_in, i8 %y) {
+; CHECK-LABEL: @src_is_mask_sext(
+; CHECK-NEXT: [[X:%.*]] = xor i16 [[X_IN:%.*]], 123
+; CHECK-NEXT: [[M_IN:%.*]] = lshr i8 31, [[Y:%.*]]
+; CHECK-NEXT: [[MASK:%.*]] = zext nneg i8 [[M_IN]] to i16
+; CHECK-NEXT: [[NOTMASK:%.*]] = xor i16 [[MASK]], -1
+; CHECK-NEXT: [[AND:%.*]] = and i16 [[X]], [[NOTMASK]]
+; CHECK-NEXT: [[R:%.*]] = icmp eq i16 [[AND]], 0
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %x = xor i16 %x_in, 123
+ %m_in = lshr i8 31, %y
+ %mask = sext i8 %m_in to i16
+ %notmask = xor i16 %mask, -1
+
+ %and = and i16 %notmask, %x
+ %r = icmp eq i16 %and, 0
+ ret i1 %r
+}
+
+define i1 @src_is_mask_sext_fail_multiuse(i16 %x_in, i8 %y) {
+; CHECK-LABEL: @src_is_mask_sext_fail_multiuse(
+; CHECK-NEXT: [[X:%.*]] = xor i16 [[X_IN:%.*]], 122
+; CHECK-NEXT: [[M_IN:%.*]] = lshr i8 -1, [[Y:%.*]]
+; CHECK-NEXT: [[TMP1:%.*]] = xor i8 [[M_IN]], -1
+; CHECK-NEXT: [[NOTMASK:%.*]] = sext i8 [[TMP1]] to i16
+; CHECK-NEXT: [[AND:%.*]] = and i16 [[X]], [[NOTMASK]]
+; CHECK-NEXT: call void @use.i16(i16 [[AND]])
+; CHECK-NEXT: [[R:%.*]] = icmp eq i16 [[AND]], 0
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %x = xor i16 %x_in, 123
+ %m_in = lshr i8 -1, %y
+ %mask = sext i8 %m_in to i16
+ %notmask = xor i16 %mask, -1
+
+ %and = and i16 %notmask, %x
+ call void @use.i16(i16 %and)
+ %r = icmp eq i16 %and, 0
+ ret i1 %r
+}
+
+define i1 @src_is_mask_and(i8 %x_in, i8 %y, i8 %z) {
+; CHECK-LABEL: @src_is_mask_and(
+; CHECK-NEXT: [[X:%.*]] = xor i8 [[X_IN:%.*]], 123
+; CHECK-NEXT: [[MY:%.*]] = lshr i8 7, [[Y:%.*]]
+; CHECK-NEXT: [[MZ:%.*]] = lshr i8 -1, [[Z:%.*]]
+; CHECK-NEXT: [[MASK:%.*]] = and i8 [[MY]], [[MZ]]
+; CHECK-NEXT: [[AND:%.*]] = and i8 [[X]], [[MASK]]
+; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[X]], [[AND]]
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %x = xor i8 %x_in, 123
+ %my = ashr i8 7, %y
+ %mz = lshr i8 -1, %z
+ %mask = and i8 %my, %mz
+
+ %and = and i8 %x, %mask
+ %r = icmp eq i8 %x, %and
+ ret i1 %r
+}
+
+define i1 @src_is_mask_and_fail_mixed(i8 %x_in, i8 %y, i8 %z) {
+; CHECK-LABEL: @src_is_mask_and_fail_mixed(
+; CHECK-NEXT: [[X:%.*]] = xor i8 [[X_IN:%.*]], 123
+; CHECK-NEXT: [[MY:%.*]] = ashr i8 -8, [[Y:%.*]]
+; CHECK-NEXT: [[MZ:%.*]] = lshr i8 -1, [[Z:%.*]]
+; CHECK-NEXT: [[MASK:%.*]] = and i8 [[MY]], [[MZ]]
+; CHECK-NEXT: [[AND:%.*]] = and i8 [[X]], [[MASK]]
+; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[X]], [[AND]]
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %x = xor i8 %x_in, 123
+ %my = ashr i8 -8, %y
+ %mz = lshr i8 -1, %z
+ %mask = and i8 %my, %mz
+
+ %and = and i8 %x, %mask
+ %r = icmp eq i8 %x, %and
+ ret i1 %r
+}
+
+define i1 @src_is_mask_or(i8 %x_in, i8 %y) {
+; CHECK-LABEL: @src_is_mask_or(
+; CHECK-NEXT: [[X:%.*]] = xor i8 [[X_IN:%.*]], 123
+; CHECK-NEXT: [[MY:%.*]] = lshr i8 -1, [[Y:%.*]]
+; CHECK-NEXT: [[MASK:%.*]] = and i8 [[MY]], 7
+; CHECK-NEXT: [[AND:%.*]] = and i8 [[MASK]], [[X]]
+; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[X]], [[AND]]
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %x = xor i8 %x_in, 123
+ %my = lshr i8 -1, %y
+ %mask = and i8 %my, 7
+
+ %and = and i8 %mask, %x
+ %r = icmp eq i8 %x, %and
+ ret i1 %r
+}
+
+define i1 @src_is_mask_xor(i8 %x_in, i8 %y) {
+; CHECK-LABEL: @src_is_mask_xor(
+; CHECK-NEXT: [[X:%.*]] = xor i8 [[X_IN:%.*]], 123
+; CHECK-NEXT: [[Y_M1:%.*]] = add i8 [[Y:%.*]], -1
+; CHECK-NEXT: [[MASK:%.*]] = xor i8 [[Y_M1]], [[Y]]
+; CHECK-NEXT: [[AND:%.*]] = and i8 [[X]], [[MASK]]
+; CHECK-NEXT: [[R:%.*]] = icmp ne i8 [[AND]], [[X]]
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %x = xor i8 %x_in, 123
+ %y_m1 = add i8 %y, -1
+ %mask = xor i8 %y, %y_m1
+ %and = and i8 %x, %mask
+ %r = icmp ne i8 %and, %x
+ ret i1 %r
+}
+
+define i1 @src_is_mask_xor_fail_notmask(i8 %x_in, i8 %y) {
+; CHECK-LABEL: @src_is_mask_xor_fail_notmask(
+; CHECK-NEXT: [[X:%.*]] = xor i8 [[X_IN:%.*]], 123
+; CHECK-NEXT: [[TMP1:%.*]] = sub i8 0, [[Y:%.*]]
+; CHECK-NEXT: [[NOTMASK:%.*]] = xor i8 [[TMP1]], [[Y]]
+; CHECK-NEXT: [[AND:%.*]] = and i8 [[X]], [[NOTMASK]]
+; CHECK-NEXT: [[R:%.*]] = icmp ne i8 [[AND]], [[X]]
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %x = xor i8 %x_in, 123
+ %y_m1 = add i8 %y, -1
+ %mask = xor i8 %y, %y_m1
+ %notmask = xor i8 %mask, -1
+ %and = and i8 %x, %notmask
+ %r = icmp ne i8 %and, %x
+ ret i1 %r
+}
+
+define i1 @src_is_mask_select(i8 %x_in, i8 %y, i1 %cond) {
+; CHECK-LABEL: @src_is_mask_select(
+; CHECK-NEXT: [[X:%.*]] = xor i8 [[X_IN:%.*]], 123
+; CHECK-NEXT: [[Y_M1:%.*]] = add i8 [[Y:%.*]], -1
+; CHECK-NEXT: [[YMASK:%.*]] = xor i8 [[Y_M1]], [[Y]]
+; CHECK-NEXT: [[MASK:%.*]] = select i1 [[COND:%.*]], i8 [[YMASK]], i8 15
+; CHECK-NEXT: [[AND:%.*]] = and i8 [[MASK]], [[X]]
+; CHECK-NEXT: [[R:%.*]] = icmp ne i8 [[AND]], [[X]]
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %x = xor i8 %x_in, 123
+ %y_m1 = add i8 %y, -1
+ %ymask = xor i8 %y, %y_m1
+ %mask = select i1 %cond, i8 %ymask, i8 15
+
+ %and = and i8 %mask, %x
+ %r = icmp ne i8 %and, %x
+ ret i1 %r
+}
+
+define i1 @src_is_mask_select_fail_wrong_pattern(i8 %x_in, i8 %y, i1 %cond, i8 %z) {
+; CHECK-LABEL: @src_is_mask_select_fail_wrong_pattern(
+; CHECK-NEXT: [[X:%.*]] = xor i8 [[X_IN:%.*]], 123
+; CHECK-NEXT: [[Y_M1:%.*]] = add i8 [[Y:%.*]], -1
+; CHECK-NEXT: [[YMASK:%.*]] = xor i8 [[Y_M1]], [[Y]]
+; CHECK-NEXT: [[MASK:%.*]] = select i1 [[COND:%.*]], i8 [[YMASK]], i8 15
+; CHECK-NEXT: [[AND:%.*]] = and i8 [[MASK]], [[X]]
+; CHECK-NEXT: [[R:%.*]] = icmp ne i8 [[AND]], [[Z:%.*]]
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %x = xor i8 %x_in, 123
+ %y_m1 = add i8 %y, -1
+ %ymask = xor i8 %y, %y_m1
+ %mask = select i1 %cond, i8 %ymask, i8 15
+
+ %and = and i8 %mask, %x
+ %r = icmp ne i8 %and, %z
+ ret i1 %r
+}
+
+define i1 @src_is_mask_shl_lshr(i8 %x_in, i8 %y, i1 %cond) {
+; CHECK-LABEL: @src_is_mask_shl_lshr(
+; CHECK-NEXT: [[X:%.*]] = xor i8 [[X_IN:%.*]], 122
+; CHECK-NEXT: [[TMP1:%.*]] = lshr i8 -1, [[Y:%.*]]
+; CHECK-NEXT: [[NOTMASK:%.*]] = xor i8 [[TMP1]], -1
+; CHECK-NEXT: [[AND:%.*]] = and i8 [[X]], [[NOTMASK]]
+; CHECK-NEXT: [[R:%.*]] = icmp ne i8 [[AND]], 0
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %x = xor i8 %x_in, 123
+ %m_shl = shl i8 -1, %y
+ %mask = lshr i8 %m_shl, %y
+ %notmask = xor i8 %mask, -1
+
+ %and = and i8 %x, %notmask
+ %r = icmp ne i8 0, %and
+ ret i1 %r
+}
+
+define i1 @src_is_mask_shl_lshr_fail_not_allones(i8 %x_in, i8 %y, i1 %cond) {
+; CHECK-LABEL: @src_is_mask_shl_lshr_fail_not_allones(
+; CHECK-NEXT: [[X:%.*]] = xor i8 [[X_IN:%.*]], 123
+; CHECK-NEXT: [[TMP1:%.*]] = lshr i8 -1, [[Y:%.*]]
+; CHECK-NEXT: [[MASK:%.*]] = and i8 [[TMP1]], -2
+; CHECK-NEXT: [[NOTMASK:%.*]] = xor i8 [[MASK]], -1
+; CHECK-NEXT: [[AND:%.*]] = and i8 [[X]], [[NOTMASK]]
+; CHECK-NEXT: [[R:%.*]] = icmp ne i8 [[AND]], 0
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %x = xor i8 %x_in, 123
+ %m_shl = shl i8 -2, %y
+ %mask = lshr i8 %m_shl, %y
+ %notmask = xor i8 %mask, -1
+
+ %and = and i8 %x, %notmask
+ %r = icmp ne i8 0, %and
+ ret i1 %r
+}
+
+define i1 @src_is_mask_lshr(i8 %x_in, i8 %y, i8 %z, i1 %cond) {
+; CHECK-LABEL: @src_is_mask_lshr(
+; CHECK-NEXT: [[X:%.*]] = xor i8 [[X_IN:%.*]], 123
+; CHECK-NEXT: [[Y_M1:%.*]] = add i8 [[Y:%.*]], -1
+; CHECK-NEXT: [[YMASK:%.*]] = xor i8 [[Y_M1]], [[Y]]
+; CHECK-NEXT: [[SMASK:%.*]] = select i1 [[COND:%.*]], i8 [[YMASK]], i8 15
+; CHECK-NEXT: [[MASK:%.*]] = lshr i8 [[SMASK]], [[Z:%.*]]
+; CHECK-NEXT: [[AND:%.*]] = and i8 [[MASK]], [[X]]
+; CHECK-NEXT: [[R:%.*]] = icmp ne i8 [[X]], [[AND]]
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %x = xor i8 %x_in, 123
+ %y_m1 = add i8 %y, -1
+ %ymask = xor i8 %y, %y_m1
+ %smask = select i1 %cond, i8 %ymask, i8 15
+ %mask = lshr i8 %smask, %z
+ %and = and i8 %mask, %x
+ %r = icmp ne i8 %x, %and
+ ret i1 %r
+}
+
+define i1 @src_is_mask_ashr(i8 %x_in, i8 %y, i8 %z, i1 %cond) {
+; CHECK-LABEL: @src_is_mask_ashr(
+; CHECK-NEXT: [[X:%.*]] = xor i8 [[X_IN:%.*]], 123
+; CHECK-NEXT: [[Y_M1:%.*]] = add i8 [[Y:%.*]], -1
+; CHECK-NEXT: [[YMASK:%.*]] = xor i8 [[Y_M1]], [[Y]]
+; CHECK-NEXT: [[SMASK:%.*]] = select i1 [[COND:%.*]], i8 [[YMASK]], i8 15
+; CHECK-NEXT: [[MASK:%.*]] = ashr i8 [[SMASK]], [[Z:%.*]]
+; CHECK-NEXT: [[AND:%.*]] = and i8 [[X]], [[MASK]]
+; CHECK-NEXT: [[R:%.*]] = icmp ne i8 [[AND]], [[X]]
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %x = xor i8 %x_in, 123
+ %y_m1 = add i8 %y, -1
+ %ymask = xor i8 %y, %y_m1
+ %smask = select i1 %cond, i8 %ymask, i8 15
+ %mask = ashr i8 %smask, %z
+ %and = and i8 %x, %mask
+ %r = icmp ult i8 %and, %x
+ ret i1 %r
+}
+
+define i1 @src_is_mask_p2_m1(i8 %x_in, i8 %y) {
+; CHECK-LABEL: @src_is_mask_p2_m1(
+; CHECK-NEXT: [[X:%.*]] = xor i8 [[X_IN:%.*]], 123
+; CHECK-NEXT: [[P2ORZ:%.*]] = shl i8 2, [[Y:%.*]]
+; CHECK-NEXT: [[MASK:%.*]] = add i8 [[P2ORZ]], -1
+; CHECK-NEXT: [[AND:%.*]] = and i8 [[MASK]], [[X]]
+; CHECK-NEXT: [[R:%.*]] = icmp ne i8 [[AND]], [[X]]
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %x = xor i8 %x_in, 123
+ %p2orz = shl i8 2, %y
+ %mask = add i8 %p2orz, -1
+ %and = and i8 %mask, %x
+ %r = icmp ult i8 %and, %x
+ ret i1 %r
+}
+
+define i1 @src_is_mask_umax(i8 %x_in, i8 %y) {
+; CHECK-LABEL: @src_is_mask_umax(
+; CHECK-NEXT: [[X:%.*]] = xor i8 [[X_IN:%.*]], 123
+; CHECK-NEXT: [[Y_M1:%.*]] = add i8 [[Y:%.*]], -1
+; CHECK-NEXT: [[YMASK:%.*]] = xor i8 [[Y_M1]], [[Y]]
+; CHECK-NEXT: [[MASK:%.*]] = call i8 @llvm.umax.i8(i8 [[YMASK]], i8 3)
+; CHECK-NEXT: [[AND:%.*]] = and i8 [[X]], [[MASK]]
+; CHECK-NEXT: [[R:%.*]] = icmp ne i8 [[AND]], [[X]]
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %x = xor i8 %x_in, 123
+ %y_m1 = add i8 %y, -1
+ %ymask = xor i8 %y, %y_m1
+ %mask = call i8 @llvm.umax.i8(i8 %ymask, i8 3)
+
+ %and = and i8 %x, %mask
+ %r = icmp ugt i8 %x, %and
+ ret i1 %r
+}
+
+define i1 @src_is_mask_umin(i8 %x_in, i8 %y, i8 %z) {
+; CHECK-LABEL: @src_is_mask_umin(
+; CHECK-NEXT: [[X:%.*]] = xor i8 [[X_IN:%.*]], 123
+; CHECK-NEXT: [[Y_M1:%.*]] = add i8 [[Y:%.*]], -1
+; CHECK-NEXT: [[YMASK:%.*]] = xor i8 [[Y_M1]], [[Y]]
+; CHECK-NEXT: [[ZMASK:%.*]] = lshr i8 15, [[Z:%.*]]
+; CHECK-NEXT: [[MASK:%.*]] = call i8 @llvm.umin.i8(i8 [[YMASK]], i8 [[ZMASK]])
+; CHECK-NEXT: [[AND:%.*]] = and i8 [[MASK]], [[X]]
+; CHECK-NEXT: [[R:%.*]] = icmp ne i8 [[AND]], [[X]]
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %x = xor i8 %x_in, 123
+ %y_m1 = add i8 %y, -1
+ %ymask = xor i8 %y, %y_m1
+ %zmask = lshr i8 15, %z
+ %mask = call i8 @llvm.umin.i8(i8 %ymask, i8 %zmask)
+
+ %and = and i8 %mask, %x
+ %r = icmp ugt i8 %x, %and
+ ret i1 %r
+}
+
+define i1 @src_is_mask_umin_fail_mismatch(i8 %x_in, i8 %y) {
+; CHECK-LABEL: @src_is_mask_umin_fail_mismatch(
+; CHECK-NEXT: [[X:%.*]] = xor i8 [[X_IN:%.*]], 123
+; CHECK-NEXT: [[Y_M1:%.*]] = add i8 [[Y:%.*]], -1
+; CHECK-NEXT: [[YMASK:%.*]] = xor i8 [[Y_M1]], [[Y]]
+; CHECK-NEXT: [[MASK:%.*]] = call i8 @llvm.umin.i8(i8 [[YMASK]], i8 -32)
+; CHECK-NEXT: [[AND:%.*]] = and i8 [[MASK]], [[X]]
+; CHECK-NEXT: [[R:%.*]] = icmp ne i8 [[AND]], [[X]]
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %x = xor i8 %x_in, 123
+ %y_m1 = add i8 %y, -1
+ %ymask = xor i8 %y, %y_m1
+ %mask = call i8 @llvm.umin.i8(i8 %ymask, i8 -32)
+
+ %and = and i8 %mask, %x
+ %r = icmp ugt i8 %x, %and
+ ret i1 %r
+}
+
+define i1 @src_is_mask_smax(i8 %x_in, i8 %y) {
+; CHECK-LABEL: @src_is_mask_smax(
+; CHECK-NEXT: [[X:%.*]] = xor i8 [[X_IN:%.*]], 123
+; CHECK-NEXT: [[Y_M1:%.*]] = add i8 [[Y:%.*]], -1
+; CHECK-NEXT: [[YMASK:%.*]] = xor i8 [[Y_M1]], [[Y]]
+; CHECK-NEXT: [[MASK:%.*]] = call i8 @llvm.smax.i8(i8 [[YMASK]], i8 -1)
+; CHECK-NEXT: [[AND:%.*]] = and i8 [[X]], [[MASK]]
+; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[AND]], [[X]]
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %x = xor i8 %x_in, 123
+ %y_m1 = add i8 %y, -1
+ %ymask = xor i8 %y, %y_m1
+ %mask = call i8 @llvm.smax.i8(i8 %ymask, i8 -1)
+
+ %and = and i8 %x, %mask
+ %r = icmp uge i8 %and, %x
+ ret i1 %r
+}
+
+define i1 @src_is_mask_smin(i8 %x_in, i8 %y) {
+; CHECK-LABEL: @src_is_mask_smin(
+; CHECK-NEXT: [[X:%.*]] = xor i8 [[X_IN:%.*]], 123
+; CHECK-NEXT: [[Y_M1:%.*]] = add i8 [[Y:%.*]], -1
+; CHECK-NEXT: [[YMASK:%.*]] = xor i8 [[Y_M1]], [[Y]]
+; CHECK-NEXT: [[MASK:%.*]] = call i8 @llvm.smin.i8(i8 [[YMASK]], i8 0)
+; CHECK-NEXT: [[AND:%.*]] = and i8 [[MASK]], [[X]]
+; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[AND]], [[X]]
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %x = xor i8 %x_in, 123
+ %y_m1 = add i8 %y, -1
+ %ymask = xor i8 %y, %y_m1
+ %mask = call i8 @llvm.smin.i8(i8 %ymask, i8 0)
+
+ %and = and i8 %mask, %x
+ %r = icmp uge i8 %and, %x
+ ret i1 %r
+}
+
+define i1 @src_is_mask_bitreverse_not_mask(i8 %x_in, i8 %y) {
+; CHECK-LABEL: @src_is_mask_bitreverse_not_mask(
+; CHECK-NEXT: [[X:%.*]] = xor i8 [[X_IN:%.*]], 123
+; CHECK-NEXT: [[NMASK:%.*]] = shl nsw i8 -1, [[Y:%.*]]
+; CHECK-NEXT: [[MASK:%.*]] = call i8 @llvm.bitreverse.i8(i8 [[NMASK]])
+; CHECK-NEXT: [[AND:%.*]] = and i8 [[X]], [[MASK]]
+; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[AND]], [[X]]
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %x = xor i8 %x_in, 123
+ %nmask = shl i8 -1, %y
+ %mask = call i8 @llvm.bitreverse.i8(i8 %nmask)
+
+ %and = and i8 %x, %mask
+ %r = icmp ule i8 %x, %and
+ ret i1 %r
+}
+
+define i1 @src_is_notmask_sext(i16 %x_in, i8 %y) {
+; CHECK-LABEL: @src_is_notmask_sext(
+; CHECK-NEXT: [[X:%.*]] = xor i16 [[X_IN:%.*]], 123
+; CHECK-NEXT: [[M_IN:%.*]] = shl i8 -8, [[Y:%.*]]
+; CHECK-NEXT: [[TMP1:%.*]] = xor i8 [[M_IN]], -1
+; CHECK-NEXT: [[MASK:%.*]] = sext i8 [[TMP1]] to i16
+; CHECK-NEXT: [[AND:%.*]] = and i16 [[X]], [[MASK]]
+; CHECK-NEXT: [[R:%.*]] = icmp eq i16 [[AND]], [[X]]
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %x = xor i16 %x_in, 123
+ %m_in = shl i8 -8, %y
+ %nmask = sext i8 %m_in to i16
+ %mask = xor i16 %nmask, -1
+ %and = and i16 %mask, %x
+ %r = icmp ule i16 %x, %and
+ ret i1 %r
+}
+
+define i1 @src_is_notmask_shl(i8 %x_in, i8 %y, i1 %cond) {
+; CHECK-LABEL: @src_is_notmask_shl(
+; CHECK-NEXT: [[X:%.*]] = xor i8 [[X_IN:%.*]], 122
+; CHECK-NEXT: [[NMASK:%.*]] = shl nsw i8 -1, [[Y:%.*]]
+; CHECK-NEXT: [[TMP1:%.*]] = xor i8 [[NMASK]], -1
+; CHECK-NEXT: [[NOTMASK0:%.*]] = call i8 @llvm.bitreverse.i8(i8 [[TMP1]])
+; CHECK-NEXT: [[NOTMASK:%.*]] = select i1 [[COND:%.*]], i8 [[NOTMASK0]], i8 -8
+; CHECK-NEXT: [[AND:%.*]] = and i8 [[X]], [[NOTMASK]]
+; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[AND]], 0
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %x = xor i8 %x_in, 123
+ %nmask = shl i8 -1, %y
+ %mask = call i8 @llvm.bitreverse.i8(i8 %nmask)
+ %notmask0 = xor i8 %mask, -1
+ %notmask = select i1 %cond, i8 %notmask0, i8 -8
+ %and = and i8 %x, %notmask
+ %r = icmp eq i8 %and, 0
+ ret i1 %r
+}
+
+define i1 @src_is_notmask_shl_fail_multiuse_invert(i8 %x_in, i8 %y, i1 %cond) {
+; CHECK-LABEL: @src_is_notmask_shl_fail_multiuse_invert(
+; CHECK-NEXT: [[X:%.*]] = xor i8 [[X_IN:%.*]], 122
+; CHECK-NEXT: [[NMASK:%.*]] = shl nsw i8 -1, [[Y:%.*]]
+; CHECK-NEXT: [[TMP1:%.*]] = xor i8 [[NMASK]], -1
+; CHECK-NEXT: [[NOTMASK0:%.*]] = call i8 @llvm.bitreverse.i8(i8 [[TMP1]])
+; CHECK-NEXT: [[NOTMASK:%.*]] = select i1 [[COND:%.*]], i8 [[NOTMASK0]], i8 -8
+; CHECK-NEXT: call void @use.i8(i8 [[NOTMASK]])
+; CHECK-NEXT: [[AND:%.*]] = and i8 [[X]], [[NOTMASK]]
+; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[AND]], 0
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %x = xor i8 %x_in, 123
+ %nmask = shl i8 -1, %y
+ %mask = call i8 @llvm.bitreverse.i8(i8 %nmask)
+ %notmask0 = xor i8 %mask, -1
+ %notmask = select i1 %cond, i8 %notmask0, i8 -8
+ call void @use.i8(i8 %notmask)
+ %and = and i8 %x, %notmask
+ %r = icmp eq i8 %and, 0
+ ret i1 %r
+}
+
+define i1 @src_is_notmask_lshr_shl(i8 %x_in, i8 %y) {
+; CHECK-LABEL: @src_is_notmask_lshr_shl(
+; CHECK-NEXT: [[TMP1:%.*]] = shl nsw i8 -1, [[Y:%.*]]
+; CHECK-NEXT: [[TMP2:%.*]] = xor i8 [[X_IN:%.*]], -124
+; CHECK-NEXT: [[R:%.*]] = icmp uge i8 [[TMP2]], [[TMP1]]
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %x = xor i8 %x_in, 123
+ %mask_shr = lshr i8 -1, %y
+ %nmask = shl i8 %mask_shr, %y
+ %mask = xor i8 %nmask, -1
+ %and = and i8 %mask, %x
+ %r = icmp eq i8 %and, %x
+ ret i1 %r
+}
+
+define i1 @src_is_notmask_lshr_shl_fail_mismatch_shifts(i8 %x_in, i8 %y, i8 %z) {
+; CHECK-LABEL: @src_is_notmask_lshr_shl_fail_mismatch_shifts(
+; CHECK-NEXT: [[X:%.*]] = xor i8 [[X_IN:%.*]], 123
+; CHECK-NEXT: [[MASK_SHR:%.*]] = lshr i8 -1, [[Y:%.*]]
+; CHECK-NEXT: [[NMASK:%.*]] = shl i8 [[MASK_SHR]], [[Z:%.*]]
+; CHECK-NEXT: [[MASK:%.*]] = xor i8 [[NMASK]], -1
+; CHECK-NEXT: [[AND:%.*]] = and i8 [[X]], [[MASK]]
+; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[AND]], [[X]]
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %x = xor i8 %x_in, 123
+ %mask_shr = lshr i8 -1, %y
+ %nmask = shl i8 %mask_shr, %z
+ %mask = xor i8 %nmask, -1
+ %and = and i8 %mask, %x
+ %r = icmp eq i8 %and, %x
+ ret i1 %r
+}
+
+define i1 @src_is_notmask_ashr(i16 %x_in, i8 %y, i16 %z) {
+; CHECK-LABEL: @src_is_notmask_ashr(
+; CHECK-NEXT: [[X:%.*]] = xor i16 [[X_IN:%.*]], 123
+; CHECK-NEXT: [[M_IN:%.*]] = shl i8 -32, [[Y:%.*]]
+; CHECK-NEXT: [[NMASK:%.*]] = sext i8 [[M_IN]] to i16
+; CHECK-NEXT: [[NMASK_SHR:%.*]] = ashr i16 [[NMASK]], [[Z:%.*]]
+; CHECK-NEXT: [[MASK:%.*]] = xor i16 [[NMASK_SHR]], -1
+; CHECK-NEXT: [[AND:%.*]] = and i16 [[X]], [[MASK]]
+; CHECK-NEXT: [[R:%.*]] = icmp eq i16 [[X]], [[AND]]
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %x = xor i16 %x_in, 123
+ %m_in = shl i8 -32, %y
+ %nmask = sext i8 %m_in to i16
+ %nmask_shr = ashr i16 %nmask, %z
+ %mask = xor i16 %nmask_shr, -1
+ %and = and i16 %x, %mask
+ %r = icmp eq i16 %x, %and
+ ret i1 %r
+}
+
+define i1 @src_is_notmask_neg_p2(i8 %x_in, i8 %y) {
+; CHECK-LABEL: @src_is_notmask_neg_p2(
+; CHECK-NEXT: [[X:%.*]] = xor i8 [[X_IN:%.*]], 123
+; CHECK-NEXT: [[TMP1:%.*]] = add i8 [[Y:%.*]], -1
+; CHECK-NEXT: [[TMP2:%.*]] = xor i8 [[Y]], -1
+; CHECK-NEXT: [[TMP3:%.*]] = and i8 [[TMP1]], [[TMP2]]
+; CHECK-NEXT: [[NOTMASK:%.*]] = call i8 @llvm.bitreverse.i8(i8 [[TMP3]])
+; CHECK-NEXT: [[AND:%.*]] = and i8 [[NOTMASK]], [[X]]
+; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[AND]], 0
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %x = xor i8 %x_in, 123
+ %ny = sub i8 0, %y
+ %p2 = and i8 %ny, %y
+ %nmask = sub i8 0, %p2
+ %mask = call i8 @llvm.bitreverse.i8(i8 %nmask)
+ %notmask = xor i8 %mask, -1
+ %and = and i8 %notmask, %x
+ %r = icmp eq i8 0, %and
+ ret i1 %r
+}
+
+define i1 @src_is_notmask_neg_p2_fail_not_invertable(i8 %x_in, i8 %y) {
+; CHECK-LABEL: @src_is_notmask_neg_p2_fail_not_invertable(
+; CHECK-NEXT: [[X:%.*]] = xor i8 [[X_IN:%.*]], 123
+; CHECK-NEXT: [[NY:%.*]] = sub i8 0, [[Y:%.*]]
+; CHECK-NEXT: [[P2:%.*]] = and i8 [[NY]], [[Y]]
+; CHECK-NEXT: [[NOTMASK:%.*]] = sub i8 0, [[P2]]
+; CHECK-NEXT: [[AND:%.*]] = and i8 [[X]], [[NOTMASK]]
+; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[AND]], 0
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %x = xor i8 %x_in, 123
+ %ny = sub i8 0, %y
+ %p2 = and i8 %ny, %y
+ %notmask = sub i8 0, %p2
+ %and = and i8 %notmask, %x
+ %r = icmp eq i8 0, %and
+ ret i1 %r
+}
+
+define i1 @src_is_mask_const_slt(i8 %x_in) {
+; CHECK-LABEL: @src_is_mask_const_slt(
+; CHECK-NEXT: [[X:%.*]] = xor i8 [[X_IN:%.*]], 123
+; CHECK-NEXT: [[AND:%.*]] = and i8 [[X]], 7
+; CHECK-NEXT: [[R:%.*]] = icmp slt i8 [[X]], [[AND]]
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %x = xor i8 %x_in, 123
+ %and = and i8 %x, 7
+ %r = icmp slt i8 %x, %and
+ ret i1 %r
+}
+
+define i1 @src_is_mask_const_sgt(i8 %x_in) {
+; CHECK-LABEL: @src_is_mask_const_sgt(
+; CHECK-NEXT: [[X:%.*]] = xor i8 [[X_IN:%.*]], 123
+; CHECK-NEXT: [[R:%.*]] = icmp sgt i8 [[X]], 7
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %x = xor i8 %x_in, 123
+ %and = and i8 %x, 7
+ %r = icmp sgt i8 %x, %and
+ ret i1 %r
+}
+
+define i1 @src_is_mask_const_sle(i8 %x_in) {
+; CHECK-LABEL: @src_is_mask_const_sle(
+; CHECK-NEXT: [[X:%.*]] = xor i8 [[X_IN:%.*]], 123
+; CHECK-NEXT: [[AND:%.*]] = and i8 [[X]], 31
+; CHECK-NEXT: [[R:%.*]] = icmp sle i8 [[AND]], [[X]]
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %x = xor i8 %x_in, 123
+ %and = and i8 %x, 31
+ %r = icmp sle i8 %and, %x
+ ret i1 %r
+}
+
+define i1 @src_is_mask_const_sge(i8 %x_in) {
+; CHECK-LABEL: @src_is_mask_const_sge(
+; CHECK-NEXT: [[X:%.*]] = xor i8 [[X_IN:%.*]], 123
+; CHECK-NEXT: [[R:%.*]] = icmp slt i8 [[X]], 32
+; CHECK-NEXT: ret i1 [[R]]
+;
+ %x = xor i8 %x_in, 123
+ %and = and i8 %x, 31
+ %r = icmp sge i8 %and, %x
+ ret i1 %r
+}
>From 2a5aefdf8eec1c35928f4c8cfd843bfa0acb8a91 Mon Sep 17 00:00:00 2001
From: Noah Goldstein <goldstein.w.n at gmail.com>
Date: Wed, 13 Sep 2023 13:45:52 -0500
Subject: [PATCH 2/3] [InstCombine] Improve mask detection in
`foldICmpWithLowBitMaskedVal`
Make recursive matcher that is able to detect a lot more patterns.
Proofs for all supported patterns: https://alive2.llvm.org/ce/z/fSQ3nZ
Differential Revision: https://reviews.llvm.org/D159058
---
llvm/include/llvm/IR/PatternMatch.h | 25 +++
.../InstCombine/InstCombineCompares.cpp | 149 ++++++++++++++++--
...nt-low-bit-mask-and-icmp-eq-to-icmp-ule.ll | 3 +-
...nt-low-bit-mask-and-icmp-ne-to-icmp-ugt.ll | 3 +-
...t-low-bit-mask-and-icmp-sge-to-icmp-sle.ll | 3 +-
...t-low-bit-mask-and-icmp-sgt-to-icmp-sgt.ll | 3 +-
...t-low-bit-mask-and-icmp-sle-to-icmp-sle.ll | 3 +-
...t-low-bit-mask-and-icmp-slt-to-icmp-sgt.ll | 3 +-
...t-low-bit-mask-and-icmp-uge-to-icmp-ule.ll | 3 +-
...t-low-bit-mask-and-icmp-ugt-to-icmp-ugt.ll | 3 +-
...t-low-bit-mask-and-icmp-ule-to-icmp-ule.ll | 3 +-
...t-low-bit-mask-and-icmp-ult-to-icmp-ugt.ll | 3 +-
.../InstCombine/icmp-and-lowbit-mask.ll | 48 ++----
13 files changed, 185 insertions(+), 67 deletions(-)
diff --git a/llvm/include/llvm/IR/PatternMatch.h b/llvm/include/llvm/IR/PatternMatch.h
index fed552414298ad..487ae170210de9 100644
--- a/llvm/include/llvm/IR/PatternMatch.h
+++ b/llvm/include/llvm/IR/PatternMatch.h
@@ -564,6 +564,19 @@ inline api_pred_ty<is_negated_power2> m_NegatedPower2(const APInt *&V) {
return V;
}
+struct is_negated_power2_or_zero {
+ bool isValue(const APInt &C) { return !C || C.isNegatedPowerOf2(); }
+};
+/// Match a integer or vector negated power-of-2.
+/// For vectors, this includes constants with undefined elements.
+inline cst_pred_ty<is_negated_power2_or_zero> m_NegatedPower2OrZero() {
+ return cst_pred_ty<is_negated_power2_or_zero>();
+}
+inline api_pred_ty<is_negated_power2_or_zero>
+m_NegatedPower2OrZero(const APInt *&V) {
+ return V;
+}
+
struct is_power2_or_zero {
bool isValue(const APInt &C) { return !C || C.isPowerOf2(); }
};
@@ -595,6 +608,18 @@ inline cst_pred_ty<is_lowbit_mask> m_LowBitMask() {
}
inline api_pred_ty<is_lowbit_mask> m_LowBitMask(const APInt *&V) { return V; }
+struct is_lowbit_mask_or_zero {
+ bool isValue(const APInt &C) { return !C || C.isMask(); }
+};
+/// Match an integer or vector with only the low bit(s) set.
+/// For vectors, this includes constants with undefined elements.
+inline cst_pred_ty<is_lowbit_mask_or_zero> m_LowBitMaskOrZero() {
+ return cst_pred_ty<is_lowbit_mask_or_zero>();
+}
+inline api_pred_ty<is_lowbit_mask_or_zero> m_LowBitMaskOrZero(const APInt *&V) {
+ return V;
+}
+
struct icmp_pred_with_threshold {
ICmpInst::Predicate Pred;
const APInt *Thr;
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
index 280c4d77b6dfca..535a5146fa9415 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
@@ -4068,6 +4068,109 @@ Instruction *InstCombinerImpl::foldSelectICmp(ICmpInst::Predicate Pred,
return nullptr;
}
+// Returns of V is a Mask ((X + 1) & X == 0) or ~Mask (-Pow2OrZero)
+static bool isMaskOrZero(const Value *V, bool Not, const SimplifyQuery &Q,
+ unsigned Depth = 0) {
+ if (Not ? match(V, m_NegatedPower2OrZero()) : match(V, m_LowBitMaskOrZero()))
+ return true;
+ if (V->getType()->getScalarSizeInBits() == 1)
+ return true;
+ if (Depth++ >= MaxAnalysisRecursionDepth)
+ return false;
+ Value *X;
+ if (match(V, m_Not(m_Value(X))))
+ return isMaskOrZero(X, !Not, Q, Depth);
+ const Operator *I = dyn_cast<Operator>(V);
+ if (I == nullptr)
+ return false;
+ switch (I->getOpcode()) {
+ case Instruction::ZExt:
+ // ZExt(Mask) is a Mask.
+ return !Not && isMaskOrZero(I->getOperand(0), Not, Q, Depth);
+ case Instruction::SExt:
+ // SExt(Mask) is a Mask.
+ // SExt(~Mask) is a ~Mask.
+ return isMaskOrZero(I->getOperand(0), Not, Q, Depth);
+ case Instruction::And:
+ case Instruction::Or:
+ // Mask0 | Mask1 is a Mask.
+ // Mask0 & Mask1 is a Mask.
+ // ~Mask0 | ~Mask1 is a ~Mask.
+ // ~Mask0 & ~Mask1 is a ~Mask.
+ return isMaskOrZero(I->getOperand(1), Not, Q, Depth) &&
+ isMaskOrZero(I->getOperand(0), Not, Q, Depth);
+ case Instruction::Xor:
+ // (X ^ (X - 1)) is a Mask
+ return match(V, m_c_Xor(m_Value(X), m_Add(m_Deferred(X), m_AllOnes())));
+ case Instruction::Select:
+ // c ? Mask0 : Mask1 is a Mask.
+ return isMaskOrZero(I->getOperand(1), Not, Q, Depth) &&
+ isMaskOrZero(I->getOperand(2), Not, Q, Depth);
+ case Instruction::Shl:
+ if (Not) {
+ // (-1 >> X) << X is ~Mask
+ if (match(I->getOperand(0),
+ m_Shr(m_AllOnes(), m_Specific(I->getOperand(1)))))
+ return true;
+
+ // (~Mask) << X is a ~Mask.
+ return isMaskOrZero(I->getOperand(0), Not, Q, Depth);
+ }
+ break;
+ case Instruction::LShr:
+ if (!Not) {
+ // (-1 << X) >> X is a Mask
+ if (match(I->getOperand(0),
+ m_Shl(m_AllOnes(), m_Specific(I->getOperand(1)))))
+ return true;
+ // Mask >> X is a Mask.
+ return isMaskOrZero(I->getOperand(0), Not, Q, Depth);
+ }
+ return false;
+ case Instruction::AShr:
+ // Mask s>> X is a Mask.
+ // ~Mask s>> X is a ~Mask.
+ return isMaskOrZero(I->getOperand(0), Not, Q, Depth);
+ case Instruction::Add:
+ // Pow2 - 1 is a Mask.
+ if (!Not && match(I->getOperand(1), m_AllOnes()))
+ return isKnownToBeAPowerOfTwo(I->getOperand(0), Q.DL, /*OrZero*/ true,
+ Depth, Q.AC, Q.CxtI, Q.DT);
+ break;
+ case Instruction::Sub:
+ // -Pow2 is a ~Mask.
+ if (Not && match(I->getOperand(0), m_Zero()))
+ return isKnownToBeAPowerOfTwo(I->getOperand(1), Q.DL, /*OrZero*/ true,
+ Depth, Q.AC, Q.CxtI, Q.DT);
+ break;
+ case Instruction::Invoke:
+ case Instruction::Call: {
+ if (auto *II = dyn_cast<IntrinsicInst>(I)) {
+ switch (II->getIntrinsicID()) {
+ // min/max(Mask0, Mask1) is a Mask.
+ // min/max(~Mask0, ~Mask1) is a ~Mask.
+ case Intrinsic::umax:
+ case Intrinsic::smax:
+ case Intrinsic::umin:
+ case Intrinsic::smin:
+ return isMaskOrZero(II->getArgOperand(1), Not, Q, Depth) &&
+ isMaskOrZero(II->getArgOperand(0), Not, Q, Depth);
+
+ // In the context of masks, bitreverse(Mask) == ~Mask
+ case Intrinsic::bitreverse:
+ return isMaskOrZero(II->getArgOperand(0), !Not, Q, Depth);
+ default:
+ break;
+ }
+ }
+ break;
+ }
+ default:
+ break;
+ }
+ return false;
+}
+
/// Some comparisons can be simplified.
/// In this case, we are looking for comparisons that look like
/// a check for a lossy truncation.
@@ -4081,21 +4184,35 @@ Instruction *InstCombinerImpl::foldSelectICmp(ICmpInst::Predicate Pred,
/// The Mask can be a constant, too.
/// For some predicates, the operands are commutative.
/// For others, x can only be on a specific side.
-static Value *foldICmpWithLowBitMaskedVal(ICmpInst &I,
- InstCombiner::BuilderTy &Builder) {
+static Value *foldICmpWithLowBitMaskedVal(ICmpInst &I, const SimplifyQuery &Q,
+ InstCombiner &IC) {
+
+ Value *X, *M;
+ ICmpInst::Predicate Pred = I.getPredicate();
ICmpInst::Predicate SrcPred;
- Value *X, *M, *Y;
- auto m_VariableMask = m_CombineOr(
- m_CombineOr(m_Not(m_Shl(m_AllOnes(), m_Value())),
- m_Add(m_Shl(m_One(), m_Value()), m_AllOnes())),
- m_CombineOr(m_LShr(m_AllOnes(), m_Value()),
- m_LShr(m_Shl(m_AllOnes(), m_Value(Y)), m_Deferred(Y))));
- auto m_Mask = m_CombineOr(m_VariableMask, m_LowBitMask());
- if (!match(&I, m_c_ICmp(SrcPred,
- m_c_And(m_CombineAnd(m_Mask, m_Value(M)), m_Value(X)),
- m_Deferred(X))))
- return nullptr;
+ bool NeedsNot = false;
+
+ auto CheckMask = [&](Value *V, bool Not) {
+ if (!ICmpInst::isSigned(Pred))
+ return isMaskOrZero(V, Not, Q);
+ return Not ? match(V, m_NegatedPower2OrZero())
+ : match(V, m_LowBitMaskOrZero());
+ };
+ auto TryMatch = [&](unsigned OpNo) {
+ SrcPred = Pred;
+ if (match(I.getOperand(OpNo),
+ m_c_And(m_Specific(I.getOperand(1 - OpNo)), m_Value(M)))) {
+ X = I.getOperand(1 - OpNo);
+ if (OpNo)
+ SrcPred = ICmpInst::getSwappedPredicate(Pred);
+ return CheckMask(M, /*Not*/ false);
+ }
+ return false;
+ };
+
+ if (!TryMatch(0) && !TryMatch(1))
+ return nullptr;
ICmpInst::Predicate DstPred;
switch (SrcPred) {
case ICmpInst::Predicate::ICMP_EQ:
@@ -4163,7 +4280,9 @@ static Value *foldICmpWithLowBitMaskedVal(ICmpInst &I,
M = Constant::replaceUndefsWith(VecC, SafeReplacementConstant);
}
- return Builder.CreateICmp(DstPred, X, M);
+ if (NeedsNot)
+ M = IC.Builder.CreateNot(M);
+ return IC.Builder.CreateICmp(DstPred, X, M);
}
/// Some comparisons can be simplified.
@@ -5080,7 +5199,7 @@ Instruction *InstCombinerImpl::foldICmpBinOp(ICmpInst &I,
if (Value *V = foldMultiplicationOverflowCheck(I))
return replaceInstUsesWith(I, V);
- if (Value *V = foldICmpWithLowBitMaskedVal(I, Builder))
+ if (Value *V = foldICmpWithLowBitMaskedVal(I, Q, *this))
return replaceInstUsesWith(I, V);
if (Instruction *R = foldICmpAndXX(I, Q, *this))
diff --git a/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-eq-to-icmp-ule.ll b/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-eq-to-icmp-ule.ll
index a957fb2d088ef4..5b7a99d53c308c 100644
--- a/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-eq-to-icmp-ule.ll
+++ b/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-eq-to-icmp-ule.ll
@@ -62,8 +62,7 @@ define <2 x i1> @p2_vec_nonsplat(<2 x i8> %x) {
define <2 x i1> @p2_vec_nonsplat_edgecase0(<2 x i8> %x) {
; CHECK-LABEL: @p2_vec_nonsplat_edgecase0(
-; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i8> [[X:%.*]], <i8 -4, i8 -1>
-; CHECK-NEXT: [[RET:%.*]] = icmp eq <2 x i8> [[TMP1]], zeroinitializer
+; CHECK-NEXT: [[RET:%.*]] = icmp ult <2 x i8> [[X:%.*]], <i8 4, i8 1>
; CHECK-NEXT: ret <2 x i1> [[RET]]
;
%tmp0 = and <2 x i8> %x, <i8 3, i8 0>
diff --git a/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ne-to-icmp-ugt.ll b/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ne-to-icmp-ugt.ll
index 57361cdf38977c..160d968b9ac4c7 100644
--- a/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ne-to-icmp-ugt.ll
+++ b/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ne-to-icmp-ugt.ll
@@ -62,8 +62,7 @@ define <2 x i1> @p2_vec_nonsplat(<2 x i8> %x) {
define <2 x i1> @p2_vec_nonsplat_edgecase0(<2 x i8> %x) {
; CHECK-LABEL: @p2_vec_nonsplat_edgecase0(
-; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i8> [[X:%.*]], <i8 -4, i8 -1>
-; CHECK-NEXT: [[RET:%.*]] = icmp ne <2 x i8> [[TMP1]], zeroinitializer
+; CHECK-NEXT: [[RET:%.*]] = icmp ugt <2 x i8> [[X:%.*]], <i8 3, i8 0>
; CHECK-NEXT: ret <2 x i1> [[RET]]
;
%tmp0 = and <2 x i8> %x, <i8 3, i8 0>
diff --git a/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-sge-to-icmp-sle.ll b/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-sge-to-icmp-sle.ll
index 0dfc9f51baf9c2..60921042d52435 100644
--- a/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-sge-to-icmp-sle.ll
+++ b/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-sge-to-icmp-sle.ll
@@ -50,8 +50,7 @@ define <2 x i1> @p2_vec_nonsplat(<2 x i8> %x) {
define <2 x i1> @p2_vec_nonsplat_edgecase(<2 x i8> %x) {
; CHECK-LABEL: @p2_vec_nonsplat_edgecase(
-; CHECK-NEXT: [[TMP0:%.*]] = and <2 x i8> [[X:%.*]], <i8 3, i8 0>
-; CHECK-NEXT: [[RET:%.*]] = icmp sge <2 x i8> [[TMP0]], [[X]]
+; CHECK-NEXT: [[RET:%.*]] = icmp slt <2 x i8> [[X:%.*]], <i8 4, i8 1>
; CHECK-NEXT: ret <2 x i1> [[RET]]
;
%tmp0 = and <2 x i8> %x, <i8 3, i8 0>
diff --git a/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-sgt-to-icmp-sgt.ll b/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-sgt-to-icmp-sgt.ll
index e0893ce4cf2ecb..6345e70d7220e2 100644
--- a/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-sgt-to-icmp-sgt.ll
+++ b/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-sgt-to-icmp-sgt.ll
@@ -63,8 +63,7 @@ define <2 x i1> @p2_vec_nonsplat() {
define <2 x i1> @p2_vec_nonsplat_edgecase() {
; CHECK-LABEL: @p2_vec_nonsplat_edgecase(
; CHECK-NEXT: [[X:%.*]] = call <2 x i8> @gen2x8()
-; CHECK-NEXT: [[TMP0:%.*]] = and <2 x i8> [[X]], <i8 3, i8 0>
-; CHECK-NEXT: [[RET:%.*]] = icmp sgt <2 x i8> [[X]], [[TMP0]]
+; CHECK-NEXT: [[RET:%.*]] = icmp sgt <2 x i8> [[X]], <i8 3, i8 0>
; CHECK-NEXT: ret <2 x i1> [[RET]]
;
%x = call <2 x i8> @gen2x8()
diff --git a/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-sle-to-icmp-sle.ll b/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-sle-to-icmp-sle.ll
index 81887a39091573..b7aec53fed6760 100644
--- a/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-sle-to-icmp-sle.ll
+++ b/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-sle-to-icmp-sle.ll
@@ -63,8 +63,7 @@ define <2 x i1> @p2_vec_nonsplat() {
define <2 x i1> @p2_vec_nonsplat_edgecase() {
; CHECK-LABEL: @p2_vec_nonsplat_edgecase(
; CHECK-NEXT: [[X:%.*]] = call <2 x i8> @gen2x8()
-; CHECK-NEXT: [[TMP0:%.*]] = and <2 x i8> [[X]], <i8 3, i8 0>
-; CHECK-NEXT: [[RET:%.*]] = icmp sle <2 x i8> [[X]], [[TMP0]]
+; CHECK-NEXT: [[RET:%.*]] = icmp slt <2 x i8> [[X]], <i8 4, i8 1>
; CHECK-NEXT: ret <2 x i1> [[RET]]
;
%x = call <2 x i8> @gen2x8()
diff --git a/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-slt-to-icmp-sgt.ll b/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-slt-to-icmp-sgt.ll
index 8ce8687f198446..56661d335c4f60 100644
--- a/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-slt-to-icmp-sgt.ll
+++ b/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-slt-to-icmp-sgt.ll
@@ -50,8 +50,7 @@ define <2 x i1> @p2_vec_nonsplat(<2 x i8> %x) {
define <2 x i1> @p2_vec_nonsplat_edgecase(<2 x i8> %x) {
; CHECK-LABEL: @p2_vec_nonsplat_edgecase(
-; CHECK-NEXT: [[TMP0:%.*]] = and <2 x i8> [[X:%.*]], <i8 3, i8 0>
-; CHECK-NEXT: [[RET:%.*]] = icmp slt <2 x i8> [[TMP0]], [[X]]
+; CHECK-NEXT: [[RET:%.*]] = icmp sgt <2 x i8> [[X:%.*]], <i8 3, i8 0>
; CHECK-NEXT: ret <2 x i1> [[RET]]
;
%tmp0 = and <2 x i8> %x, <i8 3, i8 0>
diff --git a/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-uge-to-icmp-ule.ll b/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-uge-to-icmp-ule.ll
index ff09e255185b5a..a93e8f779435fc 100644
--- a/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-uge-to-icmp-ule.ll
+++ b/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-uge-to-icmp-ule.ll
@@ -62,8 +62,7 @@ define <2 x i1> @p2_vec_nonsplat(<2 x i8> %x) {
define <2 x i1> @p2_vec_nonsplat_edgecase0(<2 x i8> %x) {
; CHECK-LABEL: @p2_vec_nonsplat_edgecase0(
-; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i8> [[X:%.*]], <i8 -4, i8 -1>
-; CHECK-NEXT: [[RET:%.*]] = icmp eq <2 x i8> [[TMP1]], zeroinitializer
+; CHECK-NEXT: [[RET:%.*]] = icmp ult <2 x i8> [[X:%.*]], <i8 4, i8 1>
; CHECK-NEXT: ret <2 x i1> [[RET]]
;
%tmp0 = and <2 x i8> %x, <i8 3, i8 0>
diff --git a/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ugt-to-icmp-ugt.ll b/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ugt-to-icmp-ugt.ll
index 4ad04710fd7bb9..73ea4d456d2462 100644
--- a/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ugt-to-icmp-ugt.ll
+++ b/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ugt-to-icmp-ugt.ll
@@ -75,8 +75,7 @@ define <2 x i1> @p2_vec_nonsplat() {
define <2 x i1> @p2_vec_nonsplat_edgecase0() {
; CHECK-LABEL: @p2_vec_nonsplat_edgecase0(
; CHECK-NEXT: [[X:%.*]] = call <2 x i8> @gen2x8()
-; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i8> [[X]], <i8 -4, i8 -1>
-; CHECK-NEXT: [[RET:%.*]] = icmp ne <2 x i8> [[TMP1]], zeroinitializer
+; CHECK-NEXT: [[RET:%.*]] = icmp ugt <2 x i8> [[X]], <i8 3, i8 0>
; CHECK-NEXT: ret <2 x i1> [[RET]]
;
%x = call <2 x i8> @gen2x8()
diff --git a/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ule-to-icmp-ule.ll b/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ule-to-icmp-ule.ll
index 8e513dcbf4ef3a..53886b5f2dc9c3 100644
--- a/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ule-to-icmp-ule.ll
+++ b/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ule-to-icmp-ule.ll
@@ -75,8 +75,7 @@ define <2 x i1> @p2_vec_nonsplat() {
define <2 x i1> @p2_vec_nonsplat_edgecase0() {
; CHECK-LABEL: @p2_vec_nonsplat_edgecase0(
; CHECK-NEXT: [[X:%.*]] = call <2 x i8> @gen2x8()
-; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i8> [[X]], <i8 -4, i8 -1>
-; CHECK-NEXT: [[RET:%.*]] = icmp eq <2 x i8> [[TMP1]], zeroinitializer
+; CHECK-NEXT: [[RET:%.*]] = icmp ult <2 x i8> [[X]], <i8 4, i8 1>
; CHECK-NEXT: ret <2 x i1> [[RET]]
;
%x = call <2 x i8> @gen2x8()
diff --git a/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ult-to-icmp-ugt.ll b/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ult-to-icmp-ugt.ll
index d02ecf6965e878..d66be571008c2f 100644
--- a/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ult-to-icmp-ugt.ll
+++ b/llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ult-to-icmp-ugt.ll
@@ -62,8 +62,7 @@ define <2 x i1> @p2_vec_nonsplat(<2 x i8> %x) {
define <2 x i1> @p2_vec_nonsplat_edgecase0(<2 x i8> %x) {
; CHECK-LABEL: @p2_vec_nonsplat_edgecase0(
-; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i8> [[X:%.*]], <i8 -4, i8 -1>
-; CHECK-NEXT: [[RET:%.*]] = icmp ne <2 x i8> [[TMP1]], zeroinitializer
+; CHECK-NEXT: [[RET:%.*]] = icmp ugt <2 x i8> [[X:%.*]], <i8 3, i8 0>
; CHECK-NEXT: ret <2 x i1> [[RET]]
;
%tmp0 = and <2 x i8> %x, <i8 3, i8 0>
diff --git a/llvm/test/Transforms/InstCombine/icmp-and-lowbit-mask.ll b/llvm/test/Transforms/InstCombine/icmp-and-lowbit-mask.ll
index b98cdb50cf7859..ca378ec8b681f0 100644
--- a/llvm/test/Transforms/InstCombine/icmp-and-lowbit-mask.ll
+++ b/llvm/test/Transforms/InstCombine/icmp-and-lowbit-mask.ll
@@ -15,8 +15,7 @@ define i1 @src_is_mask_zext(i16 %x_in, i8 %y) {
; CHECK-NEXT: [[X:%.*]] = xor i16 [[X_IN:%.*]], 123
; CHECK-NEXT: [[M_IN:%.*]] = lshr i8 -1, [[Y:%.*]]
; CHECK-NEXT: [[MASK:%.*]] = zext i8 [[M_IN]] to i16
-; CHECK-NEXT: [[AND:%.*]] = and i16 [[X]], [[MASK]]
-; CHECK-NEXT: [[R:%.*]] = icmp eq i16 [[AND]], [[X]]
+; CHECK-NEXT: [[R:%.*]] = icmp ule i16 [[X]], [[MASK]]
; CHECK-NEXT: ret i1 [[R]]
;
%x = xor i16 %x_in, 123
@@ -94,8 +93,7 @@ define i1 @src_is_mask_and(i8 %x_in, i8 %y, i8 %z) {
; CHECK-NEXT: [[MY:%.*]] = lshr i8 7, [[Y:%.*]]
; CHECK-NEXT: [[MZ:%.*]] = lshr i8 -1, [[Z:%.*]]
; CHECK-NEXT: [[MASK:%.*]] = and i8 [[MY]], [[MZ]]
-; CHECK-NEXT: [[AND:%.*]] = and i8 [[X]], [[MASK]]
-; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[X]], [[AND]]
+; CHECK-NEXT: [[R:%.*]] = icmp ule i8 [[X]], [[MASK]]
; CHECK-NEXT: ret i1 [[R]]
;
%x = xor i8 %x_in, 123
@@ -133,8 +131,7 @@ define i1 @src_is_mask_or(i8 %x_in, i8 %y) {
; CHECK-NEXT: [[X:%.*]] = xor i8 [[X_IN:%.*]], 123
; CHECK-NEXT: [[MY:%.*]] = lshr i8 -1, [[Y:%.*]]
; CHECK-NEXT: [[MASK:%.*]] = and i8 [[MY]], 7
-; CHECK-NEXT: [[AND:%.*]] = and i8 [[MASK]], [[X]]
-; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[X]], [[AND]]
+; CHECK-NEXT: [[R:%.*]] = icmp ule i8 [[X]], [[MASK]]
; CHECK-NEXT: ret i1 [[R]]
;
%x = xor i8 %x_in, 123
@@ -151,8 +148,7 @@ define i1 @src_is_mask_xor(i8 %x_in, i8 %y) {
; CHECK-NEXT: [[X:%.*]] = xor i8 [[X_IN:%.*]], 123
; CHECK-NEXT: [[Y_M1:%.*]] = add i8 [[Y:%.*]], -1
; CHECK-NEXT: [[MASK:%.*]] = xor i8 [[Y_M1]], [[Y]]
-; CHECK-NEXT: [[AND:%.*]] = and i8 [[X]], [[MASK]]
-; CHECK-NEXT: [[R:%.*]] = icmp ne i8 [[AND]], [[X]]
+; CHECK-NEXT: [[R:%.*]] = icmp ugt i8 [[X]], [[MASK]]
; CHECK-NEXT: ret i1 [[R]]
;
%x = xor i8 %x_in, 123
@@ -187,8 +183,7 @@ define i1 @src_is_mask_select(i8 %x_in, i8 %y, i1 %cond) {
; CHECK-NEXT: [[Y_M1:%.*]] = add i8 [[Y:%.*]], -1
; CHECK-NEXT: [[YMASK:%.*]] = xor i8 [[Y_M1]], [[Y]]
; CHECK-NEXT: [[MASK:%.*]] = select i1 [[COND:%.*]], i8 [[YMASK]], i8 15
-; CHECK-NEXT: [[AND:%.*]] = and i8 [[MASK]], [[X]]
-; CHECK-NEXT: [[R:%.*]] = icmp ne i8 [[AND]], [[X]]
+; CHECK-NEXT: [[R:%.*]] = icmp ugt i8 [[X]], [[MASK]]
; CHECK-NEXT: ret i1 [[R]]
;
%x = xor i8 %x_in, 123
@@ -267,8 +262,7 @@ define i1 @src_is_mask_lshr(i8 %x_in, i8 %y, i8 %z, i1 %cond) {
; CHECK-NEXT: [[YMASK:%.*]] = xor i8 [[Y_M1]], [[Y]]
; CHECK-NEXT: [[SMASK:%.*]] = select i1 [[COND:%.*]], i8 [[YMASK]], i8 15
; CHECK-NEXT: [[MASK:%.*]] = lshr i8 [[SMASK]], [[Z:%.*]]
-; CHECK-NEXT: [[AND:%.*]] = and i8 [[MASK]], [[X]]
-; CHECK-NEXT: [[R:%.*]] = icmp ne i8 [[X]], [[AND]]
+; CHECK-NEXT: [[R:%.*]] = icmp ugt i8 [[X]], [[MASK]]
; CHECK-NEXT: ret i1 [[R]]
;
%x = xor i8 %x_in, 123
@@ -288,8 +282,7 @@ define i1 @src_is_mask_ashr(i8 %x_in, i8 %y, i8 %z, i1 %cond) {
; CHECK-NEXT: [[YMASK:%.*]] = xor i8 [[Y_M1]], [[Y]]
; CHECK-NEXT: [[SMASK:%.*]] = select i1 [[COND:%.*]], i8 [[YMASK]], i8 15
; CHECK-NEXT: [[MASK:%.*]] = ashr i8 [[SMASK]], [[Z:%.*]]
-; CHECK-NEXT: [[AND:%.*]] = and i8 [[X]], [[MASK]]
-; CHECK-NEXT: [[R:%.*]] = icmp ne i8 [[AND]], [[X]]
+; CHECK-NEXT: [[R:%.*]] = icmp ugt i8 [[X]], [[MASK]]
; CHECK-NEXT: ret i1 [[R]]
;
%x = xor i8 %x_in, 123
@@ -307,8 +300,7 @@ define i1 @src_is_mask_p2_m1(i8 %x_in, i8 %y) {
; CHECK-NEXT: [[X:%.*]] = xor i8 [[X_IN:%.*]], 123
; CHECK-NEXT: [[P2ORZ:%.*]] = shl i8 2, [[Y:%.*]]
; CHECK-NEXT: [[MASK:%.*]] = add i8 [[P2ORZ]], -1
-; CHECK-NEXT: [[AND:%.*]] = and i8 [[MASK]], [[X]]
-; CHECK-NEXT: [[R:%.*]] = icmp ne i8 [[AND]], [[X]]
+; CHECK-NEXT: [[R:%.*]] = icmp ugt i8 [[X]], [[MASK]]
; CHECK-NEXT: ret i1 [[R]]
;
%x = xor i8 %x_in, 123
@@ -325,8 +317,7 @@ define i1 @src_is_mask_umax(i8 %x_in, i8 %y) {
; CHECK-NEXT: [[Y_M1:%.*]] = add i8 [[Y:%.*]], -1
; CHECK-NEXT: [[YMASK:%.*]] = xor i8 [[Y_M1]], [[Y]]
; CHECK-NEXT: [[MASK:%.*]] = call i8 @llvm.umax.i8(i8 [[YMASK]], i8 3)
-; CHECK-NEXT: [[AND:%.*]] = and i8 [[X]], [[MASK]]
-; CHECK-NEXT: [[R:%.*]] = icmp ne i8 [[AND]], [[X]]
+; CHECK-NEXT: [[R:%.*]] = icmp ugt i8 [[X]], [[MASK]]
; CHECK-NEXT: ret i1 [[R]]
;
%x = xor i8 %x_in, 123
@@ -346,8 +337,7 @@ define i1 @src_is_mask_umin(i8 %x_in, i8 %y, i8 %z) {
; CHECK-NEXT: [[YMASK:%.*]] = xor i8 [[Y_M1]], [[Y]]
; CHECK-NEXT: [[ZMASK:%.*]] = lshr i8 15, [[Z:%.*]]
; CHECK-NEXT: [[MASK:%.*]] = call i8 @llvm.umin.i8(i8 [[YMASK]], i8 [[ZMASK]])
-; CHECK-NEXT: [[AND:%.*]] = and i8 [[MASK]], [[X]]
-; CHECK-NEXT: [[R:%.*]] = icmp ne i8 [[AND]], [[X]]
+; CHECK-NEXT: [[R:%.*]] = icmp ugt i8 [[X]], [[MASK]]
; CHECK-NEXT: ret i1 [[R]]
;
%x = xor i8 %x_in, 123
@@ -387,8 +377,7 @@ define i1 @src_is_mask_smax(i8 %x_in, i8 %y) {
; CHECK-NEXT: [[Y_M1:%.*]] = add i8 [[Y:%.*]], -1
; CHECK-NEXT: [[YMASK:%.*]] = xor i8 [[Y_M1]], [[Y]]
; CHECK-NEXT: [[MASK:%.*]] = call i8 @llvm.smax.i8(i8 [[YMASK]], i8 -1)
-; CHECK-NEXT: [[AND:%.*]] = and i8 [[X]], [[MASK]]
-; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[AND]], [[X]]
+; CHECK-NEXT: [[R:%.*]] = icmp ule i8 [[X]], [[MASK]]
; CHECK-NEXT: ret i1 [[R]]
;
%x = xor i8 %x_in, 123
@@ -407,8 +396,7 @@ define i1 @src_is_mask_smin(i8 %x_in, i8 %y) {
; CHECK-NEXT: [[Y_M1:%.*]] = add i8 [[Y:%.*]], -1
; CHECK-NEXT: [[YMASK:%.*]] = xor i8 [[Y_M1]], [[Y]]
; CHECK-NEXT: [[MASK:%.*]] = call i8 @llvm.smin.i8(i8 [[YMASK]], i8 0)
-; CHECK-NEXT: [[AND:%.*]] = and i8 [[MASK]], [[X]]
-; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[AND]], [[X]]
+; CHECK-NEXT: [[R:%.*]] = icmp ule i8 [[X]], [[MASK]]
; CHECK-NEXT: ret i1 [[R]]
;
%x = xor i8 %x_in, 123
@@ -426,8 +414,7 @@ define i1 @src_is_mask_bitreverse_not_mask(i8 %x_in, i8 %y) {
; CHECK-NEXT: [[X:%.*]] = xor i8 [[X_IN:%.*]], 123
; CHECK-NEXT: [[NMASK:%.*]] = shl nsw i8 -1, [[Y:%.*]]
; CHECK-NEXT: [[MASK:%.*]] = call i8 @llvm.bitreverse.i8(i8 [[NMASK]])
-; CHECK-NEXT: [[AND:%.*]] = and i8 [[X]], [[MASK]]
-; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[AND]], [[X]]
+; CHECK-NEXT: [[R:%.*]] = icmp ule i8 [[X]], [[MASK]]
; CHECK-NEXT: ret i1 [[R]]
;
%x = xor i8 %x_in, 123
@@ -445,8 +432,7 @@ define i1 @src_is_notmask_sext(i16 %x_in, i8 %y) {
; CHECK-NEXT: [[M_IN:%.*]] = shl i8 -8, [[Y:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = xor i8 [[M_IN]], -1
; CHECK-NEXT: [[MASK:%.*]] = sext i8 [[TMP1]] to i16
-; CHECK-NEXT: [[AND:%.*]] = and i16 [[X]], [[MASK]]
-; CHECK-NEXT: [[R:%.*]] = icmp eq i16 [[AND]], [[X]]
+; CHECK-NEXT: [[R:%.*]] = icmp ule i16 [[X]], [[MASK]]
; CHECK-NEXT: ret i1 [[R]]
;
%x = xor i16 %x_in, 123
@@ -539,13 +525,11 @@ define i1 @src_is_notmask_lshr_shl_fail_mismatch_shifts(i8 %x_in, i8 %y, i8 %z)
define i1 @src_is_notmask_ashr(i16 %x_in, i8 %y, i16 %z) {
; CHECK-LABEL: @src_is_notmask_ashr(
-; CHECK-NEXT: [[X:%.*]] = xor i16 [[X_IN:%.*]], 123
; CHECK-NEXT: [[M_IN:%.*]] = shl i8 -32, [[Y:%.*]]
; CHECK-NEXT: [[NMASK:%.*]] = sext i8 [[M_IN]] to i16
; CHECK-NEXT: [[NMASK_SHR:%.*]] = ashr i16 [[NMASK]], [[Z:%.*]]
-; CHECK-NEXT: [[MASK:%.*]] = xor i16 [[NMASK_SHR]], -1
-; CHECK-NEXT: [[AND:%.*]] = and i16 [[X]], [[MASK]]
-; CHECK-NEXT: [[R:%.*]] = icmp eq i16 [[X]], [[AND]]
+; CHECK-NEXT: [[TMP1:%.*]] = xor i16 [[X_IN:%.*]], -124
+; CHECK-NEXT: [[R:%.*]] = icmp uge i16 [[TMP1]], [[NMASK_SHR]]
; CHECK-NEXT: ret i1 [[R]]
;
%x = xor i16 %x_in, 123
>From ea9f6e4eed00f6a6b9960d3195c5eb9f111dfa9c Mon Sep 17 00:00:00 2001
From: Noah Goldstein <goldstein.w.n at gmail.com>
Date: Wed, 13 Sep 2023 13:45:55 -0500
Subject: [PATCH 3/3] [InstCombine] Recognize `(icmp eq/ne (and X, ~Mask), 0)`
pattern in `foldICmpWithLowBitMaskedVal`
`(icmp eq/ne (and X, ~Mask), 0)` is equivilent to `(icmp eq/ne (and X,
Mask), X` and we sometimes generate the former pattern intentionally
to reduce number of uses of `X`.
Proof: https://alive2.llvm.org/ce/z/3u-usC
Differential Revision: https://reviews.llvm.org/D159329
---
.../InstCombine/InstCombineCompares.cpp | 11 +++++++++++
.../InstCombine/icmp-and-lowbit-mask.ll | 17 ++++++-----------
.../InstCombine/lshr-and-negC-icmpeq-zero.ll | 9 +++------
.../InstCombine/lshr-and-signbit-icmpeq-zero.ll | 9 +++------
.../InstCombine/shl-and-negC-icmpeq-zero.ll | 9 +++------
.../InstCombine/shl-and-signbit-icmpeq-zero.ll | 9 +++------
6 files changed, 29 insertions(+), 35 deletions(-)
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
index 535a5146fa9415..b33004aefb7405 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
@@ -4176,6 +4176,7 @@ static bool isMaskOrZero(const Value *V, bool Not, const SimplifyQuery &Q,
/// a check for a lossy truncation.
/// Folds:
/// icmp SrcPred (x & Mask), x to icmp DstPred x, Mask
+/// icmp eq/ne (x & ~Mask), 0 to icmp DstPred x, Mask
/// Where Mask is some pattern that produces all-ones in low bits:
/// (-1 >> y)
/// ((-1 << y) >> y) <- non-canonical, has extra uses
@@ -4208,6 +4209,16 @@ static Value *foldICmpWithLowBitMaskedVal(ICmpInst &I, const SimplifyQuery &Q,
SrcPred = ICmpInst::getSwappedPredicate(Pred);
return CheckMask(M, /*Not*/ false);
}
+ if (OpNo == 1 && match(I.getOperand(1), m_Zero()) &&
+ ICmpInst::isEquality(Pred) &&
+ match(I.getOperand(0), m_OneUse(m_And(m_Value(X), m_Value(M))))) {
+ NeedsNot = true;
+ if (IC.isFreeToInvert(X, X->hasOneUse()) && CheckMask(X, /*Not*/ true)) {
+ std::swap(X, M);
+ return true;
+ }
+ return IC.isFreeToInvert(M, M->hasOneUse()) && CheckMask(M, /*Not*/ true);
+ }
return false;
};
diff --git a/llvm/test/Transforms/InstCombine/icmp-and-lowbit-mask.ll b/llvm/test/Transforms/InstCombine/icmp-and-lowbit-mask.ll
index ca378ec8b681f0..b06efaac25d169 100644
--- a/llvm/test/Transforms/InstCombine/icmp-and-lowbit-mask.ll
+++ b/llvm/test/Transforms/InstCombine/icmp-and-lowbit-mask.ll
@@ -50,9 +50,7 @@ define i1 @src_is_mask_sext(i16 %x_in, i8 %y) {
; CHECK-NEXT: [[X:%.*]] = xor i16 [[X_IN:%.*]], 123
; CHECK-NEXT: [[M_IN:%.*]] = lshr i8 31, [[Y:%.*]]
; CHECK-NEXT: [[MASK:%.*]] = zext nneg i8 [[M_IN]] to i16
-; CHECK-NEXT: [[NOTMASK:%.*]] = xor i16 [[MASK]], -1
-; CHECK-NEXT: [[AND:%.*]] = and i16 [[X]], [[NOTMASK]]
-; CHECK-NEXT: [[R:%.*]] = icmp eq i16 [[AND]], 0
+; CHECK-NEXT: [[R:%.*]] = icmp ule i16 [[X]], [[MASK]]
; CHECK-NEXT: ret i1 [[R]]
;
%x = xor i16 %x_in, 123
@@ -220,9 +218,7 @@ define i1 @src_is_mask_shl_lshr(i8 %x_in, i8 %y, i1 %cond) {
; CHECK-LABEL: @src_is_mask_shl_lshr(
; CHECK-NEXT: [[X:%.*]] = xor i8 [[X_IN:%.*]], 122
; CHECK-NEXT: [[TMP1:%.*]] = lshr i8 -1, [[Y:%.*]]
-; CHECK-NEXT: [[NOTMASK:%.*]] = xor i8 [[TMP1]], -1
-; CHECK-NEXT: [[AND:%.*]] = and i8 [[X]], [[NOTMASK]]
-; CHECK-NEXT: [[R:%.*]] = icmp ne i8 [[AND]], 0
+; CHECK-NEXT: [[R:%.*]] = icmp ugt i8 [[X]], [[TMP1]]
; CHECK-NEXT: ret i1 [[R]]
;
%x = xor i8 %x_in, 123
@@ -567,11 +563,10 @@ define i1 @src_is_notmask_neg_p2(i8 %x_in, i8 %y) {
define i1 @src_is_notmask_neg_p2_fail_not_invertable(i8 %x_in, i8 %y) {
; CHECK-LABEL: @src_is_notmask_neg_p2_fail_not_invertable(
; CHECK-NEXT: [[X:%.*]] = xor i8 [[X_IN:%.*]], 123
-; CHECK-NEXT: [[NY:%.*]] = sub i8 0, [[Y:%.*]]
-; CHECK-NEXT: [[P2:%.*]] = and i8 [[NY]], [[Y]]
-; CHECK-NEXT: [[NOTMASK:%.*]] = sub i8 0, [[P2]]
-; CHECK-NEXT: [[AND:%.*]] = and i8 [[X]], [[NOTMASK]]
-; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[AND]], 0
+; CHECK-NEXT: [[TMP1:%.*]] = add i8 [[Y:%.*]], -1
+; CHECK-NEXT: [[TMP2:%.*]] = xor i8 [[Y]], -1
+; CHECK-NEXT: [[TMP3:%.*]] = and i8 [[TMP1]], [[TMP2]]
+; CHECK-NEXT: [[R:%.*]] = icmp ule i8 [[X]], [[TMP3]]
; CHECK-NEXT: ret i1 [[R]]
;
%x = xor i8 %x_in, 123
diff --git a/llvm/test/Transforms/InstCombine/lshr-and-negC-icmpeq-zero.ll b/llvm/test/Transforms/InstCombine/lshr-and-negC-icmpeq-zero.ll
index 79aef3a5406cfb..847a7940bad8c7 100644
--- a/llvm/test/Transforms/InstCombine/lshr-and-negC-icmpeq-zero.ll
+++ b/llvm/test/Transforms/InstCombine/lshr-and-negC-icmpeq-zero.ll
@@ -84,8 +84,7 @@ define <4 x i1> @vec_4xi32_lshr_and_negC_eq(<4 x i32> %x, <4 x i32> %y) {
define <4 x i1> @vec_lshr_and_negC_eq_undef1(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: @vec_lshr_and_negC_eq_undef1(
; CHECK-NEXT: [[LSHR:%.*]] = lshr <4 x i32> [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[AND:%.*]] = and <4 x i32> [[LSHR]], <i32 -8, i32 undef, i32 -8, i32 -8>
-; CHECK-NEXT: [[R:%.*]] = icmp eq <4 x i32> [[AND]], zeroinitializer
+; CHECK-NEXT: [[R:%.*]] = icmp ult <4 x i32> [[LSHR]], <i32 8, i32 8, i32 8, i32 8>
; CHECK-NEXT: ret <4 x i1> [[R]]
;
%lshr = lshr <4 x i32> %x, %y
@@ -97,8 +96,7 @@ define <4 x i1> @vec_lshr_and_negC_eq_undef1(<4 x i32> %x, <4 x i32> %y) {
define <4 x i1> @vec_lshr_and_negC_eq_undef2(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: @vec_lshr_and_negC_eq_undef2(
; CHECK-NEXT: [[LSHR:%.*]] = lshr <4 x i32> [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[AND:%.*]] = and <4 x i32> [[LSHR]], <i32 -8, i32 -8, i32 -8, i32 -8>
-; CHECK-NEXT: [[R:%.*]] = icmp eq <4 x i32> [[AND]], <i32 0, i32 0, i32 0, i32 undef>
+; CHECK-NEXT: [[R:%.*]] = icmp ult <4 x i32> [[LSHR]], <i32 8, i32 8, i32 8, i32 8>
; CHECK-NEXT: ret <4 x i1> [[R]]
;
%lshr = lshr <4 x i32> %x, %y
@@ -110,8 +108,7 @@ define <4 x i1> @vec_lshr_and_negC_eq_undef2(<4 x i32> %x, <4 x i32> %y) {
define <4 x i1> @vec_lshr_and_negC_eq_undef3(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: @vec_lshr_and_negC_eq_undef3(
; CHECK-NEXT: [[LSHR:%.*]] = lshr <4 x i32> [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[AND:%.*]] = and <4 x i32> [[LSHR]], <i32 -8, i32 -8, i32 undef, i32 -8>
-; CHECK-NEXT: [[R:%.*]] = icmp eq <4 x i32> [[AND]], <i32 0, i32 0, i32 0, i32 undef>
+; CHECK-NEXT: [[R:%.*]] = icmp ult <4 x i32> [[LSHR]], <i32 8, i32 8, i32 8, i32 8>
; CHECK-NEXT: ret <4 x i1> [[R]]
;
%lshr = lshr <4 x i32> %x, %y
diff --git a/llvm/test/Transforms/InstCombine/lshr-and-signbit-icmpeq-zero.ll b/llvm/test/Transforms/InstCombine/lshr-and-signbit-icmpeq-zero.ll
index 5335a4736896d7..39f4e58b25dc84 100644
--- a/llvm/test/Transforms/InstCombine/lshr-and-signbit-icmpeq-zero.ll
+++ b/llvm/test/Transforms/InstCombine/lshr-and-signbit-icmpeq-zero.ll
@@ -84,8 +84,7 @@ define <4 x i1> @vec_4xi32_lshr_and_signbit_eq(<4 x i32> %x, <4 x i32> %y) {
define <4 x i1> @vec_4xi32_lshr_and_signbit_eq_undef1(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: @vec_4xi32_lshr_and_signbit_eq_undef1(
; CHECK-NEXT: [[LSHR:%.*]] = lshr <4 x i32> [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[AND:%.*]] = and <4 x i32> [[LSHR]], <i32 -2147483648, i32 undef, i32 -2147483648, i32 -2147483648>
-; CHECK-NEXT: [[R:%.*]] = icmp eq <4 x i32> [[AND]], zeroinitializer
+; CHECK-NEXT: [[R:%.*]] = icmp sgt <4 x i32> [[LSHR]], <i32 -1, i32 -1, i32 -1, i32 -1>
; CHECK-NEXT: ret <4 x i1> [[R]]
;
%lshr = lshr <4 x i32> %x, %y
@@ -97,8 +96,7 @@ define <4 x i1> @vec_4xi32_lshr_and_signbit_eq_undef1(<4 x i32> %x, <4 x i32> %y
define <4 x i1> @vec_4xi32_lshr_and_signbit_eq_undef2(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: @vec_4xi32_lshr_and_signbit_eq_undef2(
; CHECK-NEXT: [[LSHR:%.*]] = lshr <4 x i32> [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[AND:%.*]] = and <4 x i32> [[LSHR]], <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
-; CHECK-NEXT: [[R:%.*]] = icmp eq <4 x i32> [[AND]], <i32 undef, i32 0, i32 0, i32 0>
+; CHECK-NEXT: [[R:%.*]] = icmp sgt <4 x i32> [[LSHR]], <i32 -1, i32 -1, i32 -1, i32 -1>
; CHECK-NEXT: ret <4 x i1> [[R]]
;
%lshr = lshr <4 x i32> %x, %y
@@ -110,8 +108,7 @@ define <4 x i1> @vec_4xi32_lshr_and_signbit_eq_undef2(<4 x i32> %x, <4 x i32> %y
define <4 x i1> @vec_4xi32_lshr_and_signbit_eq_undef3(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: @vec_4xi32_lshr_and_signbit_eq_undef3(
; CHECK-NEXT: [[LSHR:%.*]] = lshr <4 x i32> [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[AND:%.*]] = and <4 x i32> [[LSHR]], <i32 -2147483648, i32 undef, i32 -2147483648, i32 -2147483648>
-; CHECK-NEXT: [[R:%.*]] = icmp eq <4 x i32> [[AND]], <i32 0, i32 0, i32 0, i32 undef>
+; CHECK-NEXT: [[R:%.*]] = icmp sgt <4 x i32> [[LSHR]], <i32 -1, i32 -1, i32 -1, i32 -1>
; CHECK-NEXT: ret <4 x i1> [[R]]
;
%lshr = lshr <4 x i32> %x, %y
diff --git a/llvm/test/Transforms/InstCombine/shl-and-negC-icmpeq-zero.ll b/llvm/test/Transforms/InstCombine/shl-and-negC-icmpeq-zero.ll
index d8e7fe2e2a2c16..406dc72f2646e5 100644
--- a/llvm/test/Transforms/InstCombine/shl-and-negC-icmpeq-zero.ll
+++ b/llvm/test/Transforms/InstCombine/shl-and-negC-icmpeq-zero.ll
@@ -84,8 +84,7 @@ define <4 x i1> @vec_4xi32_shl_and_negC_eq(<4 x i32> %x, <4 x i32> %y) {
define <4 x i1> @vec_shl_and_negC_eq_undef1(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: @vec_shl_and_negC_eq_undef1(
; CHECK-NEXT: [[SHL:%.*]] = shl <4 x i32> [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[AND:%.*]] = and <4 x i32> [[SHL]], <i32 -8, i32 undef, i32 -8, i32 -8>
-; CHECK-NEXT: [[R:%.*]] = icmp eq <4 x i32> [[AND]], zeroinitializer
+; CHECK-NEXT: [[R:%.*]] = icmp ult <4 x i32> [[SHL]], <i32 8, i32 8, i32 8, i32 8>
; CHECK-NEXT: ret <4 x i1> [[R]]
;
%shl = shl <4 x i32> %x, %y
@@ -97,8 +96,7 @@ define <4 x i1> @vec_shl_and_negC_eq_undef1(<4 x i32> %x, <4 x i32> %y) {
define <4 x i1> @vec_shl_and_negC_eq_undef2(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: @vec_shl_and_negC_eq_undef2(
; CHECK-NEXT: [[SHL:%.*]] = shl <4 x i32> [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[AND:%.*]] = and <4 x i32> [[SHL]], <i32 -8, i32 -8, i32 -8, i32 -8>
-; CHECK-NEXT: [[R:%.*]] = icmp eq <4 x i32> [[AND]], <i32 0, i32 0, i32 0, i32 undef>
+; CHECK-NEXT: [[R:%.*]] = icmp ult <4 x i32> [[SHL]], <i32 8, i32 8, i32 8, i32 8>
; CHECK-NEXT: ret <4 x i1> [[R]]
;
%shl = shl <4 x i32> %x, %y
@@ -110,8 +108,7 @@ define <4 x i1> @vec_shl_and_negC_eq_undef2(<4 x i32> %x, <4 x i32> %y) {
define <4 x i1> @vec_shl_and_negC_eq_undef3(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: @vec_shl_and_negC_eq_undef3(
; CHECK-NEXT: [[SHL:%.*]] = shl <4 x i32> [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[AND:%.*]] = and <4 x i32> [[SHL]], <i32 -8, i32 -8, i32 undef, i32 -8>
-; CHECK-NEXT: [[R:%.*]] = icmp eq <4 x i32> [[AND]], <i32 0, i32 0, i32 0, i32 undef>
+; CHECK-NEXT: [[R:%.*]] = icmp ult <4 x i32> [[SHL]], <i32 8, i32 8, i32 8, i32 8>
; CHECK-NEXT: ret <4 x i1> [[R]]
;
%shl = shl <4 x i32> %x, %y
diff --git a/llvm/test/Transforms/InstCombine/shl-and-signbit-icmpeq-zero.ll b/llvm/test/Transforms/InstCombine/shl-and-signbit-icmpeq-zero.ll
index 42b755f51a9713..4c2c876e3925bf 100644
--- a/llvm/test/Transforms/InstCombine/shl-and-signbit-icmpeq-zero.ll
+++ b/llvm/test/Transforms/InstCombine/shl-and-signbit-icmpeq-zero.ll
@@ -84,8 +84,7 @@ define <4 x i1> @vec_4xi32_shl_and_signbit_eq(<4 x i32> %x, <4 x i32> %y) {
define <4 x i1> @vec_4xi32_shl_and_signbit_eq_undef1(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: @vec_4xi32_shl_and_signbit_eq_undef1(
; CHECK-NEXT: [[SHL:%.*]] = shl <4 x i32> [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[AND:%.*]] = and <4 x i32> [[SHL]], <i32 -2147483648, i32 undef, i32 -2147483648, i32 -2147483648>
-; CHECK-NEXT: [[R:%.*]] = icmp eq <4 x i32> [[AND]], zeroinitializer
+; CHECK-NEXT: [[R:%.*]] = icmp sgt <4 x i32> [[SHL]], <i32 -1, i32 -1, i32 -1, i32 -1>
; CHECK-NEXT: ret <4 x i1> [[R]]
;
%shl = shl <4 x i32> %x, %y
@@ -97,8 +96,7 @@ define <4 x i1> @vec_4xi32_shl_and_signbit_eq_undef1(<4 x i32> %x, <4 x i32> %y)
define <4 x i1> @vec_4xi32_shl_and_signbit_eq_undef2(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: @vec_4xi32_shl_and_signbit_eq_undef2(
; CHECK-NEXT: [[SHL:%.*]] = shl <4 x i32> [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[AND:%.*]] = and <4 x i32> [[SHL]], <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
-; CHECK-NEXT: [[R:%.*]] = icmp eq <4 x i32> [[AND]], <i32 undef, i32 0, i32 0, i32 0>
+; CHECK-NEXT: [[R:%.*]] = icmp sgt <4 x i32> [[SHL]], <i32 -1, i32 -1, i32 -1, i32 -1>
; CHECK-NEXT: ret <4 x i1> [[R]]
;
%shl = shl <4 x i32> %x, %y
@@ -110,8 +108,7 @@ define <4 x i1> @vec_4xi32_shl_and_signbit_eq_undef2(<4 x i32> %x, <4 x i32> %y)
define <4 x i1> @vec_4xi32_shl_and_signbit_eq_undef3(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: @vec_4xi32_shl_and_signbit_eq_undef3(
; CHECK-NEXT: [[SHL:%.*]] = shl <4 x i32> [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[AND:%.*]] = and <4 x i32> [[SHL]], <i32 -2147483648, i32 undef, i32 -2147483648, i32 -2147483648>
-; CHECK-NEXT: [[R:%.*]] = icmp eq <4 x i32> [[AND]], <i32 0, i32 0, i32 0, i32 undef>
+; CHECK-NEXT: [[R:%.*]] = icmp sgt <4 x i32> [[SHL]], <i32 -1, i32 -1, i32 -1, i32 -1>
; CHECK-NEXT: ret <4 x i1> [[R]]
;
%shl = shl <4 x i32> %x, %y
More information about the llvm-commits
mailing list