[llvm] [GlobalISel][TableGen] Take first result for multi-output instructions (PR #81130)

[Björn Pettersson via llvm-commits]

bjope wrote:

@s-barannikov : First of all this patch is about handling one explicit def plus extra implicit defs.
Typical example is the test case I added looking like this:
```
let Defs = [R0] in
def ImplicitDefInstr : I<(outs GPR32:$dst), (ins GPR32:$src), []>;
def OtherInstr : I<(outs GPR32:$dst), (ins GPR32:$src), []>;

def : Pat<(i32 (add i32:$src, i32:$src)),
  (OtherInstr (ImplicitDefInstr GPR32:$src))>;
```

Your example involves multiple explicit outs. The ADDrf instruction is only having one explicit def, but nm_add is having two outs. So I don't really know how that would work either with SDagISel. Afaik you can't have patterns that produce more than one outs and match that in the selection DAG.

Are you sure that the

> def : Pat<(nm_add i32:$lhs, i32:$rhs), (ADDrf i32:$lhs, i32:$rhs)>;

pattern really works as intended with SDagISel?
(Apparently tablegen has accepted the pattern, but I wonder if it ever is matched and if you really get the MIR that you expect in such cases.)



https://github.com/llvm/llvm-project/pull/81130