[llvm] [GlobalISel][Mips] Global ISel for `brcond` (PR #81306)
via llvm-commits
llvm-commits at lists.llvm.org
Sat Feb 10 10:55:48 PST 2024
https://github.com/darkbuck updated https://github.com/llvm/llvm-project/pull/81306
>From 5f00686369fdeb6f00fa949a8f9a6baf47eed9f5 Mon Sep 17 00:00:00 2001
From: Michael Liao <michael.hliao at gmail.com>
Date: Fri, 9 Feb 2024 14:41:28 -0500
Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=?UTF-8?q?itial=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
---
llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td | 1 +
1 file changed, 1 insertion(+)
diff --git a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
index f792237203b431..6bc19421fb0169 100644
--- a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
+++ b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
@@ -130,6 +130,7 @@ let IfConvergent = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS in {
}
def : GINodeEquiv<G_BR, br>;
+def : GINodeEquiv<G_BRCOND, brcond>;
def : GINodeEquiv<G_BSWAP, bswap>;
def : GINodeEquiv<G_BITREVERSE, bitreverse>;
def : GINodeEquiv<G_FSHL, fshl>;
>From 8f736a3139d92b99619c66275c9239ff88921748 Mon Sep 17 00:00:00 2001
From: Michael Liao <michael.hliao at gmail.com>
Date: Fri, 9 Feb 2024 16:28:05 -0500
Subject: [PATCH 2/2] Fix the failure from Mips GISel
Created using spr 1.3.4
---
.../Target/Mips/MipsInstructionSelector.cpp | 7 -
.../GlobalISel/instruction-select/branch.mir | 2 +-
.../jump_table_and_brjt.mir | 297 ++++++++++--------
.../GlobalISel/instruction-select/phi.mir | 16 +-
4 files changed, 175 insertions(+), 147 deletions(-)
diff --git a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
index 4478a574a24088..654f29d08af0b5 100644
--- a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
+++ b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
@@ -357,13 +357,6 @@ bool MipsInstructionSelector::select(MachineInstr &I) {
.addImm(0);
break;
}
- case G_BRCOND: {
- MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::BNE))
- .add(I.getOperand(0))
- .addUse(Mips::ZERO)
- .add(I.getOperand(1));
- break;
- }
case G_BRJT: {
unsigned EntrySize =
MF.getJumpTableInfo()->getEntrySize(MF.getDataLayout());
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/branch.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/branch.mir
index 2de4096764e785..13116329fe1aa3 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/branch.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/branch.mir
@@ -77,7 +77,7 @@ body: |
; MIPS32-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
; MIPS32-NEXT: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
- ; MIPS32-NEXT: BNE [[ANDi]], $zero, %bb.1, implicit-def $at
+ ; MIPS32-NEXT: BNE [[ANDi]], $zero, %bb.1, implicit-def dead $at
; MIPS32-NEXT: J %bb.2, implicit-def dead $at
; MIPS32-NEXT: {{ $}}
; MIPS32-NEXT: bb.1.if.then:
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/jump_table_and_brjt.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/jump_table_and_brjt.mir
index b8450fffdb98df..6022e7ac4828f1 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/jump_table_and_brjt.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/jump_table_and_brjt.mir
@@ -73,139 +73,174 @@ jumpTable:
body: |
; MIPS32-LABEL: name: mod4_0_to_11
; MIPS32: bb.0.entry:
- ; MIPS32: successors: %bb.6(0x40000000), %bb.1(0x40000000)
- ; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 7
- ; MIPS32: [[ORi1:%[0-9]+]]:gpr32 = ORi $zero, 3
- ; MIPS32: [[ORi2:%[0-9]+]]:gpr32 = ORi $zero, 2
- ; MIPS32: [[ORi3:%[0-9]+]]:gpr32 = ORi $zero, 1
- ; MIPS32: [[ORi4:%[0-9]+]]:gpr32 = ORi $zero, 0
- ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
- ; MIPS32: [[ORi5:%[0-9]+]]:gpr32 = ORi $zero, 0
- ; MIPS32: [[SUBu:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[ORi5]]
- ; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[ORi]], [[SUBu]]
- ; MIPS32: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[SLTu]], 1
- ; MIPS32: BNE [[ANDi]], $zero, %bb.6, implicit-def $at
- ; MIPS32: bb.1.entry:
- ; MIPS32: successors: %bb.2(0x20000000), %bb.3(0x20000000), %bb.4(0x20000000), %bb.5(0x20000000)
- ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) %jump-table.0
- ; MIPS32: [[SLL:%[0-9]+]]:gpr32 = SLL [[SUBu]], 2
- ; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu [[LUi]], [[SLL]]
- ; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[ADDu]], target-flags(mips-abs-lo) %jump-table.0 :: (load (s32))
- ; MIPS32: PseudoIndirectBranch [[LW]]
- ; MIPS32: bb.2.sw.bb:
- ; MIPS32: $v0 = COPY [[ORi4]]
- ; MIPS32: RetRA implicit $v0
- ; MIPS32: bb.3.sw.bb1:
- ; MIPS32: $v0 = COPY [[ORi3]]
- ; MIPS32: RetRA implicit $v0
- ; MIPS32: bb.4.sw.bb2:
- ; MIPS32: $v0 = COPY [[ORi2]]
- ; MIPS32: RetRA implicit $v0
- ; MIPS32: bb.5.sw.bb3:
- ; MIPS32: $v0 = COPY [[ORi1]]
- ; MIPS32: RetRA implicit $v0
- ; MIPS32: bb.6.sw.default:
- ; MIPS32: successors: %bb.7(0x80000000)
- ; MIPS32: bb.7.sw.epilog:
- ; MIPS32: successors: %bb.13(0x40000000), %bb.8(0x40000000)
- ; MIPS32: [[ORi6:%[0-9]+]]:gpr32 = ORi $zero, 8
- ; MIPS32: [[SUBu1:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[ORi6]]
- ; MIPS32: [[SLTu1:%[0-9]+]]:gpr32 = SLTu [[ORi1]], [[SUBu1]]
- ; MIPS32: [[ANDi1:%[0-9]+]]:gpr32 = ANDi [[SLTu1]], 1
- ; MIPS32: BNE [[ANDi1]], $zero, %bb.13, implicit-def $at
- ; MIPS32: bb.8.sw.epilog:
- ; MIPS32: successors: %bb.9(0x20000000), %bb.10(0x20000000), %bb.11(0x20000000), %bb.12(0x20000000)
- ; MIPS32: [[LUi1:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) %jump-table.1
- ; MIPS32: [[SLL1:%[0-9]+]]:gpr32 = SLL [[SUBu1]], 2
- ; MIPS32: [[ADDu1:%[0-9]+]]:gpr32 = ADDu [[LUi1]], [[SLL1]]
- ; MIPS32: [[LW1:%[0-9]+]]:gpr32 = LW [[ADDu1]], target-flags(mips-abs-lo) %jump-table.1 :: (load (s32))
- ; MIPS32: PseudoIndirectBranch [[LW1]]
- ; MIPS32: bb.9.sw.bb4:
- ; MIPS32: $v0 = COPY [[ORi4]]
- ; MIPS32: RetRA implicit $v0
- ; MIPS32: bb.10.sw.bb5:
- ; MIPS32: $v0 = COPY [[ORi3]]
- ; MIPS32: RetRA implicit $v0
- ; MIPS32: bb.11.sw.bb6:
- ; MIPS32: $v0 = COPY [[ORi2]]
- ; MIPS32: RetRA implicit $v0
- ; MIPS32: bb.12.sw.bb7:
- ; MIPS32: $v0 = COPY [[ORi1]]
- ; MIPS32: RetRA implicit $v0
- ; MIPS32: bb.13.sw.default8:
- ; MIPS32: $v0 = COPY [[ADDiu]]
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32-NEXT: successors: %bb.6(0x40000000), %bb.1(0x40000000)
+ ; MIPS32-NEXT: liveins: $a0
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; MIPS32-NEXT: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 7
+ ; MIPS32-NEXT: [[ORi1:%[0-9]+]]:gpr32 = ORi $zero, 3
+ ; MIPS32-NEXT: [[ORi2:%[0-9]+]]:gpr32 = ORi $zero, 2
+ ; MIPS32-NEXT: [[ORi3:%[0-9]+]]:gpr32 = ORi $zero, 1
+ ; MIPS32-NEXT: [[ORi4:%[0-9]+]]:gpr32 = ORi $zero, 0
+ ; MIPS32-NEXT: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
+ ; MIPS32-NEXT: [[ORi5:%[0-9]+]]:gpr32 = ORi $zero, 0
+ ; MIPS32-NEXT: [[SUBu:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[ORi5]]
+ ; MIPS32-NEXT: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[ORi]], [[SUBu]]
+ ; MIPS32-NEXT: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[SLTu]], 1
+ ; MIPS32-NEXT: BNE [[ANDi]], $zero, %bb.6, implicit-def dead $at
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: bb.1.entry:
+ ; MIPS32-NEXT: successors: %bb.2(0x20000000), %bb.3(0x20000000), %bb.4(0x20000000), %bb.5(0x20000000)
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) %jump-table.0
+ ; MIPS32-NEXT: [[SLL:%[0-9]+]]:gpr32 = SLL [[SUBu]], 2
+ ; MIPS32-NEXT: [[ADDu:%[0-9]+]]:gpr32 = ADDu [[LUi]], [[SLL]]
+ ; MIPS32-NEXT: [[LW:%[0-9]+]]:gpr32 = LW [[ADDu]], target-flags(mips-abs-lo) %jump-table.0 :: (load (s32))
+ ; MIPS32-NEXT: PseudoIndirectBranch [[LW]]
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: bb.2.sw.bb:
+ ; MIPS32-NEXT: $v0 = COPY [[ORi4]]
+ ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: bb.3.sw.bb1:
+ ; MIPS32-NEXT: $v0 = COPY [[ORi3]]
+ ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: bb.4.sw.bb2:
+ ; MIPS32-NEXT: $v0 = COPY [[ORi2]]
+ ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: bb.5.sw.bb3:
+ ; MIPS32-NEXT: $v0 = COPY [[ORi1]]
+ ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: bb.6.sw.default:
+ ; MIPS32-NEXT: successors: %bb.7(0x80000000)
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: bb.7.sw.epilog:
+ ; MIPS32-NEXT: successors: %bb.13(0x40000000), %bb.8(0x40000000)
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: [[ORi6:%[0-9]+]]:gpr32 = ORi $zero, 8
+ ; MIPS32-NEXT: [[SUBu1:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[ORi6]]
+ ; MIPS32-NEXT: [[SLTu1:%[0-9]+]]:gpr32 = SLTu [[ORi1]], [[SUBu1]]
+ ; MIPS32-NEXT: [[ANDi1:%[0-9]+]]:gpr32 = ANDi [[SLTu1]], 1
+ ; MIPS32-NEXT: BNE [[ANDi1]], $zero, %bb.13, implicit-def dead $at
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: bb.8.sw.epilog:
+ ; MIPS32-NEXT: successors: %bb.9(0x20000000), %bb.10(0x20000000), %bb.11(0x20000000), %bb.12(0x20000000)
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: [[LUi1:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) %jump-table.1
+ ; MIPS32-NEXT: [[SLL1:%[0-9]+]]:gpr32 = SLL [[SUBu1]], 2
+ ; MIPS32-NEXT: [[ADDu1:%[0-9]+]]:gpr32 = ADDu [[LUi1]], [[SLL1]]
+ ; MIPS32-NEXT: [[LW1:%[0-9]+]]:gpr32 = LW [[ADDu1]], target-flags(mips-abs-lo) %jump-table.1 :: (load (s32))
+ ; MIPS32-NEXT: PseudoIndirectBranch [[LW1]]
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: bb.9.sw.bb4:
+ ; MIPS32-NEXT: $v0 = COPY [[ORi4]]
+ ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: bb.10.sw.bb5:
+ ; MIPS32-NEXT: $v0 = COPY [[ORi3]]
+ ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: bb.11.sw.bb6:
+ ; MIPS32-NEXT: $v0 = COPY [[ORi2]]
+ ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: bb.12.sw.bb7:
+ ; MIPS32-NEXT: $v0 = COPY [[ORi1]]
+ ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: bb.13.sw.default8:
+ ; MIPS32-NEXT: $v0 = COPY [[ADDiu]]
+ ; MIPS32-NEXT: RetRA implicit $v0
+ ;
; MIPS32_PIC-LABEL: name: mod4_0_to_11
; MIPS32_PIC: bb.0.entry:
- ; MIPS32_PIC: successors: %bb.6(0x40000000), %bb.1(0x40000000)
- ; MIPS32_PIC: liveins: $a0, $t9, $v0
- ; MIPS32_PIC: [[ADDu:%[0-9]+]]:gpr32 = ADDu $v0, $t9
- ; MIPS32_PIC: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
- ; MIPS32_PIC: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 7
- ; MIPS32_PIC: [[ORi1:%[0-9]+]]:gpr32 = ORi $zero, 3
- ; MIPS32_PIC: [[ORi2:%[0-9]+]]:gpr32 = ORi $zero, 2
- ; MIPS32_PIC: [[ORi3:%[0-9]+]]:gpr32 = ORi $zero, 1
- ; MIPS32_PIC: [[ORi4:%[0-9]+]]:gpr32 = ORi $zero, 0
- ; MIPS32_PIC: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
- ; MIPS32_PIC: [[ORi5:%[0-9]+]]:gpr32 = ORi $zero, 0
- ; MIPS32_PIC: [[SUBu:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[ORi5]]
- ; MIPS32_PIC: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[ORi]], [[SUBu]]
- ; MIPS32_PIC: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[SLTu]], 1
- ; MIPS32_PIC: BNE [[ANDi]], $zero, %bb.6, implicit-def $at
- ; MIPS32_PIC: bb.1.entry:
- ; MIPS32_PIC: successors: %bb.2(0x20000000), %bb.3(0x20000000), %bb.4(0x20000000), %bb.5(0x20000000)
- ; MIPS32_PIC: [[LW:%[0-9]+]]:gpr32 = LW [[ADDu]], target-flags(mips-got) %jump-table.0 :: (load (s32) from got)
- ; MIPS32_PIC: [[SLL:%[0-9]+]]:gpr32 = SLL [[SUBu]], 2
- ; MIPS32_PIC: [[ADDu1:%[0-9]+]]:gpr32 = ADDu [[LW]], [[SLL]]
- ; MIPS32_PIC: [[LW1:%[0-9]+]]:gpr32 = LW [[ADDu1]], target-flags(mips-abs-lo) %jump-table.0 :: (load (s32))
- ; MIPS32_PIC: [[ADDu2:%[0-9]+]]:gpr32 = ADDu [[LW1]], [[ADDu]]
- ; MIPS32_PIC: PseudoIndirectBranch [[ADDu2]]
- ; MIPS32_PIC: bb.2.sw.bb:
- ; MIPS32_PIC: $v0 = COPY [[ORi4]]
- ; MIPS32_PIC: RetRA implicit $v0
- ; MIPS32_PIC: bb.3.sw.bb1:
- ; MIPS32_PIC: $v0 = COPY [[ORi3]]
- ; MIPS32_PIC: RetRA implicit $v0
- ; MIPS32_PIC: bb.4.sw.bb2:
- ; MIPS32_PIC: $v0 = COPY [[ORi2]]
- ; MIPS32_PIC: RetRA implicit $v0
- ; MIPS32_PIC: bb.5.sw.bb3:
- ; MIPS32_PIC: $v0 = COPY [[ORi1]]
- ; MIPS32_PIC: RetRA implicit $v0
- ; MIPS32_PIC: bb.6.sw.default:
- ; MIPS32_PIC: successors: %bb.7(0x80000000)
- ; MIPS32_PIC: bb.7.sw.epilog:
- ; MIPS32_PIC: successors: %bb.13(0x40000000), %bb.8(0x40000000)
- ; MIPS32_PIC: [[ORi6:%[0-9]+]]:gpr32 = ORi $zero, 8
- ; MIPS32_PIC: [[SUBu1:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[ORi6]]
- ; MIPS32_PIC: [[SLTu1:%[0-9]+]]:gpr32 = SLTu [[ORi1]], [[SUBu1]]
- ; MIPS32_PIC: [[ANDi1:%[0-9]+]]:gpr32 = ANDi [[SLTu1]], 1
- ; MIPS32_PIC: BNE [[ANDi1]], $zero, %bb.13, implicit-def $at
- ; MIPS32_PIC: bb.8.sw.epilog:
- ; MIPS32_PIC: successors: %bb.9(0x20000000), %bb.10(0x20000000), %bb.11(0x20000000), %bb.12(0x20000000)
- ; MIPS32_PIC: [[LW2:%[0-9]+]]:gpr32 = LW [[ADDu]], target-flags(mips-got) %jump-table.1 :: (load (s32) from got)
- ; MIPS32_PIC: [[SLL1:%[0-9]+]]:gpr32 = SLL [[SUBu1]], 2
- ; MIPS32_PIC: [[ADDu3:%[0-9]+]]:gpr32 = ADDu [[LW2]], [[SLL1]]
- ; MIPS32_PIC: [[LW3:%[0-9]+]]:gpr32 = LW [[ADDu3]], target-flags(mips-abs-lo) %jump-table.1 :: (load (s32))
- ; MIPS32_PIC: [[ADDu4:%[0-9]+]]:gpr32 = ADDu [[LW3]], [[ADDu]]
- ; MIPS32_PIC: PseudoIndirectBranch [[ADDu4]]
- ; MIPS32_PIC: bb.9.sw.bb4:
- ; MIPS32_PIC: $v0 = COPY [[ORi4]]
- ; MIPS32_PIC: RetRA implicit $v0
- ; MIPS32_PIC: bb.10.sw.bb5:
- ; MIPS32_PIC: $v0 = COPY [[ORi3]]
- ; MIPS32_PIC: RetRA implicit $v0
- ; MIPS32_PIC: bb.11.sw.bb6:
- ; MIPS32_PIC: $v0 = COPY [[ORi2]]
- ; MIPS32_PIC: RetRA implicit $v0
- ; MIPS32_PIC: bb.12.sw.bb7:
- ; MIPS32_PIC: $v0 = COPY [[ORi1]]
- ; MIPS32_PIC: RetRA implicit $v0
- ; MIPS32_PIC: bb.13.sw.default8:
- ; MIPS32_PIC: $v0 = COPY [[ADDiu]]
- ; MIPS32_PIC: RetRA implicit $v0
+ ; MIPS32_PIC-NEXT: successors: %bb.6(0x40000000), %bb.1(0x40000000)
+ ; MIPS32_PIC-NEXT: liveins: $a0, $t9, $v0
+ ; MIPS32_PIC-NEXT: {{ $}}
+ ; MIPS32_PIC-NEXT: [[ADDu:%[0-9]+]]:gpr32 = ADDu $v0, $t9
+ ; MIPS32_PIC-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; MIPS32_PIC-NEXT: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 7
+ ; MIPS32_PIC-NEXT: [[ORi1:%[0-9]+]]:gpr32 = ORi $zero, 3
+ ; MIPS32_PIC-NEXT: [[ORi2:%[0-9]+]]:gpr32 = ORi $zero, 2
+ ; MIPS32_PIC-NEXT: [[ORi3:%[0-9]+]]:gpr32 = ORi $zero, 1
+ ; MIPS32_PIC-NEXT: [[ORi4:%[0-9]+]]:gpr32 = ORi $zero, 0
+ ; MIPS32_PIC-NEXT: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
+ ; MIPS32_PIC-NEXT: [[ORi5:%[0-9]+]]:gpr32 = ORi $zero, 0
+ ; MIPS32_PIC-NEXT: [[SUBu:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[ORi5]]
+ ; MIPS32_PIC-NEXT: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[ORi]], [[SUBu]]
+ ; MIPS32_PIC-NEXT: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[SLTu]], 1
+ ; MIPS32_PIC-NEXT: BNE [[ANDi]], $zero, %bb.6, implicit-def dead $at
+ ; MIPS32_PIC-NEXT: {{ $}}
+ ; MIPS32_PIC-NEXT: bb.1.entry:
+ ; MIPS32_PIC-NEXT: successors: %bb.2(0x20000000), %bb.3(0x20000000), %bb.4(0x20000000), %bb.5(0x20000000)
+ ; MIPS32_PIC-NEXT: {{ $}}
+ ; MIPS32_PIC-NEXT: [[LW:%[0-9]+]]:gpr32 = LW [[ADDu]], target-flags(mips-got) %jump-table.0 :: (load (s32) from got)
+ ; MIPS32_PIC-NEXT: [[SLL:%[0-9]+]]:gpr32 = SLL [[SUBu]], 2
+ ; MIPS32_PIC-NEXT: [[ADDu1:%[0-9]+]]:gpr32 = ADDu [[LW]], [[SLL]]
+ ; MIPS32_PIC-NEXT: [[LW1:%[0-9]+]]:gpr32 = LW [[ADDu1]], target-flags(mips-abs-lo) %jump-table.0 :: (load (s32))
+ ; MIPS32_PIC-NEXT: [[ADDu2:%[0-9]+]]:gpr32 = ADDu [[LW1]], [[ADDu]]
+ ; MIPS32_PIC-NEXT: PseudoIndirectBranch [[ADDu2]]
+ ; MIPS32_PIC-NEXT: {{ $}}
+ ; MIPS32_PIC-NEXT: bb.2.sw.bb:
+ ; MIPS32_PIC-NEXT: $v0 = COPY [[ORi4]]
+ ; MIPS32_PIC-NEXT: RetRA implicit $v0
+ ; MIPS32_PIC-NEXT: {{ $}}
+ ; MIPS32_PIC-NEXT: bb.3.sw.bb1:
+ ; MIPS32_PIC-NEXT: $v0 = COPY [[ORi3]]
+ ; MIPS32_PIC-NEXT: RetRA implicit $v0
+ ; MIPS32_PIC-NEXT: {{ $}}
+ ; MIPS32_PIC-NEXT: bb.4.sw.bb2:
+ ; MIPS32_PIC-NEXT: $v0 = COPY [[ORi2]]
+ ; MIPS32_PIC-NEXT: RetRA implicit $v0
+ ; MIPS32_PIC-NEXT: {{ $}}
+ ; MIPS32_PIC-NEXT: bb.5.sw.bb3:
+ ; MIPS32_PIC-NEXT: $v0 = COPY [[ORi1]]
+ ; MIPS32_PIC-NEXT: RetRA implicit $v0
+ ; MIPS32_PIC-NEXT: {{ $}}
+ ; MIPS32_PIC-NEXT: bb.6.sw.default:
+ ; MIPS32_PIC-NEXT: successors: %bb.7(0x80000000)
+ ; MIPS32_PIC-NEXT: {{ $}}
+ ; MIPS32_PIC-NEXT: bb.7.sw.epilog:
+ ; MIPS32_PIC-NEXT: successors: %bb.13(0x40000000), %bb.8(0x40000000)
+ ; MIPS32_PIC-NEXT: {{ $}}
+ ; MIPS32_PIC-NEXT: [[ORi6:%[0-9]+]]:gpr32 = ORi $zero, 8
+ ; MIPS32_PIC-NEXT: [[SUBu1:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[ORi6]]
+ ; MIPS32_PIC-NEXT: [[SLTu1:%[0-9]+]]:gpr32 = SLTu [[ORi1]], [[SUBu1]]
+ ; MIPS32_PIC-NEXT: [[ANDi1:%[0-9]+]]:gpr32 = ANDi [[SLTu1]], 1
+ ; MIPS32_PIC-NEXT: BNE [[ANDi1]], $zero, %bb.13, implicit-def dead $at
+ ; MIPS32_PIC-NEXT: {{ $}}
+ ; MIPS32_PIC-NEXT: bb.8.sw.epilog:
+ ; MIPS32_PIC-NEXT: successors: %bb.9(0x20000000), %bb.10(0x20000000), %bb.11(0x20000000), %bb.12(0x20000000)
+ ; MIPS32_PIC-NEXT: {{ $}}
+ ; MIPS32_PIC-NEXT: [[LW2:%[0-9]+]]:gpr32 = LW [[ADDu]], target-flags(mips-got) %jump-table.1 :: (load (s32) from got)
+ ; MIPS32_PIC-NEXT: [[SLL1:%[0-9]+]]:gpr32 = SLL [[SUBu1]], 2
+ ; MIPS32_PIC-NEXT: [[ADDu3:%[0-9]+]]:gpr32 = ADDu [[LW2]], [[SLL1]]
+ ; MIPS32_PIC-NEXT: [[LW3:%[0-9]+]]:gpr32 = LW [[ADDu3]], target-flags(mips-abs-lo) %jump-table.1 :: (load (s32))
+ ; MIPS32_PIC-NEXT: [[ADDu4:%[0-9]+]]:gpr32 = ADDu [[LW3]], [[ADDu]]
+ ; MIPS32_PIC-NEXT: PseudoIndirectBranch [[ADDu4]]
+ ; MIPS32_PIC-NEXT: {{ $}}
+ ; MIPS32_PIC-NEXT: bb.9.sw.bb4:
+ ; MIPS32_PIC-NEXT: $v0 = COPY [[ORi4]]
+ ; MIPS32_PIC-NEXT: RetRA implicit $v0
+ ; MIPS32_PIC-NEXT: {{ $}}
+ ; MIPS32_PIC-NEXT: bb.10.sw.bb5:
+ ; MIPS32_PIC-NEXT: $v0 = COPY [[ORi3]]
+ ; MIPS32_PIC-NEXT: RetRA implicit $v0
+ ; MIPS32_PIC-NEXT: {{ $}}
+ ; MIPS32_PIC-NEXT: bb.11.sw.bb6:
+ ; MIPS32_PIC-NEXT: $v0 = COPY [[ORi2]]
+ ; MIPS32_PIC-NEXT: RetRA implicit $v0
+ ; MIPS32_PIC-NEXT: {{ $}}
+ ; MIPS32_PIC-NEXT: bb.12.sw.bb7:
+ ; MIPS32_PIC-NEXT: $v0 = COPY [[ORi1]]
+ ; MIPS32_PIC-NEXT: RetRA implicit $v0
+ ; MIPS32_PIC-NEXT: {{ $}}
+ ; MIPS32_PIC-NEXT: bb.13.sw.default8:
+ ; MIPS32_PIC-NEXT: $v0 = COPY [[ADDiu]]
+ ; MIPS32_PIC-NEXT: RetRA implicit $v0
bb.1.entry:
liveins: $a0
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/phi.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/phi.mir
index 77e5ee2fdcbc2e..44d31d99efcac3 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/phi.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/phi.mir
@@ -80,7 +80,7 @@ body: |
; MIPS32FP32-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32FP32-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
; MIPS32FP32-NEXT: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
- ; MIPS32FP32-NEXT: BNE [[ANDi]], $zero, %bb.1, implicit-def $at
+ ; MIPS32FP32-NEXT: BNE [[ANDi]], $zero, %bb.1, implicit-def dead $at
; MIPS32FP32-NEXT: J %bb.2, implicit-def dead $at
; MIPS32FP32-NEXT: {{ $}}
; MIPS32FP32-NEXT: bb.1.cond.true:
@@ -105,7 +105,7 @@ body: |
; MIPS32FP64-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32FP64-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
; MIPS32FP64-NEXT: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
- ; MIPS32FP64-NEXT: BNE [[ANDi]], $zero, %bb.1, implicit-def $at
+ ; MIPS32FP64-NEXT: BNE [[ANDi]], $zero, %bb.1, implicit-def dead $at
; MIPS32FP64-NEXT: J %bb.2, implicit-def dead $at
; MIPS32FP64-NEXT: {{ $}}
; MIPS32FP64-NEXT: bb.1.cond.true:
@@ -166,7 +166,7 @@ body: |
; MIPS32FP32-NEXT: [[ADDiu1:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.1, 0
; MIPS32FP32-NEXT: [[LW1:%[0-9]+]]:gpr32 = LW [[ADDiu1]], 0 :: (load (s32) from %fixed-stack.1)
; MIPS32FP32-NEXT: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
- ; MIPS32FP32-NEXT: BNE [[ANDi]], $zero, %bb.1, implicit-def $at
+ ; MIPS32FP32-NEXT: BNE [[ANDi]], $zero, %bb.1, implicit-def dead $at
; MIPS32FP32-NEXT: J %bb.2, implicit-def dead $at
; MIPS32FP32-NEXT: {{ $}}
; MIPS32FP32-NEXT: bb.1.cond.true:
@@ -197,7 +197,7 @@ body: |
; MIPS32FP64-NEXT: [[ADDiu1:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.1, 0
; MIPS32FP64-NEXT: [[LW1:%[0-9]+]]:gpr32 = LW [[ADDiu1]], 0 :: (load (s32) from %fixed-stack.1)
; MIPS32FP64-NEXT: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
- ; MIPS32FP64-NEXT: BNE [[ANDi]], $zero, %bb.1, implicit-def $at
+ ; MIPS32FP64-NEXT: BNE [[ANDi]], $zero, %bb.1, implicit-def dead $at
; MIPS32FP64-NEXT: J %bb.2, implicit-def dead $at
; MIPS32FP64-NEXT: {{ $}}
; MIPS32FP64-NEXT: bb.1.cond.true:
@@ -259,7 +259,7 @@ body: |
; MIPS32FP32-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32FP32-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
; MIPS32FP32-NEXT: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
- ; MIPS32FP32-NEXT: BNE [[ANDi]], $zero, %bb.1, implicit-def $at
+ ; MIPS32FP32-NEXT: BNE [[ANDi]], $zero, %bb.1, implicit-def dead $at
; MIPS32FP32-NEXT: J %bb.2, implicit-def dead $at
; MIPS32FP32-NEXT: {{ $}}
; MIPS32FP32-NEXT: bb.1.cond.true:
@@ -284,7 +284,7 @@ body: |
; MIPS32FP64-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32FP64-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
; MIPS32FP64-NEXT: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
- ; MIPS32FP64-NEXT: BNE [[ANDi]], $zero, %bb.1, implicit-def $at
+ ; MIPS32FP64-NEXT: BNE [[ANDi]], $zero, %bb.1, implicit-def dead $at
; MIPS32FP64-NEXT: J %bb.2, implicit-def dead $at
; MIPS32FP64-NEXT: {{ $}}
; MIPS32FP64-NEXT: bb.1.cond.true:
@@ -341,7 +341,7 @@ body: |
; MIPS32FP32-NEXT: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
; MIPS32FP32-NEXT: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load (s32) from %fixed-stack.0, align 8)
; MIPS32FP32-NEXT: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[LW]], 1
- ; MIPS32FP32-NEXT: BNE [[ANDi]], $zero, %bb.1, implicit-def $at
+ ; MIPS32FP32-NEXT: BNE [[ANDi]], $zero, %bb.1, implicit-def dead $at
; MIPS32FP32-NEXT: J %bb.2, implicit-def dead $at
; MIPS32FP32-NEXT: {{ $}}
; MIPS32FP32-NEXT: bb.1.cond.true:
@@ -367,7 +367,7 @@ body: |
; MIPS32FP64-NEXT: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
; MIPS32FP64-NEXT: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load (s32) from %fixed-stack.0, align 8)
; MIPS32FP64-NEXT: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[LW]], 1
- ; MIPS32FP64-NEXT: BNE [[ANDi]], $zero, %bb.1, implicit-def $at
+ ; MIPS32FP64-NEXT: BNE [[ANDi]], $zero, %bb.1, implicit-def dead $at
; MIPS32FP64-NEXT: J %bb.2, implicit-def dead $at
; MIPS32FP64-NEXT: {{ $}}
; MIPS32FP64-NEXT: bb.1.cond.true:
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