[llvm] [GlobalISel][RISCV] Use constant pool for large integer constants. (PR #81101)
Mikhail Gudim via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 8 21:49:09 PST 2024
https://github.com/mgudim updated https://github.com/llvm/llvm-project/pull/81101
>From 5259af373f973b3499f4f3bf47eb461526069862 Mon Sep 17 00:00:00 2001
From: Mikhail Gudim <mgudim at gmail.com>
Date: Thu, 8 Feb 2024 00:12:23 -0500
Subject: [PATCH 1/3] [GlobalISel][RISCV] Use constant pool for large integer
constants.
We apply custom lowering to 64 bit constants where we use the same logic
as in non-global isel: if materializing in registers is too expensive,
we emit a load from constant pool. Later, during instruction selection,
constant pool address is generated using `selectAddr`.
---
.../Target/RISCV/GISel/RISCVLegalizerInfo.cpp | 91 ++++++++++++++++++-
.../Target/RISCV/GISel/RISCVLegalizerInfo.h | 4 +
.../legalizer/legalize-bitreverse-rv64.mir | 33 ++++---
.../legalizer/legalize-const-rv64.mir | 20 ++--
4 files changed, 124 insertions(+), 24 deletions(-)
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index ae02e86baf6e8..e238a028706fc 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -11,11 +11,14 @@
//===----------------------------------------------------------------------===//
#include "RISCVLegalizerInfo.h"
+#include "MCTargetDesc/RISCVMatInt.h"
#include "RISCVMachineFunctionInfo.h"
#include "RISCVSubtarget.h"
+#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h"
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
+#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/CodeGen/ValueTypes.h"
@@ -182,7 +185,13 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
CTPOPActions.maxScalar(0, sXLen).scalarSameSizeAs(1, 0).lower();
}
- getActionDefinitionsBuilder({G_CONSTANT, G_IMPLICIT_DEF})
+ auto &ConstantActions = getActionDefinitionsBuilder(G_CONSTANT);
+ if (ST.is64Bit())
+ ConstantActions.customFor({s64});
+ ConstantActions.legalFor({s32, p0}).widenScalarToNextPow2(0).clampScalar(
+ 0, s32, sXLen);
+
+ getActionDefinitionsBuilder(G_IMPLICIT_DEF)
.legalFor({s32, sXLen, p0})
.widenScalarToNextPow2(0)
.clampScalar(0, s32, sXLen);
@@ -451,17 +460,97 @@ bool RISCVLegalizerInfo::legalizeVAStart(MachineInstr &MI,
return true;
}
+bool RISCVLegalizerInfo::shouldBeInConstantPool(APInt APImm,
+ bool shouldOptForSize) const {
+ unsigned BitWidth = APImm.getBitWidth();
+ assert(BitWidth == 32 || BitWidth == 64);
+ uint64_t Imm = APImm.getZExtValue();
+ // All simm32 constants should be handled by isel.
+ // NOTE: The getMaxBuildIntsCost call below should return a value >= 2 making
+ // this check redundant, but small immediates are common so this check
+ // should have better compile time.
+ if (isInt<32>(Imm))
+ return false;
+
+ // We only need to cost the immediate, if constant pool lowering is enabled.
+ if (!STI.useConstantPoolForLargeInts())
+ return false;
+
+ RISCVMatInt::InstSeq Seq = RISCVMatInt::generateInstSeq(Imm, STI);
+ if (Seq.size() <= STI.getMaxBuildIntsCost())
+ return false;
+
+ // Optimizations below are disabled for opt size. If we're optimizing for
+ // size, use a constant pool.
+ if (shouldOptForSize)
+ return true;
+ //
+ // Special case. See if we can build the constant as (ADD (SLLI X, C), X) do
+ // that if it will avoid a constant pool.
+ // It will require an extra temporary register though.
+ // If we have Zba we can use (ADD_UW X, (SLLI X, 32)) to handle cases where
+ // low and high 32 bits are the same and bit 31 and 63 are set.
+ unsigned ShiftAmt, AddOpc;
+ RISCVMatInt::InstSeq SeqLo =
+ RISCVMatInt::generateTwoRegInstSeq(Imm, STI, ShiftAmt, AddOpc);
+ if (!SeqLo.empty() && (SeqLo.size() + 2) <= STI.getMaxBuildIntsCost())
+ return false;
+
+ return true;
+}
+
+// TODO: This is almost the same as LegalizerHelper::lowerFConstant and is
+// target-independent. Should we move this to LegalizeHelper?
+bool RISCVLegalizerInfo::emitLoadFromConstantPool(
+ Register DstReg, const Constant *ConstVal,
+ MachineIRBuilder &MIRBuilder) const {
+ MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
+ MachineFunction &MF = MIRBuilder.getMF();
+ const DataLayout &DL = MIRBuilder.getDataLayout();
+ LLVMContext &Ctx = MF.getFunction().getContext();
+ unsigned AddrSpace = DL.getDefaultGlobalsAddressSpace();
+ LLT AddrPtrTy = LLT::pointer(AddrSpace, DL.getPointerSizeInBits(AddrSpace));
+ LLT DstLLT = MRI.getType(DstReg);
+
+ Align Alignment = Align(DL.getABITypeAlign(getTypeForLLT(DstLLT, Ctx)));
+
+ auto Addr = MIRBuilder.buildConstantPool(
+ AddrPtrTy,
+ MF.getConstantPool()->getConstantPoolIndex(ConstVal, Alignment));
+ MachineMemOperand *MMO =
+ MF.getMachineMemOperand(MachinePointerInfo::getConstantPool(MF),
+ MachineMemOperand::MOLoad, DstLLT, Alignment);
+
+ MIRBuilder.buildLoadInstr(TargetOpcode::G_LOAD, DstReg, Addr, *MMO);
+ return true;
+}
+
bool RISCVLegalizerInfo::legalizeCustom(
LegalizerHelper &Helper, MachineInstr &MI,
LostDebugLocObserver &LocObserver) const {
MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
GISelChangeObserver &Observer = Helper.Observer;
+ MachineFunction &MF = *MI.getParent()->getParent();
switch (MI.getOpcode()) {
default:
// No idea what to do.
return false;
case TargetOpcode::G_ABS:
return Helper.lowerAbsToMaxNeg(MI);
+ // TODO: G_FCONSTANT
+ case TargetOpcode::G_CONSTANT: {
+ const Function &F = MF.getFunction();
+ // TODO: if PSI and BFI are present, add " ||
+ // llvm::shouldOptForSize(*CurMBB, PSI, BFI)".
+ bool shouldOptForSize = F.hasOptSize() || F.hasMinSize();
+ const ConstantInt *ConstVal = MI.getOperand(1).getCImm();
+ if (!shouldBeInConstantPool(ConstVal->getValue(), shouldOptForSize))
+ return true;
+ emitLoadFromConstantPool(MI.getOperand(0).getReg(),
+ MI.getOperand(1).getCImm(), MIRBuilder);
+ MI.eraseFromParent();
+ return true;
+ }
case TargetOpcode::G_SHL:
case TargetOpcode::G_ASHR:
case TargetOpcode::G_LSHR:
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h
index f3ec6be167347..2845902d3d3ab 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h
@@ -14,6 +14,7 @@
#define LLVM_LIB_TARGET_RISCV_RISCVMACHINELEGALIZER_H
#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
+#include "llvm/CodeGen/Register.h"
namespace llvm {
@@ -36,6 +37,9 @@ class RISCVLegalizerInfo : public LegalizerInfo {
MachineInstr &MI) const override;
private:
+ bool shouldBeInConstantPool(APInt APImm, bool shouldOptForSize) const;
+ bool emitLoadFromConstantPool(Register DstReg, const Constant *CPVal,
+ MachineIRBuilder &MIRBuilder) const;
bool legalizeShlAshrLshr(MachineInstr &MI, MachineIRBuilder &MIRBuilder,
GISelChangeObserver &Observer) const;
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bitreverse-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bitreverse-rv64.mir
index f4a098dd28c41..d147350465166 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bitreverse-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bitreverse-rv64.mir
@@ -220,25 +220,28 @@ body: |
; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[LSHR3]], [[C5]]
; CHECK-NEXT: [[OR6:%[0-9]+]]:_(s64) = G_OR [[OR5]], [[AND5]]
; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1085102592571150096
- ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[OR6]], [[C8]]
+ ; CHECK-NEXT: [[CONSTANT_POOL:%[0-9]+]]:_(p0) = G_CONSTANT_POOL %const.2
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[CONSTANT_POOL]](p0) :: (load (s64) from constant-pool)
+ ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[OR6]], [[LOAD]]
; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[AND6]], [[C7]](s64)
; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s64) = G_SHL [[OR6]], [[C7]](s64)
- ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[SHL4]], [[C8]]
+ ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[SHL4]], [[LOAD]]
; CHECK-NEXT: [[OR7:%[0-9]+]]:_(s64) = G_OR [[LSHR4]], [[AND7]]
- ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 -3689348814741910324
- ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[OR7]], [[C10]]
- ; CHECK-NEXT: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[AND8]], [[C9]](s64)
- ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s64) = G_SHL [[OR7]], [[C9]](s64)
- ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[SHL5]], [[C10]]
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[CONSTANT_POOL1:%[0-9]+]]:_(p0) = G_CONSTANT_POOL %const.1
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[CONSTANT_POOL1]](p0) :: (load (s64) from constant-pool)
+ ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[OR7]], [[LOAD1]]
+ ; CHECK-NEXT: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[AND8]], [[C8]](s64)
+ ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s64) = G_SHL [[OR7]], [[C8]](s64)
+ ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[SHL5]], [[LOAD1]]
; CHECK-NEXT: [[OR8:%[0-9]+]]:_(s64) = G_OR [[LSHR5]], [[AND9]]
- ; CHECK-NEXT: [[C11:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s64) = G_CONSTANT i64 -6148914691236517206
- ; CHECK-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[OR8]], [[C12]]
- ; CHECK-NEXT: [[LSHR6:%[0-9]+]]:_(s64) = G_LSHR [[AND10]], [[C11]](s64)
- ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(s64) = G_SHL [[OR8]], [[C11]](s64)
- ; CHECK-NEXT: [[AND11:%[0-9]+]]:_(s64) = G_AND [[SHL6]], [[C12]]
+ ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[CONSTANT_POOL2:%[0-9]+]]:_(p0) = G_CONSTANT_POOL %const.0
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s64) = G_LOAD [[CONSTANT_POOL2]](p0) :: (load (s64) from constant-pool)
+ ; CHECK-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[OR8]], [[LOAD2]]
+ ; CHECK-NEXT: [[LSHR6:%[0-9]+]]:_(s64) = G_LSHR [[AND10]], [[C9]](s64)
+ ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(s64) = G_SHL [[OR8]], [[C9]](s64)
+ ; CHECK-NEXT: [[AND11:%[0-9]+]]:_(s64) = G_AND [[SHL6]], [[LOAD2]]
; CHECK-NEXT: [[OR9:%[0-9]+]]:_(s64) = G_OR [[LSHR6]], [[AND11]]
; CHECK-NEXT: $x10 = COPY [[OR9]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-const-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-const-rv64.mir
index fa57295d3a540..63f93d13c0463 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-const-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-const-rv64.mir
@@ -6,8 +6,9 @@ name: const_i8
body: |
bb.0.entry:
; CHECK-LABEL: name: const_i8
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -127
- ; CHECK-NEXT: $x10 = COPY [[C]](s64)
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -127
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s8) = G_CONSTANT i8 129
%1:_(s64) = G_ANYEXT %0(s8)
@@ -20,8 +21,9 @@ name: const_i15
body: |
bb.0.entry:
; CHECK-LABEL: name: const_i15
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
- ; CHECK-NEXT: $x10 = COPY [[C]](s64)
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s15) = G_CONSTANT i15 15
%1:_(s64) = G_ANYEXT %0(s15)
@@ -34,8 +36,9 @@ name: const_i16
body: |
bb.0.entry:
; CHECK-LABEL: name: const_i16
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 767
- ; CHECK-NEXT: $x10 = COPY [[C]](s64)
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 767
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s16) = G_CONSTANT i16 -64769
%1:_(s64) = G_ANYEXT %0(s16)
@@ -48,8 +51,9 @@ name: const_i32
body: |
bb.0.entry:
; CHECK-LABEL: name: const_i32
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -64769
- ; CHECK-NEXT: $x10 = COPY [[C]](s64)
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -64769
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s32) = G_CONSTANT i32 -64769
%1:_(s64) = G_ANYEXT %0(s32)
>From ae82b9bae0aea042c81573cbd10009ba214f6a60 Mon Sep 17 00:00:00 2001
From: Mikhail Gudim <mgudim at gmail.com>
Date: Fri, 9 Feb 2024 00:42:08 -0500
Subject: [PATCH 2/3] Addressed review comments.
---
.../Target/RISCV/GISel/RISCVLegalizerInfo.cpp | 24 +++++++++----------
.../Target/RISCV/GISel/RISCVLegalizerInfo.h | 2 +-
2 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index e238a028706fc..1b3a8f51dd34a 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -186,10 +186,13 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
}
auto &ConstantActions = getActionDefinitionsBuilder(G_CONSTANT);
+ ConstantActions
+ .legalFor({s32, p0})
if (ST.is64Bit())
ConstantActions.customFor({s64});
- ConstantActions.legalFor({s32, p0}).widenScalarToNextPow2(0).clampScalar(
- 0, s32, sXLen);
+ ConstantActions
+ .widenScalarToNextPow2(0)
+ .clampScalar(0, s32, sXLen);
getActionDefinitionsBuilder(G_IMPLICIT_DEF)
.legalFor({s32, sXLen, p0})
@@ -461,10 +464,10 @@ bool RISCVLegalizerInfo::legalizeVAStart(MachineInstr &MI,
}
bool RISCVLegalizerInfo::shouldBeInConstantPool(APInt APImm,
- bool shouldOptForSize) const {
+ bool ShouldOptForSize) const {
unsigned BitWidth = APImm.getBitWidth();
assert(BitWidth == 32 || BitWidth == 64);
- uint64_t Imm = APImm.getZExtValue();
+ uint64_t Imm = APImm.getSExtValue();
// All simm32 constants should be handled by isel.
// NOTE: The getMaxBuildIntsCost call below should return a value >= 2 making
// this check redundant, but small immediates are common so this check
@@ -482,7 +485,7 @@ bool RISCVLegalizerInfo::shouldBeInConstantPool(APInt APImm,
// Optimizations below are disabled for opt size. If we're optimizing for
// size, use a constant pool.
- if (shouldOptForSize)
+ if (ShouldOptForSize)
return true;
//
// Special case. See if we can build the constant as (ADD (SLLI X, C), X) do
@@ -493,10 +496,7 @@ bool RISCVLegalizerInfo::shouldBeInConstantPool(APInt APImm,
unsigned ShiftAmt, AddOpc;
RISCVMatInt::InstSeq SeqLo =
RISCVMatInt::generateTwoRegInstSeq(Imm, STI, ShiftAmt, AddOpc);
- if (!SeqLo.empty() && (SeqLo.size() + 2) <= STI.getMaxBuildIntsCost())
- return false;
-
- return true;
+ return !(!SeqLo.empty() && (SeqLo.size() + 2) <= STI.getMaxBuildIntsCost());
}
// TODO: This is almost the same as LegalizerHelper::lowerFConstant and is
@@ -512,7 +512,7 @@ bool RISCVLegalizerInfo::emitLoadFromConstantPool(
LLT AddrPtrTy = LLT::pointer(AddrSpace, DL.getPointerSizeInBits(AddrSpace));
LLT DstLLT = MRI.getType(DstReg);
- Align Alignment = Align(DL.getABITypeAlign(getTypeForLLT(DstLLT, Ctx)));
+ Align Alignment(DL.getABITypeAlign(getTypeForLLT(DstLLT, Ctx)));
auto Addr = MIRBuilder.buildConstantPool(
AddrPtrTy,
@@ -542,9 +542,9 @@ bool RISCVLegalizerInfo::legalizeCustom(
const Function &F = MF.getFunction();
// TODO: if PSI and BFI are present, add " ||
// llvm::shouldOptForSize(*CurMBB, PSI, BFI)".
- bool shouldOptForSize = F.hasOptSize() || F.hasMinSize();
+ bool ShouldOptForSize = F.hasOptSize() || F.hasMinSize();
const ConstantInt *ConstVal = MI.getOperand(1).getCImm();
- if (!shouldBeInConstantPool(ConstVal->getValue(), shouldOptForSize))
+ if (!shouldBeInConstantPool(ConstVal->getValue(), ShouldOptForSize))
return true;
emitLoadFromConstantPool(MI.getOperand(0).getReg(),
MI.getOperand(1).getCImm(), MIRBuilder);
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h
index 2845902d3d3ab..046555f3a3e9e 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h
@@ -37,7 +37,7 @@ class RISCVLegalizerInfo : public LegalizerInfo {
MachineInstr &MI) const override;
private:
- bool shouldBeInConstantPool(APInt APImm, bool shouldOptForSize) const;
+ bool shouldBeInConstantPool(APInt APImm, bool ShouldOptForSize) const;
bool emitLoadFromConstantPool(Register DstReg, const Constant *CPVal,
MachineIRBuilder &MIRBuilder) const;
bool legalizeShlAshrLshr(MachineInstr &MI, MachineIRBuilder &MIRBuilder,
>From cf32cc3e57f588c78674c5729b8d3f8e158af3fb Mon Sep 17 00:00:00 2001
From: Mikhail Gudim <mgudim at gmail.com>
Date: Fri, 9 Feb 2024 00:48:40 -0500
Subject: [PATCH 3/3] clang-format
---
llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp | 10 +++-------
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index 1b3a8f51dd34a..b899dcff6a3b0 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -186,13 +186,9 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
}
auto &ConstantActions = getActionDefinitionsBuilder(G_CONSTANT);
- ConstantActions
- .legalFor({s32, p0})
- if (ST.is64Bit())
- ConstantActions.customFor({s64});
- ConstantActions
- .widenScalarToNextPow2(0)
- .clampScalar(0, s32, sXLen);
+ ConstantActions.legalFor({s32, p0}) if (ST.is64Bit())
+ ConstantActions.customFor({s64});
+ ConstantActions.widenScalarToNextPow2(0).clampScalar(0, s32, sXLen);
getActionDefinitionsBuilder(G_IMPLICIT_DEF)
.legalFor({s32, sXLen, p0})
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