[llvm] [RISCV][NFCI] Use isADDLike helper for or_is_add PatFrag (PR #81137)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Alex Bradbury (asb)

<details>
<summary>Changes</summary>

This should be equivalent.

---
Full diff: https://github.com/llvm/llvm-project/pull/81137.diff


1 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.td (+1-5) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 518982441e7c0..aa84a4553ec1f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1249,11 +1249,7 @@ def : PatGprUimmLog2XLen<sra, SRAI>;
 // Select 'or' as ADDI if the immediate bits are known to be 0 in $rs1. This
 // can improve compressibility.
 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
-  if (N->getFlags().hasDisjoint())
-    return true;
-  KnownBits Known0 = CurDAG->computeKnownBits(N->getOperand(0), 0);
-  KnownBits Known1 = CurDAG->computeKnownBits(N->getOperand(1), 0);
-  return KnownBits::haveNoCommonBitsSet(Known0, Known1);
+  return CurDAG->isADDLike(SDValue(N, 0));
 }]>;
 def : PatGprSimm12<or_is_add, ADDI>;
 

``````````

</details>


https://github.com/llvm/llvm-project/pull/81137