[llvm] [RFC] implement convergence control in MIR using SelectionDAG (PR #71785)

[Sameer Sahasrabuddhe via llvm-commits]

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@@ -1191,6 +1191,21 @@ EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
     }
   }
 
+  if (Opc == TargetOpcode::CONVERGENCECTRL_GLUE) {
+    MIB->getOperand(0).setIsKill(false);
+  }
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ssahasra wrote:

I spoke too soon. I was running the wrong tests. The problem is that just after `amdgpu-isel`, I get MIR that looks like this:

>   %1:sreg_64 = CONVERGENCECTRL_ANCHOR
  CONVERGENCECTRL_GLUE **killed** %1:sreg_64
  %2:sreg_32 = V_READFIRSTLANE_B32 %0:vgpr_32, implicit $exec, implicit %1:sreg_64

At this same point InstrEmitter, I am doing two things: remove the killed flag, and add the implicit use to V_READFIRSTLANE. Is there a better way to do this?

https://github.com/llvm/llvm-project/pull/71785