[llvm] [GISel] Add support for scalable vectors in getLCMType (PR #80306)

[Michael Maitland via llvm-commits]

michaelmaitland wrote:

> Up to you, but to me it looks like misuse. I can unmerge 32bit into 4 8bit registers. But unmerging scalable vectors looks strange. Then you would need vector registers of different sizes. For AArch64 there are 32 scalable vector registers, Z0-Z31. They all have the same unknown scalable size.

I am happy to have a discussion and see if we can come to an agreement.

I am not seeing a problem. As I see it, there is a contract that the destination types must be able to hold all the elements of the source type on an umerge (and the opposite for a merge). I believe that this is occurring with scalable vectors. I described this in my previous comment in more detail. The key is that vscale is a runtime constant which will be the same for both types, and the minimum number of elements is guaranteed to fit. Since the vscale is the same, the actual number of elements is guaranteed to fit.

> But unmerging scalable vectors looks strange. Then you would need vector registers of different sizes.

Isn't it the case that you would need vector registers of different sizes for fixed vectors too? For example, a `4 x i32` becomes two `2 x i32`. A `4 x i32` is a different size compared to `2 x i32`. For scalable vectors a `vscale x 4 x i32` becomes two `vscale x 2 x i32`. This is also two different sizes for the scalable vectors, since `vscale` is just a runtime constant.

Why is this a problem?

> For AArch64 there are 32 scalable vector registers, Z0-Z31. They all have the same unknown scalable size.

I'm not sure, but because you bring up physical registers, it sounds like you are having contention with the following
```
%0_:(vscale x N x sM)= G_IMPLICIT_DEF
$physicalVectorRegister = G_COPY %0 // How do I know that %0 fits in physicalVectorRegister
```
If this is the case, I don't think you have a problem with G_MERGE/UNMERGE. I think you have a problem with how we can map scalable vector typed virtual registers onto physical registers. On RISC-V, we have a mapping between LLVM types and physical registers. I don't think this is a discussion relevant to this PR, however I am happy to have it in a forum such as a GitHub issue.

CC: @topperc 

https://github.com/llvm/llvm-project/pull/80306