[llvm] [RISCV][GISEL] Add IRTranslation for shufflevector on scalable vector types (PR #80378)
Michael Maitland via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 5 07:41:19 PST 2024
https://github.com/michaelmaitland updated https://github.com/llvm/llvm-project/pull/80378
>From 55d3f3f02675872fccc0c1442e57ac8b88bd0a85 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Thu, 1 Feb 2024 08:22:22 -0800
Subject: [PATCH 1/5] [GISel] Add support for scalable vectors in getLCMType
This function can be called from buildCopyToRegs where at least one of the types
is a scalable vector type. This function crashed because it did not know
how to handle scalable vector types.
This patch extends the functionality of getLCMType to handle when at
least one of the types is a scalable vector. getLCMType between a fixed
and scalable vector is not implemented since the docstring of the
function explains that getLCMType is used to build MERGE/UNMERGE
instructions and we will never build a MERGE/UNMERGE between fixed and scalable
vectors.
---
llvm/include/llvm/CodeGen/GlobalISel/Utils.h | 9 +-
llvm/lib/CodeGen/GlobalISel/Utils.cpp | 88 ++++++++++++-------
.../CodeGen/GlobalISel/GISelUtilsTest.cpp | 87 ++++++++++++++++++
3 files changed, 149 insertions(+), 35 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/Utils.h b/llvm/include/llvm/CodeGen/GlobalISel/Utils.h
index bf02911e19351..c96e4217d21f0 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/Utils.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/Utils.h
@@ -343,10 +343,13 @@ Register getFunctionLiveInPhysReg(MachineFunction &MF,
const TargetRegisterClass &RC,
const DebugLoc &DL, LLT RegTy = LLT());
-/// Return the least common multiple type of \p OrigTy and \p TargetTy, by changing the
-/// number of vector elements or scalar bitwidth. The intent is a
+/// Return the least common multiple type of \p OrigTy and \p TargetTy, by
+/// changing the number of vector elements or scalar bitwidth. The intent is a
/// G_MERGE_VALUES, G_BUILD_VECTOR, or G_CONCAT_VECTORS can be constructed from
-/// \p OrigTy elements, and unmerged into \p TargetTy
+/// \p OrigTy elements, and unmerged into \p TargetTy. It is an error to call
+/// this function where one argument is a fixed vector and the other is a
+/// scalable vector, since it is illegal to build a G_{MERGE|UNMERGE}_VALUES
+/// between fixed and scalable vectors.
LLVM_READNONE
LLT getLCMType(LLT OrigTy, LLT TargetTy);
diff --git a/llvm/lib/CodeGen/GlobalISel/Utils.cpp b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
index aed826a9cbc54..c79cb6c77f2f0 100644
--- a/llvm/lib/CodeGen/GlobalISel/Utils.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
@@ -1071,49 +1071,73 @@ void llvm::getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU) {
}
LLT llvm::getLCMType(LLT OrigTy, LLT TargetTy) {
- const unsigned OrigSize = OrigTy.getSizeInBits();
- const unsigned TargetSize = TargetTy.getSizeInBits();
-
- if (OrigSize == TargetSize)
+ if (OrigTy.getSizeInBits() == TargetTy.getSizeInBits())
return OrigTy;
- if (OrigTy.isVector()) {
- const LLT OrigElt = OrigTy.getElementType();
-
- if (TargetTy.isVector()) {
- const LLT TargetElt = TargetTy.getElementType();
+ if (OrigTy.isVector() && TargetTy.isVector()) {
+ LLT OrigElt = OrigTy.getElementType();
+ LLT TargetElt = TargetTy.getElementType();
- if (OrigElt.getSizeInBits() == TargetElt.getSizeInBits()) {
- int GCDElts =
- std::gcd(OrigTy.getNumElements(), TargetTy.getNumElements());
- // Prefer the original element type.
- ElementCount Mul = OrigTy.getElementCount() * TargetTy.getNumElements();
- return LLT::vector(Mul.divideCoefficientBy(GCDElts),
- OrigTy.getElementType());
- }
- } else {
- if (OrigElt.getSizeInBits() == TargetSize)
- return OrigTy;
+ // TODO: The docstring for this function says the intention is to use this
+ // function to build MERGE/UNMERGE instructions. It won't be the case that
+ // we generate a MERGE/UNMERGE between fixed and scalable vector types. We
+ // could implement getLCMType between the two in the future if there was a
+ // need, but it is not worth it now as this function should not be used in
+ // that way.
+ if ((OrigTy.isScalableVector() && TargetTy.isFixedVector()) ||
+ (OrigTy.isFixedVector() && TargetTy.isScalableVector()))
+ llvm_unreachable(
+ "getLCMType not implemented between fixed and scalable vectors.");
+
+ if (OrigElt.getSizeInBits() == TargetElt.getSizeInBits()) {
+ int GCDMinElts = std::gcd(OrigTy.getElementCount().getKnownMinValue(),
+ TargetTy.getElementCount().getKnownMinValue());
+ // Prefer the original element type.
+ ElementCount Mul = OrigTy.getElementCount().multiplyCoefficientBy(
+ TargetTy.getElementCount().getKnownMinValue());
+ return LLT::vector(Mul.divideCoefficientBy(GCDMinElts),
+ OrigTy.getElementType());
}
-
- unsigned LCMSize = std::lcm(OrigSize, TargetSize);
- return LLT::fixed_vector(LCMSize / OrigElt.getSizeInBits(), OrigElt);
+ unsigned LCM = std::lcm(OrigTy.getElementCount().getKnownMinValue() *
+ OrigElt.getSizeInBits().getFixedValue(),
+ TargetTy.getElementCount().getKnownMinValue() *
+ TargetElt.getSizeInBits().getFixedValue());
+ return LLT::vector(
+ ElementCount::get(LCM / OrigElt.getSizeInBits(), OrigTy.isScalable()),
+ OrigElt);
}
- if (TargetTy.isVector()) {
- unsigned LCMSize = std::lcm(OrigSize, TargetSize);
- return LLT::fixed_vector(LCMSize / OrigSize, OrigTy);
+ // One type is scalar, one type is vector
+ if (OrigTy.isVector() || TargetTy.isVector()) {
+ LLT VecTy = OrigTy.isVector() ? OrigTy : TargetTy;
+ LLT ScalarTy = OrigTy.isVector() ? TargetTy : OrigTy;
+ LLT EltTy = VecTy.getElementType();
+ LLT OrigEltTy = OrigTy.isVector() ? OrigTy.getElementType() : OrigTy;
+
+ // Prefer scalar type from OrigTy.
+ if (EltTy.getSizeInBits() == ScalarTy.getSizeInBits())
+ return LLT::vector(VecTy.getElementCount(), OrigEltTy);
+
+ // Different size scalars. Create vector with the same total size.
+ // LCM will take fixed/scalable from VecTy.
+ unsigned LCM = std::lcm(EltTy.getSizeInBits().getFixedValue() *
+ VecTy.getElementCount().getKnownMinValue(),
+ ScalarTy.getSizeInBits().getFixedValue());
+ // Prefer type from OrigTy
+ return LLT::vector(ElementCount::get(LCM / OrigEltTy.getSizeInBits(),
+ VecTy.getElementCount().isScalable()),
+ OrigEltTy);
}
- unsigned LCMSize = std::lcm(OrigSize, TargetSize);
-
+ // At this point, both types are scalars of different size
+ unsigned LCM = std::lcm(OrigTy.getSizeInBits().getFixedValue(),
+ TargetTy.getSizeInBits().getFixedValue());
// Preserve pointer types.
- if (LCMSize == OrigSize)
+ if (LCM == OrigTy.getSizeInBits())
return OrigTy;
- if (LCMSize == TargetSize)
+ if (LCM == TargetTy.getSizeInBits())
return TargetTy;
-
- return LLT::scalar(LCMSize);
+ return LLT::scalar(LCM);
}
LLT llvm::getCoverTy(LLT OrigTy, LLT TargetTy) {
diff --git a/llvm/unittests/CodeGen/GlobalISel/GISelUtilsTest.cpp b/llvm/unittests/CodeGen/GlobalISel/GISelUtilsTest.cpp
index 8fda332d5c054..92bd0a36b82b4 100644
--- a/llvm/unittests/CodeGen/GlobalISel/GISelUtilsTest.cpp
+++ b/llvm/unittests/CodeGen/GlobalISel/GISelUtilsTest.cpp
@@ -46,6 +46,37 @@ static const LLT V6P0 = LLT::fixed_vector(6, P0);
static const LLT V2P1 = LLT::fixed_vector(2, P1);
static const LLT V4P1 = LLT::fixed_vector(4, P1);
+static const LLT NXV1S1 = LLT::scalable_vector(1, S1);
+static const LLT NXV2S1 = LLT::scalable_vector(2, S1);
+static const LLT NXV3S1 = LLT::scalable_vector(3, S1);
+static const LLT NXV4S1 = LLT::scalable_vector(4, S1);
+static const LLT NXV12S1 = LLT::scalable_vector(12, S1);
+static const LLT NXV32S1 = LLT::scalable_vector(32, S1);
+static const LLT NXV64S1 = LLT::scalable_vector(64, S1);
+static const LLT NXV128S1 = LLT::scalable_vector(128, S1);
+static const LLT NXV384S1 = LLT::scalable_vector(384, S1);
+
+static const LLT NXV1S32 = LLT::scalable_vector(1, S32);
+static const LLT NXV2S32 = LLT::scalable_vector(2, S32);
+static const LLT NXV3S32 = LLT::scalable_vector(3, S32);
+static const LLT NXV4S32 = LLT::scalable_vector(4, S32);
+static const LLT NXV8S32 = LLT::scalable_vector(8, S32);
+static const LLT NXV12S32 = LLT::scalable_vector(12, S32);
+static const LLT NXV24S32 = LLT::scalable_vector(24, S32);
+
+static const LLT NXV1S64 = LLT::scalable_vector(1, S64);
+static const LLT NXV2S64 = LLT::scalable_vector(2, S64);
+static const LLT NXV3S64 = LLT::scalable_vector(3, S64);
+static const LLT NXV4S64 = LLT::scalable_vector(4, S64);
+static const LLT NXV6S64 = LLT::scalable_vector(6, S64);
+static const LLT NXV12S64 = LLT::scalable_vector(12, S64);
+
+static const LLT NXV1P0 = LLT::scalable_vector(1, P0);
+static const LLT NXV2P0 = LLT::scalable_vector(2, P0);
+static const LLT NXV3P0 = LLT::scalable_vector(3, P0);
+static const LLT NXV4P0 = LLT::scalable_vector(4, P0);
+static const LLT NXV12P0 = LLT::scalable_vector(12, P0);
+
TEST(GISelUtilsTest, getGCDType) {
EXPECT_EQ(S1, getGCDType(S1, S1));
EXPECT_EQ(S32, getGCDType(S32, S32));
@@ -244,6 +275,62 @@ TEST(GISelUtilsTest, getLCMType) {
EXPECT_EQ(V2S64, getLCMType(V2S64, P1));
EXPECT_EQ(V4P1, getLCMType(P1, V2S64));
+
+ // Scalable, Scalable
+ EXPECT_EQ(NXV32S1, getLCMType(NXV1S1, NXV1S32));
+ EXPECT_EQ(NXV1S64, getLCMType(NXV1S64, NXV1S32));
+ EXPECT_EQ(NXV2S32, getLCMType(NXV1S32, NXV1S64));
+ EXPECT_EQ(NXV1P0, getLCMType(NXV1P0, NXV1S64));
+ EXPECT_EQ(NXV1S64, getLCMType(NXV1S64, NXV1P0));
+
+ EXPECT_EQ(NXV128S1, getLCMType(NXV4S1, NXV4S32));
+ EXPECT_EQ(NXV4S64, getLCMType(NXV4S64, NXV4S32));
+ EXPECT_EQ(NXV8S32, getLCMType(NXV4S32, NXV4S64));
+ EXPECT_EQ(NXV4P0, getLCMType(NXV4P0, NXV4S64));
+ EXPECT_EQ(NXV4S64, getLCMType(NXV4S64, NXV4P0));
+
+ EXPECT_EQ(NXV64S1, getLCMType(NXV4S1, NXV2S32));
+ EXPECT_EQ(NXV4S64, getLCMType(NXV4S64, NXV2S32));
+ EXPECT_EQ(NXV4S32, getLCMType(NXV4S32, NXV2S64));
+ EXPECT_EQ(NXV4P0, getLCMType(NXV4P0, NXV2S64));
+ EXPECT_EQ(NXV4S64, getLCMType(NXV4S64, NXV2P0));
+
+ EXPECT_EQ(NXV128S1, getLCMType(NXV2S1, NXV4S32));
+ EXPECT_EQ(NXV2S64, getLCMType(NXV2S64, NXV4S32));
+ EXPECT_EQ(NXV8S32, getLCMType(NXV2S32, NXV4S64));
+ EXPECT_EQ(NXV4P0, getLCMType(NXV2P0, NXV4S64));
+ EXPECT_EQ(NXV4S64, getLCMType(NXV2S64, NXV4P0));
+
+ EXPECT_EQ(NXV384S1, getLCMType(NXV3S1, NXV4S32));
+ EXPECT_EQ(NXV6S64, getLCMType(NXV3S64, NXV4S32));
+ EXPECT_EQ(NXV24S32, getLCMType(NXV3S32, NXV4S64));
+ EXPECT_EQ(NXV12P0, getLCMType(NXV3P0, NXV4S64));
+ EXPECT_EQ(NXV12S64, getLCMType(NXV3S64, NXV4P0));
+
+ EXPECT_EQ(NXV12S1, getLCMType(NXV3S1, NXV4S1));
+ EXPECT_EQ(NXV12S32, getLCMType(NXV3S32, NXV4S32));
+ EXPECT_EQ(NXV12S64, getLCMType(NXV3S64, NXV4S64));
+ EXPECT_EQ(NXV12P0, getLCMType(NXV3P0, NXV4P0));
+
+ // Scalable, Scalar
+
+ EXPECT_EQ(NXV1S1, getLCMType(NXV1S1, S1));
+ EXPECT_EQ(NXV32S1, getLCMType(NXV1S1, S32));
+ EXPECT_EQ(NXV1S32, getLCMType(NXV1S32, S1));
+ EXPECT_EQ(NXV1S32, getLCMType(NXV1S32, S32));
+ EXPECT_EQ(NXV2S32, getLCMType(NXV1S32, S64));
+ EXPECT_EQ(NXV2S32, getLCMType(NXV2S32, S1));
+ EXPECT_EQ(NXV2S32, getLCMType(NXV2S32, S32));
+ EXPECT_EQ(NXV2S32, getLCMType(NXV2S32, S64));
+
+ EXPECT_EQ(NXV1S1, getLCMType(S1, NXV1S1));
+ EXPECT_EQ(NXV1S32, getLCMType(S32, NXV1S1));
+ EXPECT_EQ(NXV32S1, getLCMType(S1, NXV1S32));
+ EXPECT_EQ(NXV1S32, getLCMType(S32, NXV1S32));
+ EXPECT_EQ(NXV1S64, getLCMType(S64, NXV1S32));
+ EXPECT_EQ(NXV64S1, getLCMType(S1, NXV2S32));
+ EXPECT_EQ(NXV2S32, getLCMType(S32, NXV2S32));
+ EXPECT_EQ(NXV1S64, getLCMType(S64, NXV2S32));
}
TEST_F(AArch64GISelMITest, ConstFalseTest) {
>From cad17a868f2f25bab7f596bb59e43f6702691f7e Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Wed, 31 Jan 2024 11:51:26 -0800
Subject: [PATCH 2/5] [GISel] Add support for scalable vectors in getGCDType
This function can be called from buildCopyToRegs where at least one of the types
is a scalable vector type. This function crashed because it did not know
how to handle scalable vector types.
This patch extends the functionality of getGCDType to handle when at
least one of the types is a scalable vector. getGCDType between a fixed
and scalable vector is not implemented since the docstring of the
function explains that getGCDType is used to build MERGE/UNMERGE
instructions and we will never build a MERGE/UNMERGE between fixed and scalable
vectors.
---
llvm/include/llvm/CodeGen/GlobalISel/Utils.h | 5 +-
llvm/lib/CodeGen/GlobalISel/Utils.cpp | 73 +++++++++++--------
.../CodeGen/GlobalISel/GISelUtilsTest.cpp | 56 ++++++++++++++
3 files changed, 104 insertions(+), 30 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/Utils.h b/llvm/include/llvm/CodeGen/GlobalISel/Utils.h
index c96e4217d21f0..f8900f3434cca 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/Utils.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/Utils.h
@@ -368,7 +368,10 @@ LLT getCoverTy(LLT OrigTy, LLT TargetTy);
/// If these are vectors with different element types, this will try to produce
/// a vector with a compatible total size, but the element type of \p OrigTy. If
/// this can't be satisfied, this will produce a scalar smaller than the
-/// original vector elements.
+/// original vector elements. It is an error to call this function where
+/// one argument is a fixed vector and the other is a scalable vector, since it
+/// is illegal to build a G_{MERGE|UNMERGE}_VALUES between fixed and scalable
+/// vectors.
///
/// In the worst case, this returns LLT::scalar(1)
LLVM_READNONE
diff --git a/llvm/lib/CodeGen/GlobalISel/Utils.cpp b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
index c79cb6c77f2f0..73da8e61972eb 100644
--- a/llvm/lib/CodeGen/GlobalISel/Utils.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
@@ -1156,45 +1156,60 @@ LLT llvm::getCoverTy(LLT OrigTy, LLT TargetTy) {
}
LLT llvm::getGCDType(LLT OrigTy, LLT TargetTy) {
- const unsigned OrigSize = OrigTy.getSizeInBits();
- const unsigned TargetSize = TargetTy.getSizeInBits();
-
- if (OrigSize == TargetSize)
+ if (OrigTy.getSizeInBits() == TargetTy.getSizeInBits())
return OrigTy;
- if (OrigTy.isVector()) {
+ if (OrigTy.isVector() && TargetTy.isVector()) {
LLT OrigElt = OrigTy.getElementType();
- if (TargetTy.isVector()) {
- LLT TargetElt = TargetTy.getElementType();
- if (OrigElt.getSizeInBits() == TargetElt.getSizeInBits()) {
- int GCD = std::gcd(OrigTy.getNumElements(), TargetTy.getNumElements());
- return LLT::scalarOrVector(ElementCount::getFixed(GCD), OrigElt);
- }
- } else {
- // If the source is a vector of pointers, return a pointer element.
- if (OrigElt.getSizeInBits() == TargetSize)
- return OrigElt;
- }
+ LLT TargetElt = TargetTy.getElementType();
- unsigned GCD = std::gcd(OrigSize, TargetSize);
+ // TODO: The docstring for this function says the intention is to use this
+ // function to build MERGE/UNMERGE instructions. It won't be the case that
+ // we generate a MERGE/UNMERGE between fixed and scalable vector types. We
+ // could implement getGCDType between the two in the future if there was a
+ // need, but it is not worth it now as this function should not be used in
+ // that way.
+ if ((OrigTy.isScalableVector() && TargetTy.isFixedVector()) ||
+ (OrigTy.isFixedVector() && TargetTy.isScalableVector()))
+ llvm_unreachable(
+ "getGCDType not implemented between fixed and scalable vectors.");
+
+ unsigned GCD = std::gcd(OrigTy.getElementCount().getKnownMinValue() *
+ OrigElt.getSizeInBits().getFixedValue(),
+ TargetTy.getElementCount().getKnownMinValue() *
+ TargetElt.getSizeInBits().getFixedValue());
if (GCD == OrigElt.getSizeInBits())
- return OrigElt;
+ return LLT::scalarOrVector(ElementCount::get(1, OrigTy.isScalable()),
+ OrigElt);
- // If we can't produce the original element type, we have to use a smaller
- // scalar.
+ // Cannot produce original element type, but both have vscale in common.
if (GCD < OrigElt.getSizeInBits())
- return LLT::scalar(GCD);
- return LLT::fixed_vector(GCD / OrigElt.getSizeInBits(), OrigElt);
- }
+ return LLT::scalarOrVector(ElementCount::get(1, OrigTy.isScalable()),
+ GCD);
- if (TargetTy.isVector()) {
- // Try to preserve the original element type.
- LLT TargetElt = TargetTy.getElementType();
- if (TargetElt.getSizeInBits() == OrigSize)
- return OrigTy;
+ return LLT::vector(
+ ElementCount::get(GCD / OrigElt.getSizeInBits().getFixedValue(),
+ OrigTy.isScalable()),
+ OrigElt);
}
- unsigned GCD = std::gcd(OrigSize, TargetSize);
+ // If one type is vector and the element size matches the scalar size, then
+ // the gcd is the scalar type.
+ if (OrigTy.isVector() &&
+ OrigTy.getElementType().getSizeInBits() == TargetTy.getSizeInBits())
+ return OrigTy.getElementType();
+ if (TargetTy.isVector() &&
+ TargetTy.getElementType().getSizeInBits() == OrigTy.getSizeInBits())
+ return OrigTy;
+
+ // At this point, both types are either scalars of different type or one is a
+ // vector and one is a scalar. If both types are scalars, the GCD type is the
+ // GCD between the two scalar sizes. If one is vector and one is scalar, then
+ // the GCD type is the GCD between the scalar and the vector element size.
+ LLT OrigScalar = OrigTy.isVector() ? OrigTy.getElementType() : OrigTy;
+ LLT TargetScalar = TargetTy.isVector() ? TargetTy.getElementType() : TargetTy;
+ unsigned GCD = std::gcd(OrigScalar.getSizeInBits().getFixedValue(),
+ TargetScalar.getSizeInBits().getFixedValue());
return LLT::scalar(GCD);
}
diff --git a/llvm/unittests/CodeGen/GlobalISel/GISelUtilsTest.cpp b/llvm/unittests/CodeGen/GlobalISel/GISelUtilsTest.cpp
index 92bd0a36b82b4..1ff7fd956d015 100644
--- a/llvm/unittests/CodeGen/GlobalISel/GISelUtilsTest.cpp
+++ b/llvm/unittests/CodeGen/GlobalISel/GISelUtilsTest.cpp
@@ -183,6 +183,62 @@ TEST(GISelUtilsTest, getGCDType) {
EXPECT_EQ(LLT::scalar(4), getGCDType(LLT::fixed_vector(3, 4), S8));
EXPECT_EQ(LLT::scalar(4), getGCDType(S8, LLT::fixed_vector(3, 4)));
+
+ // Scalable -> Scalable
+ EXPECT_EQ(NXV1S1, getGCDType(NXV1S1, NXV1S32));
+ EXPECT_EQ(NXV1S32, getGCDType(NXV1S64, NXV1S32));
+ EXPECT_EQ(NXV1S32, getGCDType(NXV1S32, NXV1S64));
+ EXPECT_EQ(NXV1P0, getGCDType(NXV1P0, NXV1S64));
+ EXPECT_EQ(NXV1S64, getGCDType(NXV1S64, NXV1P0));
+
+ EXPECT_EQ(NXV4S1, getGCDType(NXV4S1, NXV4S32));
+ EXPECT_EQ(NXV2S64, getGCDType(NXV4S64, NXV4S32));
+ EXPECT_EQ(NXV4S32, getGCDType(NXV4S32, NXV4S64));
+ EXPECT_EQ(NXV4P0, getGCDType(NXV4P0, NXV4S64));
+ EXPECT_EQ(NXV4S64, getGCDType(NXV4S64, NXV4P0));
+
+ EXPECT_EQ(NXV4S1, getGCDType(NXV4S1, NXV2S32));
+ EXPECT_EQ(NXV1S64, getGCDType(NXV4S64, NXV2S32));
+ EXPECT_EQ(NXV4S32, getGCDType(NXV4S32, NXV2S64));
+ EXPECT_EQ(NXV2P0, getGCDType(NXV4P0, NXV2S64));
+ EXPECT_EQ(NXV2S64, getGCDType(NXV4S64, NXV2P0));
+
+ EXPECT_EQ(NXV2S1, getGCDType(NXV2S1, NXV4S32));
+ EXPECT_EQ(NXV2S64, getGCDType(NXV2S64, NXV4S32));
+ EXPECT_EQ(NXV2S32, getGCDType(NXV2S32, NXV4S64));
+ EXPECT_EQ(NXV2P0, getGCDType(NXV2P0, NXV4S64));
+ EXPECT_EQ(NXV2S64, getGCDType(NXV2S64, NXV4P0));
+
+ EXPECT_EQ(NXV1S1, getGCDType(NXV3S1, NXV4S32));
+ EXPECT_EQ(NXV1S64, getGCDType(NXV3S64, NXV4S32));
+ EXPECT_EQ(NXV1S32, getGCDType(NXV3S32, NXV4S64));
+ EXPECT_EQ(NXV1P0, getGCDType(NXV3P0, NXV4S64));
+ EXPECT_EQ(NXV1S64, getGCDType(NXV3S64, NXV4P0));
+
+ EXPECT_EQ(NXV1S1, getGCDType(NXV3S1, NXV4S1));
+ EXPECT_EQ(NXV1S32, getGCDType(NXV3S32, NXV4S32));
+ EXPECT_EQ(NXV1S64, getGCDType(NXV3S64, NXV4S64));
+ EXPECT_EQ(NXV1P0, getGCDType(NXV3P0, NXV4P0));
+
+ // Scalable, Scalar
+
+ EXPECT_EQ(S1, getGCDType(NXV1S1, S1));
+ EXPECT_EQ(S1, getGCDType(NXV1S1, S32));
+ EXPECT_EQ(S1, getGCDType(NXV1S32, S1));
+ EXPECT_EQ(S32, getGCDType(NXV1S32, S32));
+ EXPECT_EQ(S32, getGCDType(NXV1S32, S64));
+ EXPECT_EQ(S1, getGCDType(NXV2S32, S1));
+ EXPECT_EQ(S32, getGCDType(NXV2S32, S32));
+ EXPECT_EQ(S32, getGCDType(NXV2S32, S64));
+
+ EXPECT_EQ(S1, getGCDType(S1, NXV1S1));
+ EXPECT_EQ(S1, getGCDType(S32, NXV1S1));
+ EXPECT_EQ(S1, getGCDType(S1, NXV1S32));
+ EXPECT_EQ(S32, getGCDType(S32, NXV1S32));
+ EXPECT_EQ(S32, getGCDType(S64, NXV1S32));
+ EXPECT_EQ(S1, getGCDType(S1, NXV2S32));
+ EXPECT_EQ(S32, getGCDType(S32, NXV2S32));
+ EXPECT_EQ(S32, getGCDType(S64, NXV2S32));
}
TEST(GISelUtilsTest, getLCMType) {
>From a4c52148049a0fe98aed129784d6c7df0fe9d429 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Thu, 1 Feb 2024 17:38:16 -0800
Subject: [PATCH 3/5] [GISEL] More accounting for scalable vectors when
operating on LLTs
---
llvm/lib/CodeGen/GlobalISel/CallLowering.cpp | 13 +++++++------
llvm/lib/CodeGen/GlobalISel/Utils.cpp | 10 ++++++++--
llvm/lib/CodeGen/MachineVerifier.cpp | 7 ++++---
3 files changed, 19 insertions(+), 11 deletions(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
index ccd9b13d730b6..3bd1542eeb746 100644
--- a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
@@ -412,7 +412,7 @@ static void buildCopyFromRegs(MachineIRBuilder &B, ArrayRef<Register> OrigRegs,
// size, e.g. PartLLT == v2s64 and LLTy is v3s32, then first coerce it to
// have the same elt type, i.e. v4s32.
// TODO: Extend this coersion to element multiples other than just 2.
- if (PartLLT.getSizeInBits() > LLTy.getSizeInBits() &&
+ if (TypeSize::isKnownGT(PartLLT.getSizeInBits(), LLTy.getSizeInBits()) &&
PartLLT.getScalarSizeInBits() == LLTy.getScalarSizeInBits() * 2 &&
Regs.size() == 1) {
LLT NewTy = PartLLT.changeElementType(LLTy.getElementType())
@@ -529,7 +529,7 @@ static void buildCopyToRegs(MachineIRBuilder &B, ArrayRef<Register> DstRegs,
// We could just insert a regular copy, but this is unreachable at the moment.
assert(SrcTy != PartTy && "identical part types shouldn't reach here");
- const unsigned PartSize = PartTy.getSizeInBits();
+ const TypeSize PartSize = PartTy.getSizeInBits();
if (PartTy.isVector() == SrcTy.isVector() &&
PartTy.getScalarSizeInBits() > SrcTy.getScalarSizeInBits()) {
@@ -539,7 +539,7 @@ static void buildCopyToRegs(MachineIRBuilder &B, ArrayRef<Register> DstRegs,
}
if (SrcTy.isVector() && !PartTy.isVector() &&
- PartSize > SrcTy.getElementType().getSizeInBits()) {
+ TypeSize::isKnownGT(PartSize, SrcTy.getElementType().getSizeInBits())) {
// Vector was scalarized, and the elements extended.
auto UnmergeToEltTy = B.buildUnmerge(SrcTy.getElementType(), SrcReg);
for (int i = 0, e = DstRegs.size(); i != e; ++i)
@@ -548,9 +548,10 @@ static void buildCopyToRegs(MachineIRBuilder &B, ArrayRef<Register> DstRegs,
}
if (SrcTy.isVector() && PartTy.isVector() &&
- PartTy.getScalarSizeInBits() == SrcTy.getScalarSizeInBits() &&
- SrcTy.getNumElements() < PartTy.getNumElements()) {
- // A coercion like: v2f32 -> v4f32.
+ PartTy.getSizeInBits() == SrcTy.getSizeInBits() &&
+ ElementCount::isKnownLT(SrcTy.getElementCount(),
+ PartTy.getElementCount())) {
+ // A coercion like: v2f32 -> v4f32 or nxv2f32 -> nxv4f32
Register DstReg = DstRegs.front();
B.buildPadVectorWithUndefElements(DstReg, SrcReg);
return;
diff --git a/llvm/lib/CodeGen/GlobalISel/Utils.cpp b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
index 73da8e61972eb..b1f22d5ddaee8 100644
--- a/llvm/lib/CodeGen/GlobalISel/Utils.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
@@ -1141,12 +1141,18 @@ LLT llvm::getLCMType(LLT OrigTy, LLT TargetTy) {
}
LLT llvm::getCoverTy(LLT OrigTy, LLT TargetTy) {
+
+ if ((OrigTy.isScalableVector() && TargetTy.isFixedVector()) ||
+ (OrigTy.isFixedVector() && TargetTy.isScalableVector()))
+ llvm_unreachable(
+ "getCoverTy not implemented between fixed and scalable vectors.");
+
if (!OrigTy.isVector() || !TargetTy.isVector() || OrigTy == TargetTy ||
(OrigTy.getScalarSizeInBits() != TargetTy.getScalarSizeInBits()))
return getLCMType(OrigTy, TargetTy);
- unsigned OrigTyNumElts = OrigTy.getNumElements();
- unsigned TargetTyNumElts = TargetTy.getNumElements();
+ unsigned OrigTyNumElts = OrigTy.getElementCount().getKnownMinValue();
+ unsigned TargetTyNumElts = TargetTy.getElementCount().getKnownMinValue();
if (OrigTyNumElts % TargetTyNumElts == 0)
return OrigTy;
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index b182000a3d705..fe865ed6f8a0e 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -1400,7 +1400,8 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
if (DstTy.isVector()) {
// This case is the converse of G_CONCAT_VECTORS.
if (!SrcTy.isVector() || SrcTy.getScalarType() != DstTy.getScalarType() ||
- SrcTy.getNumElements() != NumDsts * DstTy.getNumElements())
+ SrcTy.isScalableVector() != DstTy.isScalableVector() ||
+ SrcTy.getSizeInBits() != NumDsts * DstTy.getSizeInBits())
report("G_UNMERGE_VALUES source operand does not match vector "
"destination operands",
MI);
@@ -1477,8 +1478,8 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
for (const MachineOperand &MO : llvm::drop_begin(MI->operands(), 2))
if (MRI->getType(MI->getOperand(1).getReg()) != MRI->getType(MO.getReg()))
report("G_CONCAT_VECTOR source operand types are not homogeneous", MI);
- if (DstTy.getNumElements() !=
- SrcTy.getNumElements() * (MI->getNumOperands() - 1))
+ if (DstTy.getElementCount() !=
+ SrcTy.getElementCount() * (MI->getNumOperands() - 1))
report("G_CONCAT_VECTOR num dest and source elements should match", MI);
break;
}
>From a670300bfe6a871bf09f91b9ecee937c67cbc577 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Tue, 30 Jan 2024 07:21:27 -0800
Subject: [PATCH 4/5] [RISCV][GISEL] Add IRTranslation for shufflevector on
scalable vector types
---
llvm/lib/CodeGen/MachineVerifier.cpp | 32 +-
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 6 +-
.../GlobalISel/irtranslator/shufflevector.ll | 1524 +++++++++++++++++
3 files changed, 1550 insertions(+), 12 deletions(-)
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/shufflevector.ll
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index fe865ed6f8a0e..ef1cefc4872ac 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -1618,20 +1618,34 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
// Don't check that all operands are vector because scalars are used in
// place of 1 element vectors.
- int SrcNumElts = Src0Ty.isVector() ? Src0Ty.getNumElements() : 1;
- int DstNumElts = DstTy.isVector() ? DstTy.getNumElements() : 1;
+ ElementCount SrcNumElts = Src0Ty.isVector() ? Src0Ty.getElementCount()
+ : ElementCount::getFixed(1);
+ ElementCount DstNumElts =
+ DstTy.isVector() ? DstTy.getElementCount() : ElementCount::getFixed(1);
ArrayRef<int> MaskIdxes = MaskOp.getShuffleMask();
- if (static_cast<int>(MaskIdxes.size()) != DstNumElts)
+ // For scalable vectors, there is an entry in the Mask for each
+ // KnownMinValue.
+ if (MaskIdxes.size() != DstNumElts.getKnownMinValue())
report("Wrong result type for shufflemask", MI);
- for (int Idx : MaskIdxes) {
- if (Idx < 0)
- continue;
-
- if (Idx >= 2 * SrcNumElts)
- report("Out of bounds shuffle index", MI);
+ if (Src0Ty.isScalableVector()) {
+ if (!llvm::all_of(MaskIdxes,
+ [&MaskIdxes](int M) { return M == MaskIdxes[0]; }))
+ report("Elements of a scalable G_SHUFFLE_VECTOR mask must match", MI);
+ if (MaskIdxes[0] != 0 && MaskIdxes[0] != -1)
+ report("Elements of a scalable G_SHUFFLE_VECTOR mask be zero or undef",
+ MI);
+ } else {
+ // Idxes for fixed vectors must be in bounds or undef, which is
+ // represented as -1.
+ for (int Idx : MaskIdxes) {
+ if (Idx < 0)
+ continue;
+ if ((unsigned)Idx >= 2 * SrcNumElts.getFixedValue())
+ report("Out of bounds shuffle index", MI);
+ }
}
break;
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index b5db41197a35a..a7807ead7a2d9 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -20485,11 +20485,11 @@ unsigned RISCVTargetLowering::getCustomCtpopCost(EVT VT,
bool RISCVTargetLowering::fallBackToDAGISel(const Instruction &Inst) const {
- // GISel support is in progress or complete for G_ADD, G_SUB, G_AND, G_OR, and
- // G_XOR.
+ // GISel support is in progress or complete for these opcodes.
unsigned Op = Inst.getOpcode();
if (Op == Instruction::Add || Op == Instruction::Sub ||
- Op == Instruction::And || Op == Instruction::Or || Op == Instruction::Xor)
+ Op == Instruction::And || Op == Instruction::Or ||
+ Op == Instruction::Xor || Op == Instruction::ShuffleVector)
return false;
if (Inst.getType()->isScalableTy())
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/shufflevector.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/shufflevector.ll
new file mode 100644
index 0000000000000..741f791ff3d05
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/shufflevector.ll
@@ -0,0 +1,1524 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
+; RUN: llc -mtriple=riscv32 -mattr=+v -global-isel -stop-after=irtranslator \
+; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=RV32 %s
+; RUN: llc -mtriple=riscv64 -mattr=+v -global-isel -stop-after=irtranslator \
+; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=RV64 %s
+
+define <vscale x 1 x i1> @shufflevector_nxv1i1_0() {
+ ; RV32-LABEL: name: shufflevector_nxv1i1_0
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 1 x s1>), [[DEF]], shufflemask(undef)
+ ; RV32-NEXT: $v0 = COPY [[SHUF]](<vscale x 1 x s1>)
+ ; RV32-NEXT: PseudoRET implicit $v0
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv1i1_0
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 1 x s1>), [[DEF]], shufflemask(undef)
+ ; RV64-NEXT: $v0 = COPY [[SHUF]](<vscale x 1 x s1>)
+ ; RV64-NEXT: PseudoRET implicit $v0
+ %a = shufflevector <vscale x 1 x i1> poison, <vscale x 1 x i1> poison, <vscale x 1 x i32> poison
+ ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 1 x i1> @shufflevector_nxv1i1_1() {
+ ; RV32-LABEL: name: shufflevector_nxv1i1_1
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 1 x s1>), [[DEF]], shufflemask(undef)
+ ; RV32-NEXT: $v0 = COPY [[SHUF]](<vscale x 1 x s1>)
+ ; RV32-NEXT: PseudoRET implicit $v0
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv1i1_1
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 1 x s1>), [[DEF]], shufflemask(undef)
+ ; RV64-NEXT: $v0 = COPY [[SHUF]](<vscale x 1 x s1>)
+ ; RV64-NEXT: PseudoRET implicit $v0
+ %a = shufflevector <vscale x 1 x i1> undef, <vscale x 1 x i1> undef, <vscale x 1 x i32> undef
+ ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 1 x i1> @shufflevector_nxv1i1_2(<vscale x 1 x i1> %a) {
+ ; RV32-LABEL: name: shufflevector_nxv1i1_2
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $v0
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 1 x s1>), [[DEF]], shufflemask(0)
+ ; RV32-NEXT: $v0 = COPY [[SHUF]](<vscale x 1 x s1>)
+ ; RV32-NEXT: PseudoRET implicit $v0
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv1i1_2
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $v0
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 1 x s1>), [[DEF]], shufflemask(0)
+ ; RV64-NEXT: $v0 = COPY [[SHUF]](<vscale x 1 x s1>)
+ ; RV64-NEXT: PseudoRET implicit $v0
+ %b = shufflevector <vscale x 1 x i1> %a , <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer
+ ret <vscale x 1 x i1> %b
+}
+
+define <vscale x 2 x i1> @shufflevector_nxv2i1_0() {
+ ; RV32-LABEL: name: shufflevector_nxv2i1_0
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 2 x s1>), [[DEF]], shufflemask(undef, undef)
+ ; RV32-NEXT: $v0 = COPY [[SHUF]](<vscale x 2 x s1>)
+ ; RV32-NEXT: PseudoRET implicit $v0
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv2i1_0
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 2 x s1>), [[DEF]], shufflemask(undef, undef)
+ ; RV64-NEXT: $v0 = COPY [[SHUF]](<vscale x 2 x s1>)
+ ; RV64-NEXT: PseudoRET implicit $v0
+ %a = shufflevector <vscale x 2 x i1> poison, <vscale x 2 x i1> poison, <vscale x 2 x i32> poison
+ ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 2 x i1> @shufflevector_nxv2i1_1() {
+ ; RV32-LABEL: name: shufflevector_nxv2i1_1
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 2 x s1>), [[DEF]], shufflemask(undef, undef)
+ ; RV32-NEXT: $v0 = COPY [[SHUF]](<vscale x 2 x s1>)
+ ; RV32-NEXT: PseudoRET implicit $v0
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv2i1_1
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 2 x s1>), [[DEF]], shufflemask(undef, undef)
+ ; RV64-NEXT: $v0 = COPY [[SHUF]](<vscale x 2 x s1>)
+ ; RV64-NEXT: PseudoRET implicit $v0
+ %a = shufflevector <vscale x 2 x i1> undef, <vscale x 2 x i1> undef, <vscale x 2 x i32> undef
+ ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 2 x i1> @shufflevector_nxv2i1_2(<vscale x 2 x i1> %a) {
+ ; RV32-LABEL: name: shufflevector_nxv2i1_2
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $v0
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v0
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 2 x s1>), [[DEF]], shufflemask(0, 0)
+ ; RV32-NEXT: $v0 = COPY [[SHUF]](<vscale x 2 x s1>)
+ ; RV32-NEXT: PseudoRET implicit $v0
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv2i1_2
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $v0
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v0
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 2 x s1>), [[DEF]], shufflemask(0, 0)
+ ; RV64-NEXT: $v0 = COPY [[SHUF]](<vscale x 2 x s1>)
+ ; RV64-NEXT: PseudoRET implicit $v0
+ %b = shufflevector <vscale x 2 x i1> %a , <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer
+ ret <vscale x 2 x i1> %b
+}
+
+define <vscale x 4 x i1> @shufflevector_nxv4i1_0() {
+ ; RV32-LABEL: name: shufflevector_nxv4i1_0
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 4 x s1>), [[DEF]], shufflemask(undef, undef, undef, undef)
+ ; RV32-NEXT: $v0 = COPY [[SHUF]](<vscale x 4 x s1>)
+ ; RV32-NEXT: PseudoRET implicit $v0
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv4i1_0
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 4 x s1>), [[DEF]], shufflemask(undef, undef, undef, undef)
+ ; RV64-NEXT: $v0 = COPY [[SHUF]](<vscale x 4 x s1>)
+ ; RV64-NEXT: PseudoRET implicit $v0
+ %a = shufflevector <vscale x 4 x i1> poison, <vscale x 4 x i1> poison, <vscale x 4 x i32> poison
+ ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 4 x i1> @shufflevector_nxv4i1_1() {
+ ; RV32-LABEL: name: shufflevector_nxv4i1_1
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 4 x s1>), [[DEF]], shufflemask(undef, undef, undef, undef)
+ ; RV32-NEXT: $v0 = COPY [[SHUF]](<vscale x 4 x s1>)
+ ; RV32-NEXT: PseudoRET implicit $v0
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv4i1_1
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 4 x s1>), [[DEF]], shufflemask(undef, undef, undef, undef)
+ ; RV64-NEXT: $v0 = COPY [[SHUF]](<vscale x 4 x s1>)
+ ; RV64-NEXT: PseudoRET implicit $v0
+ %a = shufflevector <vscale x 4 x i1> undef, <vscale x 4 x i1> undef, <vscale x 4 x i32> undef
+ ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 4 x i1> @shufflevector_nxv4i1_2(<vscale x 4 x i1> %a) {
+ ; RV32-LABEL: name: shufflevector_nxv4i1_2
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $v0
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v0
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 4 x s1>), [[DEF]], shufflemask(0, 0, 0, 0)
+ ; RV32-NEXT: $v0 = COPY [[SHUF]](<vscale x 4 x s1>)
+ ; RV32-NEXT: PseudoRET implicit $v0
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv4i1_2
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $v0
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v0
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 4 x s1>), [[DEF]], shufflemask(0, 0, 0, 0)
+ ; RV64-NEXT: $v0 = COPY [[SHUF]](<vscale x 4 x s1>)
+ ; RV64-NEXT: PseudoRET implicit $v0
+ %b = shufflevector <vscale x 4 x i1> %a , <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer
+ ret <vscale x 4 x i1> %b
+}
+
+define <vscale x 8 x i1> @shufflevector_nxv8i1_0() {
+ ; RV32-LABEL: name: shufflevector_nxv8i1_0
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 8 x s1>), [[DEF]], shufflemask(undef, undef, undef, undef, undef, undef, undef, undef)
+ ; RV32-NEXT: $v0 = COPY [[SHUF]](<vscale x 8 x s1>)
+ ; RV32-NEXT: PseudoRET implicit $v0
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv8i1_0
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 8 x s1>), [[DEF]], shufflemask(undef, undef, undef, undef, undef, undef, undef, undef)
+ ; RV64-NEXT: $v0 = COPY [[SHUF]](<vscale x 8 x s1>)
+ ; RV64-NEXT: PseudoRET implicit $v0
+ %a = shufflevector <vscale x 8 x i1> poison, <vscale x 8 x i1> poison, <vscale x 8 x i32> poison
+ ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 8 x i1> @shufflevector_nxv8i1_1() {
+ ; RV32-LABEL: name: shufflevector_nxv8i1_1
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 8 x s1>), [[DEF]], shufflemask(undef, undef, undef, undef, undef, undef, undef, undef)
+ ; RV32-NEXT: $v0 = COPY [[SHUF]](<vscale x 8 x s1>)
+ ; RV32-NEXT: PseudoRET implicit $v0
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv8i1_1
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 8 x s1>), [[DEF]], shufflemask(undef, undef, undef, undef, undef, undef, undef, undef)
+ ; RV64-NEXT: $v0 = COPY [[SHUF]](<vscale x 8 x s1>)
+ ; RV64-NEXT: PseudoRET implicit $v0
+ %a = shufflevector <vscale x 8 x i1> undef, <vscale x 8 x i1> undef, <vscale x 8 x i32> undef
+ ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 8 x i1> @shufflevector_nxv8i1_2(<vscale x 8 x i1> %a) {
+ ; RV32-LABEL: name: shufflevector_nxv8i1_2
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $v0
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s1>) = COPY $v0
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 8 x s1>), [[DEF]], shufflemask(0, 0, 0, 0, 0, 0, 0, 0)
+ ; RV32-NEXT: $v0 = COPY [[SHUF]](<vscale x 8 x s1>)
+ ; RV32-NEXT: PseudoRET implicit $v0
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv8i1_2
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $v0
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s1>) = COPY $v0
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 8 x s1>), [[DEF]], shufflemask(0, 0, 0, 0, 0, 0, 0, 0)
+ ; RV64-NEXT: $v0 = COPY [[SHUF]](<vscale x 8 x s1>)
+ ; RV64-NEXT: PseudoRET implicit $v0
+ %b = shufflevector <vscale x 8 x i1> %a , <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
+ ret <vscale x 8 x i1> %b
+}
+
+define <vscale x 16 x i1> @shufflevector_nxv16i1_0() {
+ ; RV32-LABEL: name: shufflevector_nxv16i1_0
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 16 x s1>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 16 x s1>), [[DEF]], shufflemask(undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef)
+ ; RV32-NEXT: $v0 = COPY [[SHUF]](<vscale x 16 x s1>)
+ ; RV32-NEXT: PseudoRET implicit $v0
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv16i1_0
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 16 x s1>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 16 x s1>), [[DEF]], shufflemask(undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef)
+ ; RV64-NEXT: $v0 = COPY [[SHUF]](<vscale x 16 x s1>)
+ ; RV64-NEXT: PseudoRET implicit $v0
+ %a = shufflevector <vscale x 16 x i1> poison, <vscale x 16 x i1> poison, <vscale x 16 x i32> poison
+ ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 16 x i1> @shufflevector_nxv16i1_1() {
+ ; RV32-LABEL: name: shufflevector_nxv16i1_1
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 16 x s1>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 16 x s1>), [[DEF]], shufflemask(undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef)
+ ; RV32-NEXT: $v0 = COPY [[SHUF]](<vscale x 16 x s1>)
+ ; RV32-NEXT: PseudoRET implicit $v0
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv16i1_1
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 16 x s1>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 16 x s1>), [[DEF]], shufflemask(undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef)
+ ; RV64-NEXT: $v0 = COPY [[SHUF]](<vscale x 16 x s1>)
+ ; RV64-NEXT: PseudoRET implicit $v0
+ %a = shufflevector <vscale x 16 x i1> undef, <vscale x 16 x i1> undef, <vscale x 16 x i32> undef
+ ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 16 x i1> @shufflevector_nxv16i1_2(<vscale x 16 x i1> %a) {
+ ; RV32-LABEL: name: shufflevector_nxv16i1_2
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $v0
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s1>) = COPY $v0
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 16 x s1>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 16 x s1>), [[DEF]], shufflemask(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
+ ; RV32-NEXT: $v0 = COPY [[SHUF]](<vscale x 16 x s1>)
+ ; RV32-NEXT: PseudoRET implicit $v0
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv16i1_2
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $v0
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s1>) = COPY $v0
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 16 x s1>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 16 x s1>), [[DEF]], shufflemask(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
+ ; RV64-NEXT: $v0 = COPY [[SHUF]](<vscale x 16 x s1>)
+ ; RV64-NEXT: PseudoRET implicit $v0
+ %b = shufflevector <vscale x 16 x i1> %a , <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer
+ ret <vscale x 16 x i1> %b
+}
+
+define <vscale x 1 x i8> @shufflevector_nxv1i8_0() {
+ ; RV32-LABEL: name: shufflevector_nxv1i8_0
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 1 x s8>), [[DEF]], shufflemask(undef)
+ ; RV32-NEXT: $v8 = COPY [[SHUF]](<vscale x 1 x s8>)
+ ; RV32-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv1i8_0
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 1 x s8>), [[DEF]], shufflemask(undef)
+ ; RV64-NEXT: $v8 = COPY [[SHUF]](<vscale x 1 x s8>)
+ ; RV64-NEXT: PseudoRET implicit $v8
+ %a = shufflevector <vscale x 1 x i8> poison, <vscale x 1 x i8> poison, <vscale x 1 x i32> poison
+ ret <vscale x 1 x i8> %a
+}
+
+define <vscale x 1 x i8> @shufflevector_nxv1i8_1() {
+ ; RV32-LABEL: name: shufflevector_nxv1i8_1
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 1 x s8>), [[DEF]], shufflemask(undef)
+ ; RV32-NEXT: $v8 = COPY [[SHUF]](<vscale x 1 x s8>)
+ ; RV32-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv1i8_1
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 1 x s8>), [[DEF]], shufflemask(undef)
+ ; RV64-NEXT: $v8 = COPY [[SHUF]](<vscale x 1 x s8>)
+ ; RV64-NEXT: PseudoRET implicit $v8
+ %a = shufflevector <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i32> undef
+ ret <vscale x 1 x i8> %a
+}
+
+define <vscale x 1 x i8> @shufflevector_nxv1i8_2(<vscale x 1 x i8> %a) {
+ ; RV32-LABEL: name: shufflevector_nxv1i8_2
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s8>) = COPY $v8
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 1 x s8>), [[DEF]], shufflemask(0)
+ ; RV32-NEXT: $v8 = COPY [[SHUF]](<vscale x 1 x s8>)
+ ; RV32-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv1i8_2
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s8>) = COPY $v8
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 1 x s8>), [[DEF]], shufflemask(0)
+ ; RV64-NEXT: $v8 = COPY [[SHUF]](<vscale x 1 x s8>)
+ ; RV64-NEXT: PseudoRET implicit $v8
+ %b = shufflevector <vscale x 1 x i8> %a , <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
+ ret <vscale x 1 x i8> %b
+}
+
+define <vscale x 2 x i8> @shufflevector_nxv2i8_0() {
+ ; RV32-LABEL: name: shufflevector_nxv2i8_0
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 2 x s8>), [[DEF]], shufflemask(undef, undef)
+ ; RV32-NEXT: $v8 = COPY [[SHUF]](<vscale x 2 x s8>)
+ ; RV32-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv2i8_0
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 2 x s8>), [[DEF]], shufflemask(undef, undef)
+ ; RV64-NEXT: $v8 = COPY [[SHUF]](<vscale x 2 x s8>)
+ ; RV64-NEXT: PseudoRET implicit $v8
+ %a = shufflevector <vscale x 2 x i8> poison, <vscale x 2 x i8> poison, <vscale x 2 x i32> poison
+ ret <vscale x 2 x i8> %a
+}
+
+define <vscale x 2 x i8> @shufflevector_nxv2i8_1() {
+ ; RV32-LABEL: name: shufflevector_nxv2i8_1
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 2 x s8>), [[DEF]], shufflemask(undef, undef)
+ ; RV32-NEXT: $v8 = COPY [[SHUF]](<vscale x 2 x s8>)
+ ; RV32-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv2i8_1
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 2 x s8>), [[DEF]], shufflemask(undef, undef)
+ ; RV64-NEXT: $v8 = COPY [[SHUF]](<vscale x 2 x s8>)
+ ; RV64-NEXT: PseudoRET implicit $v8
+ %a = shufflevector <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i32> undef
+ ret <vscale x 2 x i8> %a
+}
+
+define <vscale x 2 x i8> @shufflevector_nxv2i8_2(<vscale x 2 x i8> %a) {
+ ; RV32-LABEL: name: shufflevector_nxv2i8_2
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s8>) = COPY $v8
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 2 x s8>), [[DEF]], shufflemask(0, 0)
+ ; RV32-NEXT: $v8 = COPY [[SHUF]](<vscale x 2 x s8>)
+ ; RV32-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv2i8_2
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s8>) = COPY $v8
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 2 x s8>), [[DEF]], shufflemask(0, 0)
+ ; RV64-NEXT: $v8 = COPY [[SHUF]](<vscale x 2 x s8>)
+ ; RV64-NEXT: PseudoRET implicit $v8
+ %b = shufflevector <vscale x 2 x i8> %a , <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
+ ret <vscale x 2 x i8> %b
+}
+
+define <vscale x 4 x i8> @shufflevector_nxv4i8_0() {
+ ; RV32-LABEL: name: shufflevector_nxv4i8_0
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 4 x s8>), [[DEF]], shufflemask(undef, undef, undef, undef)
+ ; RV32-NEXT: $v8 = COPY [[SHUF]](<vscale x 4 x s8>)
+ ; RV32-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv4i8_0
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 4 x s8>), [[DEF]], shufflemask(undef, undef, undef, undef)
+ ; RV64-NEXT: $v8 = COPY [[SHUF]](<vscale x 4 x s8>)
+ ; RV64-NEXT: PseudoRET implicit $v8
+ %a = shufflevector <vscale x 4 x i8> poison, <vscale x 4 x i8> poison, <vscale x 4 x i32> poison
+ ret <vscale x 4 x i8> %a
+}
+
+define <vscale x 4 x i8> @shufflevector_nxv4i8_1() {
+ ; RV32-LABEL: name: shufflevector_nxv4i8_1
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 4 x s8>), [[DEF]], shufflemask(undef, undef, undef, undef)
+ ; RV32-NEXT: $v8 = COPY [[SHUF]](<vscale x 4 x s8>)
+ ; RV32-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv4i8_1
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 4 x s8>), [[DEF]], shufflemask(undef, undef, undef, undef)
+ ; RV64-NEXT: $v8 = COPY [[SHUF]](<vscale x 4 x s8>)
+ ; RV64-NEXT: PseudoRET implicit $v8
+ %a = shufflevector <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i32> undef
+ ret <vscale x 4 x i8> %a
+}
+
+define <vscale x 4 x i8> @shufflevector_nxv4i8_2(<vscale x 4 x i8> %a) {
+ ; RV32-LABEL: name: shufflevector_nxv4i8_2
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s8>) = COPY $v8
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 4 x s8>), [[DEF]], shufflemask(0, 0, 0, 0)
+ ; RV32-NEXT: $v8 = COPY [[SHUF]](<vscale x 4 x s8>)
+ ; RV32-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv4i8_2
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s8>) = COPY $v8
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 4 x s8>), [[DEF]], shufflemask(0, 0, 0, 0)
+ ; RV64-NEXT: $v8 = COPY [[SHUF]](<vscale x 4 x s8>)
+ ; RV64-NEXT: PseudoRET implicit $v8
+ %b = shufflevector <vscale x 4 x i8> %a , <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
+ ret <vscale x 4 x i8> %b
+}
+
+define <vscale x 8 x i8> @shufflevector_nxv8i8_0() {
+ ; RV32-LABEL: name: shufflevector_nxv8i8_0
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 8 x s8>), [[DEF]], shufflemask(undef, undef, undef, undef, undef, undef, undef, undef)
+ ; RV32-NEXT: $v8 = COPY [[SHUF]](<vscale x 8 x s8>)
+ ; RV32-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv8i8_0
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 8 x s8>), [[DEF]], shufflemask(undef, undef, undef, undef, undef, undef, undef, undef)
+ ; RV64-NEXT: $v8 = COPY [[SHUF]](<vscale x 8 x s8>)
+ ; RV64-NEXT: PseudoRET implicit $v8
+ %a = shufflevector <vscale x 8 x i8> poison, <vscale x 8 x i8> poison, <vscale x 8 x i32> poison
+ ret <vscale x 8 x i8> %a
+}
+
+define <vscale x 8 x i8> @shufflevector_nxv8i8_1() {
+ ; RV32-LABEL: name: shufflevector_nxv8i8_1
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 8 x s8>), [[DEF]], shufflemask(undef, undef, undef, undef, undef, undef, undef, undef)
+ ; RV32-NEXT: $v8 = COPY [[SHUF]](<vscale x 8 x s8>)
+ ; RV32-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv8i8_1
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 8 x s8>), [[DEF]], shufflemask(undef, undef, undef, undef, undef, undef, undef, undef)
+ ; RV64-NEXT: $v8 = COPY [[SHUF]](<vscale x 8 x s8>)
+ ; RV64-NEXT: PseudoRET implicit $v8
+ %a = shufflevector <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i32> undef
+ ret <vscale x 8 x i8> %a
+}
+
+define <vscale x 8 x i8> @shufflevector_nxv8i8_2(<vscale x 8 x i8> %a) {
+ ; RV32-LABEL: name: shufflevector_nxv8i8_2
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s8>) = COPY $v8
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 8 x s8>), [[DEF]], shufflemask(0, 0, 0, 0, 0, 0, 0, 0)
+ ; RV32-NEXT: $v8 = COPY [[SHUF]](<vscale x 8 x s8>)
+ ; RV32-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv8i8_2
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s8>) = COPY $v8
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 8 x s8>), [[DEF]], shufflemask(0, 0, 0, 0, 0, 0, 0, 0)
+ ; RV64-NEXT: $v8 = COPY [[SHUF]](<vscale x 8 x s8>)
+ ; RV64-NEXT: PseudoRET implicit $v8
+ %b = shufflevector <vscale x 8 x i8> %a , <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
+ ret <vscale x 8 x i8> %b
+}
+
+define <vscale x 16 x i8> @shufflevector_nxv16i8_0() {
+ ; RV32-LABEL: name: shufflevector_nxv16i8_0
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 16 x s8>), [[DEF]], shufflemask(undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef)
+ ; RV32-NEXT: $v8m2 = COPY [[SHUF]](<vscale x 16 x s8>)
+ ; RV32-NEXT: PseudoRET implicit $v8m2
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv16i8_0
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 16 x s8>), [[DEF]], shufflemask(undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef)
+ ; RV64-NEXT: $v8m2 = COPY [[SHUF]](<vscale x 16 x s8>)
+ ; RV64-NEXT: PseudoRET implicit $v8m2
+ %a = shufflevector <vscale x 16 x i8> poison, <vscale x 16 x i8> poison, <vscale x 16 x i32> poison
+ ret <vscale x 16 x i8> %a
+}
+
+define <vscale x 16 x i8> @shufflevector_nxv16i8_1() {
+ ; RV32-LABEL: name: shufflevector_nxv16i8_1
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 16 x s8>), [[DEF]], shufflemask(undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef)
+ ; RV32-NEXT: $v8m2 = COPY [[SHUF]](<vscale x 16 x s8>)
+ ; RV32-NEXT: PseudoRET implicit $v8m2
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv16i8_1
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 16 x s8>), [[DEF]], shufflemask(undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef)
+ ; RV64-NEXT: $v8m2 = COPY [[SHUF]](<vscale x 16 x s8>)
+ ; RV64-NEXT: PseudoRET implicit $v8m2
+ %a = shufflevector <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i32> undef
+ ret <vscale x 16 x i8> %a
+}
+
+define <vscale x 16 x i8> @shufflevector_nxv16i8_2(<vscale x 16 x i8> %a) {
+ ; RV32-LABEL: name: shufflevector_nxv16i8_2
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $v8m2
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $v8m2
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 16 x s8>), [[DEF]], shufflemask(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
+ ; RV32-NEXT: $v8m2 = COPY [[SHUF]](<vscale x 16 x s8>)
+ ; RV32-NEXT: PseudoRET implicit $v8m2
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv16i8_2
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $v8m2
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $v8m2
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 16 x s8>), [[DEF]], shufflemask(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
+ ; RV64-NEXT: $v8m2 = COPY [[SHUF]](<vscale x 16 x s8>)
+ ; RV64-NEXT: PseudoRET implicit $v8m2
+ %b = shufflevector <vscale x 16 x i8> %a , <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 1 x i16> @shufflevector_nxv1i16_0() {
+ ; RV32-LABEL: name: shufflevector_nxv1i16_0
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 1 x s16>), [[DEF]], shufflemask(undef)
+ ; RV32-NEXT: $v8 = COPY [[SHUF]](<vscale x 1 x s16>)
+ ; RV32-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv1i16_0
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 1 x s16>), [[DEF]], shufflemask(undef)
+ ; RV64-NEXT: $v8 = COPY [[SHUF]](<vscale x 1 x s16>)
+ ; RV64-NEXT: PseudoRET implicit $v8
+ %a = shufflevector <vscale x 1 x i16> poison, <vscale x 1 x i16> poison, <vscale x 1 x i32> poison
+ ret <vscale x 1 x i16> %a
+}
+
+define <vscale x 1 x i16> @shufflevector_nxv1i16_1() {
+ ; RV32-LABEL: name: shufflevector_nxv1i16_1
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 1 x s16>), [[DEF]], shufflemask(undef)
+ ; RV32-NEXT: $v8 = COPY [[SHUF]](<vscale x 1 x s16>)
+ ; RV32-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv1i16_1
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 1 x s16>), [[DEF]], shufflemask(undef)
+ ; RV64-NEXT: $v8 = COPY [[SHUF]](<vscale x 1 x s16>)
+ ; RV64-NEXT: PseudoRET implicit $v8
+ %a = shufflevector <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i32> undef
+ ret <vscale x 1 x i16> %a
+}
+
+define <vscale x 1 x i16> @shufflevector_nxv1i16_2(<vscale x 1 x i16> %a) {
+ ; RV32-LABEL: name: shufflevector_nxv1i16_2
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s16>) = COPY $v8
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 1 x s16>), [[DEF]], shufflemask(0)
+ ; RV32-NEXT: $v8 = COPY [[SHUF]](<vscale x 1 x s16>)
+ ; RV32-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv1i16_2
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s16>) = COPY $v8
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 1 x s16>), [[DEF]], shufflemask(0)
+ ; RV64-NEXT: $v8 = COPY [[SHUF]](<vscale x 1 x s16>)
+ ; RV64-NEXT: PseudoRET implicit $v8
+ %b = shufflevector <vscale x 1 x i16> %a , <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
+ ret <vscale x 1 x i16> %b
+}
+
+define <vscale x 2 x i16> @shufflevector_nxv2i16_0() {
+ ; RV32-LABEL: name: shufflevector_nxv2i16_0
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 2 x s16>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 2 x s16>), [[DEF]], shufflemask(undef, undef)
+ ; RV32-NEXT: $v8 = COPY [[SHUF]](<vscale x 2 x s16>)
+ ; RV32-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv2i16_0
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 2 x s16>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 2 x s16>), [[DEF]], shufflemask(undef, undef)
+ ; RV64-NEXT: $v8 = COPY [[SHUF]](<vscale x 2 x s16>)
+ ; RV64-NEXT: PseudoRET implicit $v8
+ %a = shufflevector <vscale x 2 x i16> poison, <vscale x 2 x i16> poison, <vscale x 2 x i32> poison
+ ret <vscale x 2 x i16> %a
+}
+
+define <vscale x 2 x i16> @shufflevector_nxv2i16_1() {
+ ; RV32-LABEL: name: shufflevector_nxv2i16_1
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 2 x s16>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 2 x s16>), [[DEF]], shufflemask(undef, undef)
+ ; RV32-NEXT: $v8 = COPY [[SHUF]](<vscale x 2 x s16>)
+ ; RV32-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv2i16_1
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 2 x s16>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 2 x s16>), [[DEF]], shufflemask(undef, undef)
+ ; RV64-NEXT: $v8 = COPY [[SHUF]](<vscale x 2 x s16>)
+ ; RV64-NEXT: PseudoRET implicit $v8
+ %a = shufflevector <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i32> undef
+ ret <vscale x 2 x i16> %a
+}
+
+define <vscale x 2 x i16> @shufflevector_nxv2i16_2(<vscale x 2 x i16> %a) {
+ ; RV32-LABEL: name: shufflevector_nxv2i16_2
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s16>) = COPY $v8
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 2 x s16>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 2 x s16>), [[DEF]], shufflemask(0, 0)
+ ; RV32-NEXT: $v8 = COPY [[SHUF]](<vscale x 2 x s16>)
+ ; RV32-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv2i16_2
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s16>) = COPY $v8
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 2 x s16>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 2 x s16>), [[DEF]], shufflemask(0, 0)
+ ; RV64-NEXT: $v8 = COPY [[SHUF]](<vscale x 2 x s16>)
+ ; RV64-NEXT: PseudoRET implicit $v8
+ %b = shufflevector <vscale x 2 x i16> %a , <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
+ ret <vscale x 2 x i16> %b
+}
+
+define <vscale x 4 x i16> @shufflevector_nxv4i16_0() {
+ ; RV32-LABEL: name: shufflevector_nxv4i16_0
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 4 x s16>), [[DEF]], shufflemask(undef, undef, undef, undef)
+ ; RV32-NEXT: $v8 = COPY [[SHUF]](<vscale x 4 x s16>)
+ ; RV32-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv4i16_0
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 4 x s16>), [[DEF]], shufflemask(undef, undef, undef, undef)
+ ; RV64-NEXT: $v8 = COPY [[SHUF]](<vscale x 4 x s16>)
+ ; RV64-NEXT: PseudoRET implicit $v8
+ %a = shufflevector <vscale x 4 x i16> poison, <vscale x 4 x i16> poison, <vscale x 4 x i32> poison
+ ret <vscale x 4 x i16> %a
+}
+
+define <vscale x 4 x i16> @shufflevector_nxv4i16_1() {
+ ; RV32-LABEL: name: shufflevector_nxv4i16_1
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 4 x s16>), [[DEF]], shufflemask(undef, undef, undef, undef)
+ ; RV32-NEXT: $v8 = COPY [[SHUF]](<vscale x 4 x s16>)
+ ; RV32-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv4i16_1
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 4 x s16>), [[DEF]], shufflemask(undef, undef, undef, undef)
+ ; RV64-NEXT: $v8 = COPY [[SHUF]](<vscale x 4 x s16>)
+ ; RV64-NEXT: PseudoRET implicit $v8
+ %a = shufflevector <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i32> undef
+ ret <vscale x 4 x i16> %a
+}
+
+define <vscale x 4 x i16> @shufflevector_nxv4i16_2(<vscale x 4 x i16> %a) {
+ ; RV32-LABEL: name: shufflevector_nxv4i16_2
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v8
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 4 x s16>), [[DEF]], shufflemask(0, 0, 0, 0)
+ ; RV32-NEXT: $v8 = COPY [[SHUF]](<vscale x 4 x s16>)
+ ; RV32-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv4i16_2
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v8
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 4 x s16>), [[DEF]], shufflemask(0, 0, 0, 0)
+ ; RV64-NEXT: $v8 = COPY [[SHUF]](<vscale x 4 x s16>)
+ ; RV64-NEXT: PseudoRET implicit $v8
+ %b = shufflevector <vscale x 4 x i16> %a , <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
+ ret <vscale x 4 x i16> %b
+}
+
+define <vscale x 8 x i16> @shufflevector_nxv8i16_0() {
+ ; RV32-LABEL: name: shufflevector_nxv8i16_0
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 8 x s16>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 8 x s16>), [[DEF]], shufflemask(undef, undef, undef, undef, undef, undef, undef, undef)
+ ; RV32-NEXT: $v8m2 = COPY [[SHUF]](<vscale x 8 x s16>)
+ ; RV32-NEXT: PseudoRET implicit $v8m2
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv8i16_0
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 8 x s16>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 8 x s16>), [[DEF]], shufflemask(undef, undef, undef, undef, undef, undef, undef, undef)
+ ; RV64-NEXT: $v8m2 = COPY [[SHUF]](<vscale x 8 x s16>)
+ ; RV64-NEXT: PseudoRET implicit $v8m2
+ %a = shufflevector <vscale x 8 x i16> poison, <vscale x 8 x i16> poison, <vscale x 8 x i32> poison
+ ret <vscale x 8 x i16> %a
+}
+
+define <vscale x 8 x i16> @shufflevector_nxv8i16_1() {
+ ; RV32-LABEL: name: shufflevector_nxv8i16_1
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 8 x s16>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 8 x s16>), [[DEF]], shufflemask(undef, undef, undef, undef, undef, undef, undef, undef)
+ ; RV32-NEXT: $v8m2 = COPY [[SHUF]](<vscale x 8 x s16>)
+ ; RV32-NEXT: PseudoRET implicit $v8m2
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv8i16_1
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 8 x s16>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 8 x s16>), [[DEF]], shufflemask(undef, undef, undef, undef, undef, undef, undef, undef)
+ ; RV64-NEXT: $v8m2 = COPY [[SHUF]](<vscale x 8 x s16>)
+ ; RV64-NEXT: PseudoRET implicit $v8m2
+ %a = shufflevector <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i32> undef
+ ret <vscale x 8 x i16> %a
+}
+
+define <vscale x 8 x i16> @shufflevector_nxv8i16_2(<vscale x 8 x i16> %a) {
+ ; RV32-LABEL: name: shufflevector_nxv8i16_2
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $v8m2
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $v8m2
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 8 x s16>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 8 x s16>), [[DEF]], shufflemask(0, 0, 0, 0, 0, 0, 0, 0)
+ ; RV32-NEXT: $v8m2 = COPY [[SHUF]](<vscale x 8 x s16>)
+ ; RV32-NEXT: PseudoRET implicit $v8m2
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv8i16_2
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $v8m2
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $v8m2
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 8 x s16>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 8 x s16>), [[DEF]], shufflemask(0, 0, 0, 0, 0, 0, 0, 0)
+ ; RV64-NEXT: $v8m2 = COPY [[SHUF]](<vscale x 8 x s16>)
+ ; RV64-NEXT: PseudoRET implicit $v8m2
+ %b = shufflevector <vscale x 8 x i16> %a , <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i16> @shufflevector_nxv16i16_0() {
+ ; RV32-LABEL: name: shufflevector_nxv16i16_0
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 16 x s16>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 16 x s16>), [[DEF]], shufflemask(undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef)
+ ; RV32-NEXT: $v8m4 = COPY [[SHUF]](<vscale x 16 x s16>)
+ ; RV32-NEXT: PseudoRET implicit $v8m4
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv16i16_0
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 16 x s16>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 16 x s16>), [[DEF]], shufflemask(undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef)
+ ; RV64-NEXT: $v8m4 = COPY [[SHUF]](<vscale x 16 x s16>)
+ ; RV64-NEXT: PseudoRET implicit $v8m4
+ %a = shufflevector <vscale x 16 x i16> poison, <vscale x 16 x i16> poison, <vscale x 16 x i32> poison
+ ret <vscale x 16 x i16> %a
+}
+
+define <vscale x 16 x i16> @shufflevector_nxv16i16_1() {
+ ; RV32-LABEL: name: shufflevector_nxv16i16_1
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 16 x s16>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 16 x s16>), [[DEF]], shufflemask(undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef)
+ ; RV32-NEXT: $v8m4 = COPY [[SHUF]](<vscale x 16 x s16>)
+ ; RV32-NEXT: PseudoRET implicit $v8m4
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv16i16_1
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 16 x s16>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 16 x s16>), [[DEF]], shufflemask(undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef)
+ ; RV64-NEXT: $v8m4 = COPY [[SHUF]](<vscale x 16 x s16>)
+ ; RV64-NEXT: PseudoRET implicit $v8m4
+ %a = shufflevector <vscale x 16 x i16> undef, <vscale x 16 x i16> undef, <vscale x 16 x i32> undef
+ ret <vscale x 16 x i16> %a
+}
+
+define <vscale x 16 x i16> @shufflevector_nxv16i16_2(<vscale x 16 x i16> %a) {
+ ; RV32-LABEL: name: shufflevector_nxv16i16_2
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $v8m4
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s16>) = COPY $v8m4
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 16 x s16>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 16 x s16>), [[DEF]], shufflemask(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
+ ; RV32-NEXT: $v8m4 = COPY [[SHUF]](<vscale x 16 x s16>)
+ ; RV32-NEXT: PseudoRET implicit $v8m4
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv16i16_2
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $v8m4
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s16>) = COPY $v8m4
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 16 x s16>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 16 x s16>), [[DEF]], shufflemask(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
+ ; RV64-NEXT: $v8m4 = COPY [[SHUF]](<vscale x 16 x s16>)
+ ; RV64-NEXT: PseudoRET implicit $v8m4
+ %b = shufflevector <vscale x 16 x i16> %a , <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer
+ ret <vscale x 16 x i16> %b
+}
+
+define <vscale x 1 x i32> @shufflevector_nxv1i32_0() {
+ ; RV32-LABEL: name: shufflevector_nxv1i32_0
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 1 x s32>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 1 x s32>), [[DEF]], shufflemask(undef)
+ ; RV32-NEXT: $v8 = COPY [[SHUF]](<vscale x 1 x s32>)
+ ; RV32-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv1i32_0
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 1 x s32>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 1 x s32>), [[DEF]], shufflemask(undef)
+ ; RV64-NEXT: $v8 = COPY [[SHUF]](<vscale x 1 x s32>)
+ ; RV64-NEXT: PseudoRET implicit $v8
+ %a = shufflevector <vscale x 1 x i32> poison, <vscale x 1 x i32> poison, <vscale x 1 x i32> poison
+ ret <vscale x 1 x i32> %a
+}
+
+define <vscale x 1 x i32> @shufflevector_nxv1i32_1() {
+ ; RV32-LABEL: name: shufflevector_nxv1i32_1
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 1 x s32>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 1 x s32>), [[DEF]], shufflemask(undef)
+ ; RV32-NEXT: $v8 = COPY [[SHUF]](<vscale x 1 x s32>)
+ ; RV32-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv1i32_1
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 1 x s32>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 1 x s32>), [[DEF]], shufflemask(undef)
+ ; RV64-NEXT: $v8 = COPY [[SHUF]](<vscale x 1 x s32>)
+ ; RV64-NEXT: PseudoRET implicit $v8
+ %a = shufflevector <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef
+ ret <vscale x 1 x i32> %a
+}
+
+define <vscale x 1 x i32> @shufflevector_nxv1i32_2(<vscale x 1 x i32> %a) {
+ ; RV32-LABEL: name: shufflevector_nxv1i32_2
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s32>) = COPY $v8
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 1 x s32>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 1 x s32>), [[DEF]], shufflemask(0)
+ ; RV32-NEXT: $v8 = COPY [[SHUF]](<vscale x 1 x s32>)
+ ; RV32-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv1i32_2
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s32>) = COPY $v8
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 1 x s32>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 1 x s32>), [[DEF]], shufflemask(0)
+ ; RV64-NEXT: $v8 = COPY [[SHUF]](<vscale x 1 x s32>)
+ ; RV64-NEXT: PseudoRET implicit $v8
+ %b = shufflevector <vscale x 1 x i32> %a , <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
+ ret <vscale x 1 x i32> %b
+}
+
+define <vscale x 2 x i32> @shufflevector_nxv2i32_0() {
+ ; RV32-LABEL: name: shufflevector_nxv2i32_0
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 2 x s32>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 2 x s32>), [[DEF]], shufflemask(undef, undef)
+ ; RV32-NEXT: $v8 = COPY [[SHUF]](<vscale x 2 x s32>)
+ ; RV32-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv2i32_0
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 2 x s32>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 2 x s32>), [[DEF]], shufflemask(undef, undef)
+ ; RV64-NEXT: $v8 = COPY [[SHUF]](<vscale x 2 x s32>)
+ ; RV64-NEXT: PseudoRET implicit $v8
+ %a = shufflevector <vscale x 2 x i32> poison, <vscale x 2 x i32> poison, <vscale x 2 x i32> poison
+ ret <vscale x 2 x i32> %a
+}
+
+define <vscale x 2 x i32> @shufflevector_nxv2i32_1() {
+ ; RV32-LABEL: name: shufflevector_nxv2i32_1
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 2 x s32>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 2 x s32>), [[DEF]], shufflemask(undef, undef)
+ ; RV32-NEXT: $v8 = COPY [[SHUF]](<vscale x 2 x s32>)
+ ; RV32-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv2i32_1
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 2 x s32>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 2 x s32>), [[DEF]], shufflemask(undef, undef)
+ ; RV64-NEXT: $v8 = COPY [[SHUF]](<vscale x 2 x s32>)
+ ; RV64-NEXT: PseudoRET implicit $v8
+ %a = shufflevector <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef
+ ret <vscale x 2 x i32> %a
+}
+
+define <vscale x 2 x i32> @shufflevector_nxv2i32_2(<vscale x 2 x i32> %a) {
+ ; RV32-LABEL: name: shufflevector_nxv2i32_2
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s32>) = COPY $v8
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 2 x s32>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 2 x s32>), [[DEF]], shufflemask(0, 0)
+ ; RV32-NEXT: $v8 = COPY [[SHUF]](<vscale x 2 x s32>)
+ ; RV32-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv2i32_2
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s32>) = COPY $v8
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 2 x s32>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 2 x s32>), [[DEF]], shufflemask(0, 0)
+ ; RV64-NEXT: $v8 = COPY [[SHUF]](<vscale x 2 x s32>)
+ ; RV64-NEXT: PseudoRET implicit $v8
+ %b = shufflevector <vscale x 2 x i32> %a , <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
+ ret <vscale x 2 x i32> %b
+}
+
+define <vscale x 4 x i32> @shufflevector_nxv4i32_0() {
+ ; RV32-LABEL: name: shufflevector_nxv4i32_0
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 4 x s32>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 4 x s32>), [[DEF]], shufflemask(undef, undef, undef, undef)
+ ; RV32-NEXT: $v8m2 = COPY [[SHUF]](<vscale x 4 x s32>)
+ ; RV32-NEXT: PseudoRET implicit $v8m2
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv4i32_0
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 4 x s32>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 4 x s32>), [[DEF]], shufflemask(undef, undef, undef, undef)
+ ; RV64-NEXT: $v8m2 = COPY [[SHUF]](<vscale x 4 x s32>)
+ ; RV64-NEXT: PseudoRET implicit $v8m2
+ %a = shufflevector <vscale x 4 x i32> poison, <vscale x 4 x i32> poison, <vscale x 4 x i32> poison
+ ret <vscale x 4 x i32> %a
+}
+
+define <vscale x 4 x i32> @shufflevector_nxv4i32_1() {
+ ; RV32-LABEL: name: shufflevector_nxv4i32_1
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 4 x s32>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 4 x s32>), [[DEF]], shufflemask(undef, undef, undef, undef)
+ ; RV32-NEXT: $v8m2 = COPY [[SHUF]](<vscale x 4 x s32>)
+ ; RV32-NEXT: PseudoRET implicit $v8m2
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv4i32_1
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 4 x s32>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 4 x s32>), [[DEF]], shufflemask(undef, undef, undef, undef)
+ ; RV64-NEXT: $v8m2 = COPY [[SHUF]](<vscale x 4 x s32>)
+ ; RV64-NEXT: PseudoRET implicit $v8m2
+ %a = shufflevector <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef
+ ret <vscale x 4 x i32> %a
+}
+
+define <vscale x 4 x i32> @shufflevector_nxv4i32_2(<vscale x 4 x i32> %a) {
+ ; RV32-LABEL: name: shufflevector_nxv4i32_2
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $v8m2
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $v8m2
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 4 x s32>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 4 x s32>), [[DEF]], shufflemask(0, 0, 0, 0)
+ ; RV32-NEXT: $v8m2 = COPY [[SHUF]](<vscale x 4 x s32>)
+ ; RV32-NEXT: PseudoRET implicit $v8m2
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv4i32_2
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $v8m2
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $v8m2
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 4 x s32>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 4 x s32>), [[DEF]], shufflemask(0, 0, 0, 0)
+ ; RV64-NEXT: $v8m2 = COPY [[SHUF]](<vscale x 4 x s32>)
+ ; RV64-NEXT: PseudoRET implicit $v8m2
+ %b = shufflevector <vscale x 4 x i32> %a , <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i32> @shufflevector_nxv8i32_0() {
+ ; RV32-LABEL: name: shufflevector_nxv8i32_0
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 8 x s32>), [[DEF]], shufflemask(undef, undef, undef, undef, undef, undef, undef, undef)
+ ; RV32-NEXT: $v8m4 = COPY [[SHUF]](<vscale x 8 x s32>)
+ ; RV32-NEXT: PseudoRET implicit $v8m4
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv8i32_0
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 8 x s32>), [[DEF]], shufflemask(undef, undef, undef, undef, undef, undef, undef, undef)
+ ; RV64-NEXT: $v8m4 = COPY [[SHUF]](<vscale x 8 x s32>)
+ ; RV64-NEXT: PseudoRET implicit $v8m4
+ %a = shufflevector <vscale x 8 x i32> poison, <vscale x 8 x i32> poison, <vscale x 8 x i32> poison
+ ret <vscale x 8 x i32> %a
+}
+
+define <vscale x 8 x i32> @shufflevector_nxv8i32_1() {
+ ; RV32-LABEL: name: shufflevector_nxv8i32_1
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 8 x s32>), [[DEF]], shufflemask(undef, undef, undef, undef, undef, undef, undef, undef)
+ ; RV32-NEXT: $v8m4 = COPY [[SHUF]](<vscale x 8 x s32>)
+ ; RV32-NEXT: PseudoRET implicit $v8m4
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv8i32_1
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 8 x s32>), [[DEF]], shufflemask(undef, undef, undef, undef, undef, undef, undef, undef)
+ ; RV64-NEXT: $v8m4 = COPY [[SHUF]](<vscale x 8 x s32>)
+ ; RV64-NEXT: PseudoRET implicit $v8m4
+ %a = shufflevector <vscale x 8 x i32> undef, <vscale x 8 x i32> undef, <vscale x 8 x i32> undef
+ ret <vscale x 8 x i32> %a
+}
+
+define <vscale x 8 x i32> @shufflevector_nxv8i32_2(<vscale x 8 x i32> %a) {
+ ; RV32-LABEL: name: shufflevector_nxv8i32_2
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $v8m4
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s32>) = COPY $v8m4
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 8 x s32>), [[DEF]], shufflemask(0, 0, 0, 0, 0, 0, 0, 0)
+ ; RV32-NEXT: $v8m4 = COPY [[SHUF]](<vscale x 8 x s32>)
+ ; RV32-NEXT: PseudoRET implicit $v8m4
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv8i32_2
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $v8m4
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s32>) = COPY $v8m4
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 8 x s32>), [[DEF]], shufflemask(0, 0, 0, 0, 0, 0, 0, 0)
+ ; RV64-NEXT: $v8m4 = COPY [[SHUF]](<vscale x 8 x s32>)
+ ; RV64-NEXT: PseudoRET implicit $v8m4
+ %b = shufflevector <vscale x 8 x i32> %a , <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+ ret <vscale x 8 x i32> %b
+}
+
+define <vscale x 16 x i32> @shufflevector_nxv16i32_0() {
+ ; RV32-LABEL: name: shufflevector_nxv16i32_0
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 16 x s32>), [[DEF]], shufflemask(undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef)
+ ; RV32-NEXT: $v8m8 = COPY [[SHUF]](<vscale x 16 x s32>)
+ ; RV32-NEXT: PseudoRET implicit $v8m8
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv16i32_0
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 16 x s32>), [[DEF]], shufflemask(undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef)
+ ; RV64-NEXT: $v8m8 = COPY [[SHUF]](<vscale x 16 x s32>)
+ ; RV64-NEXT: PseudoRET implicit $v8m8
+ %a = shufflevector <vscale x 16 x i32> poison, <vscale x 16 x i32> poison, <vscale x 16 x i32> poison
+ ret <vscale x 16 x i32> %a
+}
+
+define <vscale x 16 x i32> @shufflevector_nxv16i32_1() {
+ ; RV32-LABEL: name: shufflevector_nxv16i32_1
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 16 x s32>), [[DEF]], shufflemask(undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef)
+ ; RV32-NEXT: $v8m8 = COPY [[SHUF]](<vscale x 16 x s32>)
+ ; RV32-NEXT: PseudoRET implicit $v8m8
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv16i32_1
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 16 x s32>), [[DEF]], shufflemask(undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef)
+ ; RV64-NEXT: $v8m8 = COPY [[SHUF]](<vscale x 16 x s32>)
+ ; RV64-NEXT: PseudoRET implicit $v8m8
+ %a = shufflevector <vscale x 16 x i32> undef, <vscale x 16 x i32> undef, <vscale x 16 x i32> undef
+ ret <vscale x 16 x i32> %a
+}
+
+define <vscale x 16 x i32> @shufflevector_nxv16i32_2(<vscale x 16 x i32> %a) {
+ ; RV32-LABEL: name: shufflevector_nxv16i32_2
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $v8m8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s32>) = COPY $v8m8
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 16 x s32>), [[DEF]], shufflemask(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
+ ; RV32-NEXT: $v8m8 = COPY [[SHUF]](<vscale x 16 x s32>)
+ ; RV32-NEXT: PseudoRET implicit $v8m8
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv16i32_2
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $v8m8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s32>) = COPY $v8m8
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 16 x s32>), [[DEF]], shufflemask(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
+ ; RV64-NEXT: $v8m8 = COPY [[SHUF]](<vscale x 16 x s32>)
+ ; RV64-NEXT: PseudoRET implicit $v8m8
+ %b = shufflevector <vscale x 16 x i32> %a , <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer
+ ret <vscale x 16 x i32> %b
+}
+
+define <vscale x 1 x i64> @shufflevector_nxv1i64_0() {
+ ; RV32-LABEL: name: shufflevector_nxv1i64_0
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 1 x s64>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 1 x s64>), [[DEF]], shufflemask(undef)
+ ; RV32-NEXT: $v8 = COPY [[SHUF]](<vscale x 1 x s64>)
+ ; RV32-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv1i64_0
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 1 x s64>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 1 x s64>), [[DEF]], shufflemask(undef)
+ ; RV64-NEXT: $v8 = COPY [[SHUF]](<vscale x 1 x s64>)
+ ; RV64-NEXT: PseudoRET implicit $v8
+ %a = shufflevector <vscale x 1 x i64> poison, <vscale x 1 x i64> poison, <vscale x 1 x i32> poison
+ ret <vscale x 1 x i64> %a
+}
+
+define <vscale x 1 x i64> @shufflevector_nxv1i64_1() {
+ ; RV32-LABEL: name: shufflevector_nxv1i64_1
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 1 x s64>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 1 x s64>), [[DEF]], shufflemask(undef)
+ ; RV32-NEXT: $v8 = COPY [[SHUF]](<vscale x 1 x s64>)
+ ; RV32-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv1i64_1
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 1 x s64>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 1 x s64>), [[DEF]], shufflemask(undef)
+ ; RV64-NEXT: $v8 = COPY [[SHUF]](<vscale x 1 x s64>)
+ ; RV64-NEXT: PseudoRET implicit $v8
+ %a = shufflevector <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i32> undef
+ ret <vscale x 1 x i64> %a
+}
+
+define <vscale x 1 x i64> @shufflevector_nxv1i64_2(<vscale x 1 x i64> %a) {
+ ; RV32-LABEL: name: shufflevector_nxv1i64_2
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s64>) = COPY $v8
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 1 x s64>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 1 x s64>), [[DEF]], shufflemask(0)
+ ; RV32-NEXT: $v8 = COPY [[SHUF]](<vscale x 1 x s64>)
+ ; RV32-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv1i64_2
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s64>) = COPY $v8
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 1 x s64>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 1 x s64>), [[DEF]], shufflemask(0)
+ ; RV64-NEXT: $v8 = COPY [[SHUF]](<vscale x 1 x s64>)
+ ; RV64-NEXT: PseudoRET implicit $v8
+ %b = shufflevector <vscale x 1 x i64> %a , <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
+ ret <vscale x 1 x i64> %b
+}
+
+define <vscale x 2 x i64> @shufflevector_nxv2i64_0() {
+ ; RV32-LABEL: name: shufflevector_nxv2i64_0
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 2 x s64>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 2 x s64>), [[DEF]], shufflemask(undef, undef)
+ ; RV32-NEXT: $v8m2 = COPY [[SHUF]](<vscale x 2 x s64>)
+ ; RV32-NEXT: PseudoRET implicit $v8m2
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv2i64_0
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 2 x s64>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 2 x s64>), [[DEF]], shufflemask(undef, undef)
+ ; RV64-NEXT: $v8m2 = COPY [[SHUF]](<vscale x 2 x s64>)
+ ; RV64-NEXT: PseudoRET implicit $v8m2
+ %a = shufflevector <vscale x 2 x i64> poison, <vscale x 2 x i64> poison, <vscale x 2 x i32> poison
+ ret <vscale x 2 x i64> %a
+}
+
+define <vscale x 2 x i64> @shufflevector_nxv2i64_1() {
+ ; RV32-LABEL: name: shufflevector_nxv2i64_1
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 2 x s64>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 2 x s64>), [[DEF]], shufflemask(undef, undef)
+ ; RV32-NEXT: $v8m2 = COPY [[SHUF]](<vscale x 2 x s64>)
+ ; RV32-NEXT: PseudoRET implicit $v8m2
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv2i64_1
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 2 x s64>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 2 x s64>), [[DEF]], shufflemask(undef, undef)
+ ; RV64-NEXT: $v8m2 = COPY [[SHUF]](<vscale x 2 x s64>)
+ ; RV64-NEXT: PseudoRET implicit $v8m2
+ %a = shufflevector <vscale x 2 x i64> undef, <vscale x 2 x i64> undef, <vscale x 2 x i32> undef
+ ret <vscale x 2 x i64> %a
+}
+
+define <vscale x 2 x i64> @shufflevector_nxv2i64_2(<vscale x 2 x i64> %a) {
+ ; RV32-LABEL: name: shufflevector_nxv2i64_2
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $v8m2
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $v8m2
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 2 x s64>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 2 x s64>), [[DEF]], shufflemask(0, 0)
+ ; RV32-NEXT: $v8m2 = COPY [[SHUF]](<vscale x 2 x s64>)
+ ; RV32-NEXT: PseudoRET implicit $v8m2
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv2i64_2
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $v8m2
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $v8m2
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 2 x s64>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 2 x s64>), [[DEF]], shufflemask(0, 0)
+ ; RV64-NEXT: $v8m2 = COPY [[SHUF]](<vscale x 2 x s64>)
+ ; RV64-NEXT: PseudoRET implicit $v8m2
+ %b = shufflevector <vscale x 2 x i64> %a , <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i64> @shufflevector_nxv4i64_0() {
+ ; RV32-LABEL: name: shufflevector_nxv4i64_0
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 4 x s64>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 4 x s64>), [[DEF]], shufflemask(undef, undef, undef, undef)
+ ; RV32-NEXT: $v8m4 = COPY [[SHUF]](<vscale x 4 x s64>)
+ ; RV32-NEXT: PseudoRET implicit $v8m4
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv4i64_0
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 4 x s64>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 4 x s64>), [[DEF]], shufflemask(undef, undef, undef, undef)
+ ; RV64-NEXT: $v8m4 = COPY [[SHUF]](<vscale x 4 x s64>)
+ ; RV64-NEXT: PseudoRET implicit $v8m4
+ %a = shufflevector <vscale x 4 x i64> poison, <vscale x 4 x i64> poison, <vscale x 4 x i32> poison
+ ret <vscale x 4 x i64> %a
+}
+
+define <vscale x 4 x i64> @shufflevector_nxv4i64_1() {
+ ; RV32-LABEL: name: shufflevector_nxv4i64_1
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 4 x s64>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 4 x s64>), [[DEF]], shufflemask(undef, undef, undef, undef)
+ ; RV32-NEXT: $v8m4 = COPY [[SHUF]](<vscale x 4 x s64>)
+ ; RV32-NEXT: PseudoRET implicit $v8m4
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv4i64_1
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 4 x s64>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 4 x s64>), [[DEF]], shufflemask(undef, undef, undef, undef)
+ ; RV64-NEXT: $v8m4 = COPY [[SHUF]](<vscale x 4 x s64>)
+ ; RV64-NEXT: PseudoRET implicit $v8m4
+ %a = shufflevector <vscale x 4 x i64> undef, <vscale x 4 x i64> undef, <vscale x 4 x i32> undef
+ ret <vscale x 4 x i64> %a
+}
+
+define <vscale x 4 x i64> @shufflevector_nxv4i64_2(<vscale x 4 x i64> %a) {
+ ; RV32-LABEL: name: shufflevector_nxv4i64_2
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $v8m4
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s64>) = COPY $v8m4
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 4 x s64>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 4 x s64>), [[DEF]], shufflemask(0, 0, 0, 0)
+ ; RV32-NEXT: $v8m4 = COPY [[SHUF]](<vscale x 4 x s64>)
+ ; RV32-NEXT: PseudoRET implicit $v8m4
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv4i64_2
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $v8m4
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s64>) = COPY $v8m4
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 4 x s64>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 4 x s64>), [[DEF]], shufflemask(0, 0, 0, 0)
+ ; RV64-NEXT: $v8m4 = COPY [[SHUF]](<vscale x 4 x s64>)
+ ; RV64-NEXT: PseudoRET implicit $v8m4
+ %b = shufflevector <vscale x 4 x i64> %a , <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
+ ret <vscale x 4 x i64> %b
+}
+
+define <vscale x 8 x i64> @shufflevector_nxv8i64_0() {
+ ; RV32-LABEL: name: shufflevector_nxv8i64_0
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 8 x s64>), [[DEF]], shufflemask(undef, undef, undef, undef, undef, undef, undef, undef)
+ ; RV32-NEXT: $v8m8 = COPY [[SHUF]](<vscale x 8 x s64>)
+ ; RV32-NEXT: PseudoRET implicit $v8m8
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv8i64_0
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 8 x s64>), [[DEF]], shufflemask(undef, undef, undef, undef, undef, undef, undef, undef)
+ ; RV64-NEXT: $v8m8 = COPY [[SHUF]](<vscale x 8 x s64>)
+ ; RV64-NEXT: PseudoRET implicit $v8m8
+ %a = shufflevector <vscale x 8 x i64> poison, <vscale x 8 x i64> poison, <vscale x 8 x i32> poison
+ ret <vscale x 8 x i64> %a
+}
+
+define <vscale x 8 x i64> @shufflevector_nxv8i64_1() {
+ ; RV32-LABEL: name: shufflevector_nxv8i64_1
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 8 x s64>), [[DEF]], shufflemask(undef, undef, undef, undef, undef, undef, undef, undef)
+ ; RV32-NEXT: $v8m8 = COPY [[SHUF]](<vscale x 8 x s64>)
+ ; RV32-NEXT: PseudoRET implicit $v8m8
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv8i64_1
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 8 x s64>), [[DEF]], shufflemask(undef, undef, undef, undef, undef, undef, undef, undef)
+ ; RV64-NEXT: $v8m8 = COPY [[SHUF]](<vscale x 8 x s64>)
+ ; RV64-NEXT: PseudoRET implicit $v8m8
+ %a = shufflevector <vscale x 8 x i64> undef, <vscale x 8 x i64> undef, <vscale x 8 x i32> undef
+ ret <vscale x 8 x i64> %a
+}
+
+define <vscale x 8 x i64> @shufflevector_nxv8i64_2(<vscale x 8 x i64> %a) {
+ ; RV32-LABEL: name: shufflevector_nxv8i64_2
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $v8m8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s64>) = COPY $v8m8
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 8 x s64>), [[DEF]], shufflemask(0, 0, 0, 0, 0, 0, 0, 0)
+ ; RV32-NEXT: $v8m8 = COPY [[SHUF]](<vscale x 8 x s64>)
+ ; RV32-NEXT: PseudoRET implicit $v8m8
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv8i64_2
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $v8m8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s64>) = COPY $v8m8
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_SHUFFLE_VECTOR [[COPY]](<vscale x 8 x s64>), [[DEF]], shufflemask(0, 0, 0, 0, 0, 0, 0, 0)
+ ; RV64-NEXT: $v8m8 = COPY [[SHUF]](<vscale x 8 x s64>)
+ ; RV64-NEXT: PseudoRET implicit $v8m8
+ %b = shufflevector <vscale x 8 x i64> %a , <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
+ ret <vscale x 8 x i64> %b
+}
+
+define <vscale x 16 x i64> @shufflevector_nxv16i64_0() {
+ ; RV32-LABEL: name: shufflevector_nxv16i64_0
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s64>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 16 x s64>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 16 x s64>), [[DEF]], shufflemask(undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef)
+ ; RV32-NEXT: [[UV:%[0-9]+]]:_(<vscale x 8 x s64>), [[UV1:%[0-9]+]]:_(<vscale x 8 x s64>) = G_UNMERGE_VALUES [[SHUF]](<vscale x 16 x s64>)
+ ; RV32-NEXT: $v8m8 = COPY [[UV]](<vscale x 8 x s64>)
+ ; RV32-NEXT: $v16m8 = COPY [[UV1]](<vscale x 8 x s64>)
+ ; RV32-NEXT: PseudoRET implicit $v8m8, implicit $v16m8
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv16i64_0
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s64>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 16 x s64>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 16 x s64>), [[DEF]], shufflemask(undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef)
+ ; RV64-NEXT: [[UV:%[0-9]+]]:_(<vscale x 8 x s64>), [[UV1:%[0-9]+]]:_(<vscale x 8 x s64>) = G_UNMERGE_VALUES [[SHUF]](<vscale x 16 x s64>)
+ ; RV64-NEXT: $v8m8 = COPY [[UV]](<vscale x 8 x s64>)
+ ; RV64-NEXT: $v16m8 = COPY [[UV1]](<vscale x 8 x s64>)
+ ; RV64-NEXT: PseudoRET implicit $v8m8, implicit $v16m8
+ %a = shufflevector <vscale x 16 x i64> poison, <vscale x 16 x i64> poison, <vscale x 16 x i32> poison
+ ret <vscale x 16 x i64> %a
+}
+
+define <vscale x 16 x i64> @shufflevector_nxv16i64_1() {
+ ; RV32-LABEL: name: shufflevector_nxv16i64_1
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s64>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 16 x s64>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 16 x s64>), [[DEF]], shufflemask(undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef)
+ ; RV32-NEXT: [[UV:%[0-9]+]]:_(<vscale x 8 x s64>), [[UV1:%[0-9]+]]:_(<vscale x 8 x s64>) = G_UNMERGE_VALUES [[SHUF]](<vscale x 16 x s64>)
+ ; RV32-NEXT: $v8m8 = COPY [[UV]](<vscale x 8 x s64>)
+ ; RV32-NEXT: $v16m8 = COPY [[UV1]](<vscale x 8 x s64>)
+ ; RV32-NEXT: PseudoRET implicit $v8m8, implicit $v16m8
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv16i64_1
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s64>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 16 x s64>) = G_SHUFFLE_VECTOR [[DEF]](<vscale x 16 x s64>), [[DEF]], shufflemask(undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef, undef)
+ ; RV64-NEXT: [[UV:%[0-9]+]]:_(<vscale x 8 x s64>), [[UV1:%[0-9]+]]:_(<vscale x 8 x s64>) = G_UNMERGE_VALUES [[SHUF]](<vscale x 16 x s64>)
+ ; RV64-NEXT: $v8m8 = COPY [[UV]](<vscale x 8 x s64>)
+ ; RV64-NEXT: $v16m8 = COPY [[UV1]](<vscale x 8 x s64>)
+ ; RV64-NEXT: PseudoRET implicit $v8m8, implicit $v16m8
+ %a = shufflevector <vscale x 16 x i64> undef, <vscale x 16 x i64> undef, <vscale x 16 x i32> undef
+ ret <vscale x 16 x i64> %a
+}
+
+define <vscale x 16 x i64> @shufflevector_nxv16i64_2(<vscale x 16 x i64> %a) {
+ ; RV32-LABEL: name: shufflevector_nxv16i64_2
+ ; RV32: bb.1 (%ir-block.0):
+ ; RV32-NEXT: liveins: $v8m8, $v16m8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s64>) = COPY $v8m8
+ ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x s64>) = COPY $v16m8
+ ; RV32-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 16 x s64>) = G_CONCAT_VECTORS [[COPY]](<vscale x 8 x s64>), [[COPY1]](<vscale x 8 x s64>)
+ ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s64>) = G_IMPLICIT_DEF
+ ; RV32-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 16 x s64>) = G_SHUFFLE_VECTOR [[CONCAT_VECTORS]](<vscale x 16 x s64>), [[DEF]], shufflemask(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
+ ; RV32-NEXT: [[UV:%[0-9]+]]:_(<vscale x 8 x s64>), [[UV1:%[0-9]+]]:_(<vscale x 8 x s64>) = G_UNMERGE_VALUES [[SHUF]](<vscale x 16 x s64>)
+ ; RV32-NEXT: $v8m8 = COPY [[UV]](<vscale x 8 x s64>)
+ ; RV32-NEXT: $v16m8 = COPY [[UV1]](<vscale x 8 x s64>)
+ ; RV32-NEXT: PseudoRET implicit $v8m8, implicit $v16m8
+ ;
+ ; RV64-LABEL: name: shufflevector_nxv16i64_2
+ ; RV64: bb.1 (%ir-block.0):
+ ; RV64-NEXT: liveins: $v8m8, $v16m8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s64>) = COPY $v8m8
+ ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x s64>) = COPY $v16m8
+ ; RV64-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 16 x s64>) = G_CONCAT_VECTORS [[COPY]](<vscale x 8 x s64>), [[COPY1]](<vscale x 8 x s64>)
+ ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s64>) = G_IMPLICIT_DEF
+ ; RV64-NEXT: [[SHUF:%[0-9]+]]:_(<vscale x 16 x s64>) = G_SHUFFLE_VECTOR [[CONCAT_VECTORS]](<vscale x 16 x s64>), [[DEF]], shufflemask(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
+ ; RV64-NEXT: [[UV:%[0-9]+]]:_(<vscale x 8 x s64>), [[UV1:%[0-9]+]]:_(<vscale x 8 x s64>) = G_UNMERGE_VALUES [[SHUF]](<vscale x 16 x s64>)
+ ; RV64-NEXT: $v8m8 = COPY [[UV]](<vscale x 8 x s64>)
+ ; RV64-NEXT: $v16m8 = COPY [[UV1]](<vscale x 8 x s64>)
+ ; RV64-NEXT: PseudoRET implicit $v8m8, implicit $v16m8
+ %b = shufflevector <vscale x 16 x i64> %a , <vscale x 16 x i64> poison, <vscale x 16 x i32> zeroinitializer
+ ret <vscale x 16 x i64> %b
+}
+
+
+
>From 698f604e839e85a82d61f3b8e7b865cfefe78415 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Mon, 5 Feb 2024 07:40:20 -0800
Subject: [PATCH 5/5] fixme! add machineverifier tests for new report cases
---
llvm/lib/CodeGen/MachineVerifier.cpp | 3 ++-
llvm/test/MachineVerifier/test_g_shuffle_vector.mir | 11 +++++++++++
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index ef1cefc4872ac..8ccd4192a0014 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -1635,7 +1635,8 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
[&MaskIdxes](int M) { return M == MaskIdxes[0]; }))
report("Elements of a scalable G_SHUFFLE_VECTOR mask must match", MI);
if (MaskIdxes[0] != 0 && MaskIdxes[0] != -1)
- report("Elements of a scalable G_SHUFFLE_VECTOR mask be zero or undef",
+ report("Elements of a scalable G_SHUFFLE_VECTOR mask must be zero or "
+ "undef",
MI);
} else {
// Idxes for fixed vectors must be in bounds or undef, which is
diff --git a/llvm/test/MachineVerifier/test_g_shuffle_vector.mir b/llvm/test/MachineVerifier/test_g_shuffle_vector.mir
index 6aba6731c9fee..41f46d0c184ee 100644
--- a/llvm/test/MachineVerifier/test_g_shuffle_vector.mir
+++ b/llvm/test/MachineVerifier/test_g_shuffle_vector.mir
@@ -56,4 +56,15 @@ body: |
%22:_(s32) = G_IMPLICIT_DEF
%20:_(<2 x s32>) = G_SHUFFLE_VECTOR %22, %22, shufflemask(0, 2)
+ %23:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF
+ %24:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF
+
+ ; CHECK: Bad machine code: Wrong result type for shufflemask
+ %25:_(<vscale x 1 x s32>) = G_SHUFFLE_VECTOR %23, %23, shufflemask(0, 0)
+
+ ; CHECK: Elements of a scalable G_SHUFFLE_VECTOR mask must match
+ %26:_(<vscale x 2 x s32>) = G_SHUFFLE_VECTOR %24, %24, shufflemask(0, -1)
+
+ ; CHECK: Bad machine code: Elements of a scalable G_SHUFFLE_VECTOR mask must be zero or undef
+ %27:_(<vscale x 2 x s32>) = G_SHUFFLE_VECTOR %24, %24, shufflemask(1, 1)
...
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