[llvm] [AMDGPU] Don't fix the scavenge slot at offset 0 (PR #79136)

[Matt Arsenault via llvm-commits]

arsenm wrote:

> > This means that we need to fully handle access by incrementing SP and decrementing after. That was broken at some point. Do we still hit the PEI logic to keep the scavenging slot as close to the incoming SP as possible?
> 
> I'm not sure I follow, can you please clarify what you have in mind? Since the change only affects entry and chain functions, there's no incoming SP and we should be accessing the stack (scavenge slot included) directly with offsets, not via SP. If something were wrong with the way PEI is handling the SP, wouldn't that affect non-entry functions instead?

The problem this was solving was if you have offsets that are larger than can be encoded in the immediate offset of the buffer instructions. Fixing it at 0 ensures this cannot happen. If the offset is larger, you either need a free register to materialize the constant in, or inc/dec a reserved frame register around the use 

https://github.com/llvm/llvm-project/pull/79136