[llvm] [RFC] implement convergence control in MIR using SelectionDAG (PR #71785)

[Matt Arsenault via llvm-commits]

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@@ -1193,7 +1193,9 @@ EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
 
   // Run post-isel target hook to adjust this instruction if needed.
   if (II.hasPostISelHook())
-    TLI->AdjustInstrPostInstrSelection(*MIB, Node);
+    TLI->AdjustInstrPostInstrSelection(
+        *MIB, Node,
+        [this, &VRBaseMap](SDValue Op) { return getVR(Op, VRBaseMap); });
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arsenm wrote:

Yes, I mean pass around FunctionLoweringInfo. 

The implicit_def special casing looks weird to me. Seems like an unnecessary pre-optimization for something that's easy to rematerialize 

https://github.com/llvm/llvm-project/pull/71785