[llvm] [LV, VP]VP intrinsics support for the Loop Vectorizer (PR #76172)

[Florian Hahn via llvm-commits]

https://github.com/fhahn commented:

>I checked the description, did not find big difference between the description and the code. Could you point explicitly, which part must be updated?

For the title, I'd suggest explicitly stating that this adds a new tail-folding mode using EVL

```
Our first approach (implemented in this patch) builds on top of the existing tail-folding mechanism in the LV, but instead of generating masked intrinsics for memory operations it generates VP intrinsics for loads/stores instructions.
```

Would be good to mention this patch 1) adds a new VPlanTransforms to replace the wide header predicate compare with EVL and 2) updates codegen for load/stores to use VP store/load with EVL.

```
Other important part of this approach is how the Explicit Vector Length is computed. (We use active vector length and explicit vector length interchangeably; VP intrinsics define this vector length parameter as Explicit Vector Length (EVL)). We consider the following three ways to compute the EVL parameter for the VP Intrinsics.

The simplest way is to use the VF as EVL and rely solely on the mask parameter to control predication. The mask parameter is the same as computed for current tail-folding implementation.
The second way is to insert instructions to compute min(VF, trip_count - index) for each vector iteration.
For architectures like RISC-V, which have special instruction to compute/set an explicit vector length, we also introduce an experimental intrinsic get_vector_length, that can be lowered to architecture specific instruction(s) to compute EVL.
```

Better to just state what option is chosen for the implementation (or at least make it explicit that the patch only adds the 3rd one?)

I'd also drop the tentative roadmap and mention the current limitation (UF = 1, no reductions, dep-distance restrictions, no reverse access)

https://github.com/llvm/llvm-project/pull/76172