[llvm] [TTI][RISCV]Improve costs for fixed vector whole reg extract/insert. (PR #80164)

[Alexey Bataev via llvm-commits]

alexey-bataev wrote:

> > > Don't we need to know the exact vlen to know where register boundaries are?
> > 
> > 
> > I use getRegUsageForType() to get this info.
> 
> That tells the maximum number of registers needed for the type assuming a minimum VLEN. If hardware VLEN is more than the minimum VLEN, we still use the extra registers but the elements in them are not used since they would be past VL. CodeGen has to use a slidedown unless we also know the maximum VLEN is the same as the minimum VLEN.

Do we have anything in TTI that returns correct VLEN?

https://github.com/llvm/llvm-project/pull/80164