[llvm] [RISCV][Isel] Remove redundant vmerge for the scalable vwadd(u).wv (PR #80079)

[via llvm-commits]

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@@ -13795,13 +13798,22 @@ static SDValue combineVWADDWSelect(SDNode *N, SelectionDAG &DAG) {
 
   // False value of MergeOp should be all zeros
   SDValue Z = MergeOp->getOperand(2);
-  if (Z.getOpcode() != ISD::INSERT_SUBVECTOR)
-    return SDValue();
-  if (!ISD::isBuildVectorAllZeros(Z.getOperand(1).getNode()))
-    return SDValue();
-  if (!isNullOrNullSplat(Z.getOperand(0)) && !Z.getOperand(0).isUndef())
+
+  // Scalable vector
+  if (MergeOpc == ISD::VSELECT &&
+      !ISD::isConstantSplatVectorAllZeros(Z.getNode()))
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sun-jacobi wrote:

> The BUILD_VECTOR should be removed before the last round of DAG combine. What does the fixed vector code look like in the last DAG combine?

It will be `(extract_subvector (RISCVISD::VMV_V_X_VL...`

https://github.com/llvm/llvm-project/pull/80079