[llvm] ae46855 - [Target] Use getConstantOperand (NFC)

[Kazu Hirata via llvm-commits]

Author: Kazu Hirata
Date: 2024-01-28T18:03:38-08:00
New Revision: ae46855f53b6fe39a8d17797a49b2911c08fb973

URL: https://github.com/llvm/llvm-project/commit/ae46855f53b6fe39a8d17797a49b2911c08fb973
DIFF: https://github.com/llvm/llvm-project/commit/ae46855f53b6fe39a8d17797a49b2911c08fb973.diff

LOG: [Target] Use getConstantOperand (NFC)

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    llvm/lib/Target/ARM/ARMISelLowering.cpp
    llvm/lib/Target/PowerPC/PPCISelLowering.cpp
    llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index ae0f0605a4a338..226f6f969253f0 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -7726,8 +7726,7 @@ SDValue SITargetLowering::lowerImage(SDValue Op,
     }
   }
 
-  unsigned CPol = cast<ConstantSDNode>(
-      Op.getOperand(ArgOffset + Intr->CachePolicyIndex))->getZExtValue();
+  unsigned CPol = Op.getConstantOperandVal(ArgOffset + Intr->CachePolicyIndex);
   if (BaseOpcode->Atomic)
     CPol |= AMDGPU::CPol::GLC; // TODO no-return optimization
   if (CPol & ~((IsGFX12Plus ? AMDGPU::CPol::ALL : AMDGPU::CPol::ALL_pregfx12) |

diff  --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 98117e95f53a6e..bf8c877a547cdf 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -4068,9 +4068,7 @@ SDValue ARMTargetLowering::LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op,
 SDValue ARMTargetLowering::LowerINTRINSIC_VOID(
     SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) const {
   unsigned IntNo =
-      cast<ConstantSDNode>(
-          Op.getOperand(Op.getOperand(0).getValueType() == MVT::Other))
-          ->getZExtValue();
+      Op.getConstantOperandVal(Op.getOperand(0).getValueType() == MVT::Other);
   switch (IntNo) {
     default:
       return SDValue();  // Don't custom lower most intrinsics.

diff  --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 1ff74f86f1a2b3..51becf1d5b8584 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -11253,9 +11253,9 @@ SDValue PPCTargetLowering::LowerIS_FPCLASS(SDValue Op,
                                            SelectionDAG &DAG) const {
   assert(Subtarget.hasP9Vector() && "Test data class requires Power9");
   SDValue LHS = Op.getOperand(0);
-  const auto *RHS = cast<ConstantSDNode>(Op.getOperand(1));
+  uint64_t RHSC = Op.getConstantOperandVal(1);
   SDLoc Dl(Op);
-  FPClassTest Category = static_cast<FPClassTest>(RHS->getZExtValue());
+  FPClassTest Category = static_cast<FPClassTest>(RHSC);
   return getDataClassTest(LHS, Category, Dl, DAG, Subtarget);
 }
 

diff  --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index a102dda1b22c2e..48ca7b74384c61 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -831,8 +831,7 @@ void RISCVDAGToDAGISel::selectSF_VC_X_SE(SDNode *Node) {
          "Unexpected vsetvli intrinsic");
 
   // imm, imm, imm, simm5/scalar, sew, log2lmul, vl
-  auto *SewSDNode = cast<ConstantSDNode>(Node->getOperand(6));
-  unsigned Log2SEW = Log2_32(SewSDNode->getZExtValue());
+  unsigned Log2SEW = Log2_32(Node->getConstantOperandVal(6));
   SDValue SEWOp =
       CurDAG->getTargetConstant(Log2SEW, DL, Subtarget->getXLenVT());
   SmallVector<SDValue, 8> Operands = {Node->getOperand(2), Node->getOperand(3),