[llvm] 6754b54 - [X86][NFC] AnalyzeBranchImpl -> analyzeBranchImpl and remove duplicated comments in X86InstrInfo.h
Shengchen Kan via llvm-commits
llvm-commits at lists.llvm.org
Sat Jan 27 17:56:44 PST 2024
Author: Shengchen Kan
Date: 2024-01-28T09:54:31+08:00
New Revision: 6754b5428e7ddb278f03b23e8306f3d5936373e1
URL: https://github.com/llvm/llvm-project/commit/6754b5428e7ddb278f03b23e8306f3d5936373e1
DIFF: https://github.com/llvm/llvm-project/commit/6754b5428e7ddb278f03b23e8306f3d5936373e1.diff
LOG: [X86][NFC] AnalyzeBranchImpl -> analyzeBranchImpl and remove duplicated comments in X86InstrInfo.h
Added:
Modified:
llvm/lib/Target/X86/X86InstrInfo.cpp
llvm/lib/Target/X86/X86InstrInfo.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 6f08ed74d7ec61..eb9e5ca7ed470f 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -3617,7 +3617,7 @@ static MachineBasicBlock *getFallThroughMBB(MachineBasicBlock *MBB,
return FallthroughBB;
}
-bool X86InstrInfo::AnalyzeBranchImpl(
+bool X86InstrInfo::analyzeBranchImpl(
MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
SmallVectorImpl<MachineOperand> &Cond,
SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
@@ -3750,7 +3750,7 @@ bool X86InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify) const {
SmallVector<MachineInstr *, 4> CondBranches;
- return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
+ return analyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
}
static int getJumpTableIndexFromAddr(const MachineInstr &MI) {
@@ -3819,7 +3819,7 @@ bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB,
SmallVector<MachineOperand, 4> Cond;
SmallVector<MachineInstr *, 4> CondBranches;
- if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
+ if (analyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
AllowModify))
return true;
diff --git a/llvm/lib/Target/X86/X86InstrInfo.h b/llvm/lib/Target/X86/X86InstrInfo.h
index af98bb12c5c2fa..0cb69050656109 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.h
+++ b/llvm/lib/Target/X86/X86InstrInfo.h
@@ -155,7 +155,7 @@ class X86InstrInfo final : public X86GenInstrInfo {
virtual void anchor();
- bool AnalyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
+ bool analyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB,
SmallVectorImpl<MachineOperand> &Cond,
SmallVectorImpl<MachineInstr *> &CondBranches,
@@ -417,12 +417,11 @@ class X86InstrInfo final : public X86GenInstrInfo {
/// (or a subreg operand that feeds a store).
bool isSubregFoldable() const override { return true; }
- /// foldMemoryOperand - If this target supports it, fold a load or store of
- /// the specified stack slot into the specified machine instruction for the
- /// specified operand(s). If this is possible, the target should perform the
- /// folding and return true, otherwise it should return false. If it folds
- /// the instruction, it is likely that the MachineInstruction the iterator
- /// references has been changed.
+ /// Fold a load or store of the specified stack slot into the specified
+ /// machine instruction for the specified operand(s). If folding happens, it
+ /// is likely that the referenced instruction has been changed.
+ ///
+ /// \returns true on success.
MachineInstr *
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
ArrayRef<unsigned> Ops,
@@ -430,17 +429,13 @@ class X86InstrInfo final : public X86GenInstrInfo {
LiveIntervals *LIS = nullptr,
VirtRegMap *VRM = nullptr) const override;
- /// foldMemoryOperand - Same as the previous version except it allows folding
- /// of any load and store from / to any address, not just from a specific
- /// stack slot.
+ /// Same as the previous version except it allows folding of any load and
+ /// store from / to any address, not just from a specific stack slot.
MachineInstr *foldMemoryOperandImpl(
MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
LiveIntervals *LIS = nullptr) const override;
- /// unfoldMemoryOperand - Separate a single instruction which folded a load or
- /// a store or a load and a store into two or more instruction. If this is
- /// possible, returns true as well as the new instructions by reference.
bool
unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg,
bool UnfoldLoad, bool UnfoldStore,
@@ -449,39 +444,28 @@ class X86InstrInfo final : public X86GenInstrInfo {
bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
SmallVectorImpl<SDNode *> &NewNodes) const override;
- /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
- /// instruction after load / store are unfolded from an instruction of the
- /// specified opcode. It returns zero if the specified unfolding is not
- /// possible. If LoadRegIndex is non-null, it is filled in with the operand
- /// index of the operand which will hold the register holding the loaded
- /// value.
unsigned
getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore,
unsigned *LoadRegIndex = nullptr) const override;
- /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
- /// to determine if two loads are loading from the same base address. It
- /// should only return true if the base pointers are the same and the
- /// only
diff erences between the two addresses are the offset. It also returns
- /// the offsets by reference.
bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
int64_t &Offset2) const override;
- /// isSchedulingBoundary - Overrides the isSchedulingBoundary from
- /// Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR
- /// intructions and prevent it from being re-scheduled.
+ /// Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to
+ /// make it capable of identifying ENDBR intructions and prevent it from being
+ /// re-scheduled.
bool isSchedulingBoundary(const MachineInstr &MI,
const MachineBasicBlock *MBB,
const MachineFunction &MF) const override;
- /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
- /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
- /// should be scheduled togther. On some targets if two loads are loading from
- /// addresses in the same cache line, it's better if they are scheduled
- /// together. This function takes two integers that represent the load offsets
- /// from the common base address. It returns true if it decides it's desirable
- /// to schedule the two loads together. "NumLoads" is the number of loads that
- /// have already been scheduled after Load1.
+ /// This is a used by the pre-regalloc scheduler to determine (in conjunction
+ /// with areLoadsFromSameBasePtr) if two loads should be scheduled togther. On
+ /// some targets if two loads are loading from addresses in the same cache
+ /// line, it's better if they are scheduled together. This function takes two
+ /// integers that represent the load offsets from the common base address. It
+ /// returns true if it decides it's desirable to schedule the two loads
+ /// together. "NumLoads" is the number of loads that have already been
+ /// scheduled after Load1.
bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1,
int64_t Offset2,
unsigned NumLoads) const override;
@@ -494,8 +478,6 @@ class X86InstrInfo final : public X86GenInstrInfo {
bool
reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
- /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
- /// instruction that defines the specified register class.
bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
/// True if MI has a condition code def, e.g. EFLAGS, that is
@@ -552,35 +534,22 @@ class X86InstrInfo final : public X86GenInstrInfo {
MachineInstr &NewMI1,
MachineInstr &NewMI2) const override;
- /// analyzeCompare - For a comparison instruction, return the source registers
- /// in SrcReg and SrcReg2 if having two register operands, and the value it
- /// compares against in CmpValue. Return true if the comparison instruction
- /// can be analyzed.
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
Register &SrcReg2, int64_t &CmpMask,
int64_t &CmpValue) const override;
- /// optimizeCompareInstr - Check if there exists an earlier instruction that
- /// operates on the same source operands and sets flags in the same way as
- /// Compare; remove Compare if possible.
+ /// Check if there exists an earlier instruction that operates on the same
+ /// source operands and sets eflags in the same way as CMP and remove CMP if
+ /// possible.
bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
const MachineRegisterInfo *MRI) const override;
- /// optimizeLoadInstr - Try to remove the load by folding it to a register
- /// operand at the use. We fold the load instructions if and only if the
- /// def and use are in the same BB. We only look at one load and see
- /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
- /// defined by the load we are trying to fold. DefMI returns the machine
- /// instruction that defines FoldAsLoadDefReg, and the function returns
- /// the machine instruction generated due to folding.
MachineInstr *optimizeLoadInstr(MachineInstr &MI,
const MachineRegisterInfo *MRI,
Register &FoldAsLoadDefReg,
MachineInstr *&DefMI) const override;
- /// Reg is known to be defined by a move immediate instruction, try to fold
- /// the immediate into the use instruction.
bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
MachineRegisterInfo *MRI) const override;
@@ -624,32 +593,13 @@ class X86InstrInfo final : public X86GenInstrInfo {
describeLoadedValue(const MachineInstr &MI, Register Reg) const override;
protected:
- /// Commutes the operands in the given instruction by changing the operands
- /// order and/or changing the instruction's opcode and/or the immediate value
- /// operand.
- ///
- /// The arguments 'CommuteOpIdx1' and 'CommuteOpIdx2' specify the operands
- /// to be commuted.
- ///
- /// Do not call this method for a non-commutable instruction or
- /// non-commutable operands.
- /// Even though the instruction is commutable, the method may still
- /// fail to commute the operands, null pointer is returned in such cases.
MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
unsigned CommuteOpIdx1,
unsigned CommuteOpIdx2) const override;
- /// If the specific machine instruction is a instruction that moves/copies
- /// value from one register to another register return destination and source
- /// registers as machine operands.
std::optional<DestSourcePair>
isCopyInstrImpl(const MachineInstr &MI) const override;
- /// Return true when there is potentially a faster code sequence for an
- /// instruction chain ending in \p Root. All potential patterns are listed in
- /// the \p Pattern vector. Pattern should be sorted in priority order since
- /// the pattern evaluator stops checking as soon as it finds a faster
- /// sequence.
bool
getMachineCombinerPatterns(MachineInstr &Root,
SmallVectorImpl<MachineCombinerPattern> &Patterns,
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