[llvm] [JITLink][AArch32] Add TableGen Backend for Instr Encodings (PR #76996)

[Eymen Ünay via llvm-commits]

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@@ -212,19 +272,18 @@ template <> struct FixupInfo<Arm_Call> : public FixupInfoArmBranch {
   static constexpr uint32_t BitBlx = 0x10000000;
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eymay wrote:

Here is my attempt at integrating the TableGen info of branch instructions with our bit level info. I realized as we diverge more from TableGen in terms of information, it gets harder to inspect and make sense of the resulting encodings. I plan to revert this branch specific TableGen integration since more complexity is added compared to simply using the previous values. 

https://github.com/llvm/llvm-project/pull/76996