[llvm] [AMDGPU] Speed up SIRegisterInfo::getReservedRegs (PR #79610)

[Jay Foad via llvm-commits]

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@@ -693,20 +699,29 @@ BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
     }
   }
 
-  for (unsigned i = MaxNumVGPRs; i < TotalNumVGPRs; ++i) {
-    unsigned Reg = AMDGPU::VGPR_32RegClass.getRegister(i);
-    reserveRegisterTuples(Reserved, Reg);
+  for (const TargetRegisterClass *RC : regclasses()) {
+    if (RC->isBaseClass() && isVGPRClass(RC)) {
+      unsigned NumRegs = divideCeil(getRegSizeInBits(*RC), 32);
+      for (MCPhysReg Reg : *RC) {
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jayfoad wrote:

It would need adjusting for the Aligned classes. And in general I wasn't sure whether iterating RC is guaranteed to give you registers in order, and does that guarantee that HWRegIndex will also be in order?

https://github.com/llvm/llvm-project/pull/79610