[llvm] [AMDGPU] Speed up SIRegisterInfo::getReservedRegs (PR #79610)

[Jay Foad via llvm-commits]

jayfoad wrote:

> reserveRegisterTuples is slow because it uses MCRegAliasIterator and
> hence ends up reserving the same aliased registers many times. This
> patch changes getReservedRegs not to use it for reserving SGPRs, VGPRs
> and AGPRs. Instead it iterates through base register classes, which
> should come closer to reserving each register once only.

VGPR tuples still appear in more than one base class because we mark "Aligned" classes as base classes, as well as the normal (unaligned) classes. I feel this is a mistake, and I might try to change it, but that would be a different patch of course.

https://github.com/llvm/llvm-project/pull/79610