[llvm] [AArch64] Use DAG->isAddLike in add_and_or_is_add (PR #79563)

[David Green via llvm-commits]

https://github.com/davemgreen created https://github.com/llvm/llvm-project/pull/79563

This allows it to work with disjoint or's as well as computing the known bits.


>From c00bd76a7a3953cd433ce02007de7fdeb7eb6fc0 Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Fri, 26 Jan 2024 09:40:29 +0000
Subject: [PATCH 1/2] [AArch64] Add a test for disjoint or ashr fold. NFC

---
 llvm/test/CodeGen/AArch64/shift-accumulate.ll | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/llvm/test/CodeGen/AArch64/shift-accumulate.ll b/llvm/test/CodeGen/AArch64/shift-accumulate.ll
index 2ca6c73d3b83192..cc96aabbb33a107 100644
--- a/llvm/test/CodeGen/AArch64/shift-accumulate.ll
+++ b/llvm/test/CodeGen/AArch64/shift-accumulate.ll
@@ -174,3 +174,14 @@ define <2 x i64> @usra_with_movi_v2i64(<16 x i8> %0, <16 x i8> %1) {
   %7 = or <2 x i64> %6, %5
   ret <2 x i64> %7
 }
+
+define <4 x i16> @usra_v4i16_disjointor(<4 x i16> %a) {
+; CHECK-LABEL: usra_v4i16_disjointor:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ushr v1.4h, v0.4h, #7
+; CHECK-NEXT:    orr v0.8b, v1.8b, v0.8b
+; CHECK-NEXT:    ret
+  %s = lshr <4 x i16> %a, <i16 7, i16 7, i16 7, i16 7>
+  %o = or disjoint <4 x i16> %s, %a
+  ret <4 x i16> %o
+}

>From cd55c160055867667a5a9756e3a7079521387e3f Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Fri, 26 Jan 2024 09:44:04 +0000
Subject: [PATCH 2/2] [AArch64] Use DAG->isAddLike in add_and_or_is_add

This allows it to work with disjoint or's as well as computing the known bits.
---
 llvm/lib/Target/AArch64/AArch64InstrInfo.td   | 2 +-
 llvm/test/CodeGen/AArch64/shift-accumulate.ll | 3 +--
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 03baa7497615e3d..678c69f968f6b64 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -899,7 +899,7 @@ def add_and_or_is_add : PatFrags<(ops node:$lhs, node:$rhs),
                          [(add node:$lhs, node:$rhs), (or node:$lhs, node:$rhs)],[{
    if (N->getOpcode() == ISD::ADD)
      return true;
-   return CurDAG->haveNoCommonBitsSet(N->getOperand(0), N->getOperand(1));
+   return CurDAG->isADDLike(SDValue(N,0));
 }]> {
   let GISelPredicateCode = [{
      // Only handle G_ADD for now. FIXME. build capability to compute whether
diff --git a/llvm/test/CodeGen/AArch64/shift-accumulate.ll b/llvm/test/CodeGen/AArch64/shift-accumulate.ll
index cc96aabbb33a107..1daa4ea397c8371 100644
--- a/llvm/test/CodeGen/AArch64/shift-accumulate.ll
+++ b/llvm/test/CodeGen/AArch64/shift-accumulate.ll
@@ -178,8 +178,7 @@ define <2 x i64> @usra_with_movi_v2i64(<16 x i8> %0, <16 x i8> %1) {
 define <4 x i16> @usra_v4i16_disjointor(<4 x i16> %a) {
 ; CHECK-LABEL: usra_v4i16_disjointor:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ushr v1.4h, v0.4h, #7
-; CHECK-NEXT:    orr v0.8b, v1.8b, v0.8b
+; CHECK-NEXT:    usra v0.4h, v0.4h, #7
 ; CHECK-NEXT:    ret
   %s = lshr <4 x i16> %a, <i16 7, i16 7, i16 7, i16 7>
   %o = or disjoint <4 x i16> %s, %a