[llvm] [ARM][NEON] Add constraint to vld2 Odd/Even Pseudo instructions. (PR #79287)

[Alfie Richards via llvm-commits]

AlfieRichardsArm wrote:

Caveat that I'm relatively new to LLVM work and this code base.

There are multiple reasons for the special cases IMO and none of them bugs (but maybe outdated design choices). The encoding for VLDQQPseudo is intended to be more general than for the Q/QQQQ Pseudos as it is used in more cases, but that leads to some extra complexity and not being able to use it in this case.

In this case I think that VLD2DUPq8OddPseudo and VLD2DUPq8EvenPseudo have this need for glue between them that doesn't fit into the abstractions in VLDQQPseudo.

I am happy to rename, however I don't follow your point about the input register. By my interpretation the "input" register is there solely to allow the constraint that Odd and Even use the same output register range? 

https://github.com/llvm/llvm-project/pull/79287