[llvm] [AIX][TLS] Optimize the small local-exec access sequence for non-zero offsets (PR #71485)

[Amy Kwan via llvm-commits]

================
@@ -1523,19 +1558,50 @@ void PPCAsmPrinter::emitInstruction(const MachineInstr *MI) {
     EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::EnforceIEIO));
     return;
   }
+  case PPC::LBZ:
----------------
amy-kwan wrote:

I could be mistaken, but to my knowledge, similar to the previous comment I added, I believe `PPC::LBZ` and these other 32-bit version of instructions can be selected on a 64-bit target.

On a 32-bit target for `PPC::LBZ`, it will go into this case but it should end up in this case and break out to process the instruction normally.
```
    // Now process the instruction normally.
    break;
```
The part you mentioned:
```
if (Flag == PPCII::MO_TPREL_FLAG ||
    Flag == PPCII::MO_GOT_TPREL_PCREL_FLAG ||
    Flag == PPCII::MO_TPREL_PCREL_FLAG) {
  assert(HasAIXSmallLocalExecTLS &&
               "addi, or load/stores with thread-pointer only expected with "
               "local-exec small TLS");
```
Should happen for 64-bit targets, and that assert should be true for 64-bit only because we have restricted the aix-small-local-exec-tls feature to 64-bit only in https://github.com/llvm/llvm-project/commit/b1922e55ab3b35dff99238fd0b74be00df0472e7 and in https://github.com/llvm/llvm-project/commit/8bdbee8aaa76960c54cd0071455b92e9d60d8966.

https://github.com/llvm/llvm-project/pull/71485