[llvm] [AIX][TLS] Optimize the small local-exec access sequence for non-zero offsets (PR #71485)

[Amy Kwan via llvm-commits]

================
@@ -1523,19 +1558,50 @@ void PPCAsmPrinter::emitInstruction(const MachineInstr *MI) {
     EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::EnforceIEIO));
     return;
   }
+  case PPC::LBZ:
----------------
amy-kwan wrote:

Yeah, I found that these versions (the 32-bit, non-`8` versions of the instructions) can still appear.

They can get selected if one of their the preceding operands are 32-bit versions instructions. For example, below is a segment of the SDAG where we can select both `STB` and `STB8`. The `STB` gets selected since one of the operands are an `ADDI`.
```
. . . 
          t85: i64 = LI8 TargetConstant:i64<10>
        t62: ch = STB8<Mem:(store (s8) into %ir.0, !tbaa !3)> t85, TargetGlobalTLSAddress:i64<ptr @IThreadLocalVarInit> 0 [TF=7], Register:i64 $x13, t0
          t84: i64 = LI8 TargetConstant:i64<-46>
        t74: ch = STB8<Mem:(store (s8) into %ir.arrayidx1, !tbaa !3)> t84, TargetGlobalTLSAddress:i64<ptr @IThreadLocalVarInit> + 10 [TF=7], Register:i64 $x13, t0
          t60: i32 = ADDI t55, TargetConstant:i32<2>
        t61: ch = STB<Mem:(store (s8) into %ir.arrayidx3, !tbaa !3)> t60, TargetGlobalTLSAddress:i64<ptr @IThreadLocalVarInit> + 20 [TF=7], Register:i64 $x13, t0
. . .
```

https://github.com/llvm/llvm-project/pull/71485