[llvm] [ARM] Add pass for handling undef early-clobber values (PR #77770)
Jack Styles via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 24 01:54:05 PST 2024
https://github.com/Stylie777 updated https://github.com/llvm/llvm-project/pull/77770
>From 357932babf858d8d2d7dd05c975505ada3b9e05f Mon Sep 17 00:00:00 2001
From: Jack Styles <jack.styles at arm.com>
Date: Tue, 23 Jan 2024 07:38:59 +0000
Subject: [PATCH 1/2] [CodeGen] Convert RISCV Init Undef pass to support any
architecture
Currently this pass is designed for RISC-V only, however this is
not the only architecture with the bug reported in issue #50157.
We can convert the exisiting pass to be generic, using some of the
existing Parent classes rather than RISC-V specific classes to
bring the same functionality to other Architectures.
The pass has been refactored, removing the RISC-V specific functions
and data-types and replacing them with datatypes that will support
all architectures and virtual functions in the respecitive classes
that allow support for the pass to be added. By default, this pass
will not run on on all architectures, only those that have the
`hasVectorInstruction` function impletmented. This commit will only
refactor the exisiting code and add the pass in as a CodeGen pass rather
than target specific. To add support for other architectures, this should
be done in new, following commits.
This will allow for the pass to be used by any architecture. With the
correct overriding functions, other architectures can be supported
to provide the same functionality as was added to fix issue that
was reported in Issue #50157.
This is still a temporary measure, and a better more permenant fix
should be found, but for the time being this will allow for the
correct early-clobber contraint to be followed when defined in
vector instructions.
---
llvm/include/llvm/CodeGen/Passes.h | 4 +
llvm/include/llvm/CodeGen/TargetInstrInfo.h | 18 +++
.../llvm/CodeGen/TargetSubtargetInfo.h | 9 ++
llvm/include/llvm/InitializePasses.h | 1 +
llvm/lib/CodeGen/CMakeLists.txt | 1 +
.../InitUndef.cpp} | 129 +++++++-----------
llvm/lib/CodeGen/TargetPassConfig.cpp | 2 +
llvm/lib/Target/RISCV/CMakeLists.txt | 1 -
llvm/lib/Target/RISCV/RISCV.h | 4 -
llvm/lib/Target/RISCV/RISCVInstrInfo.h | 40 ++++++
llvm/lib/Target/RISCV/RISCVSubtarget.h | 4 +-
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 10 +-
.../secondary/llvm/lib/Target/RISCV/BUILD.gn | 1 -
13 files changed, 128 insertions(+), 96 deletions(-)
rename llvm/lib/{Target/RISCV/RISCVRVVInitUndef.cpp => CodeGen/InitUndef.cpp} (65%)
diff --git a/llvm/include/llvm/CodeGen/Passes.h b/llvm/include/llvm/CodeGen/Passes.h
index bbfb8a0dbe26a42..84fadbd20d9650e 100644
--- a/llvm/include/llvm/CodeGen/Passes.h
+++ b/llvm/include/llvm/CodeGen/Passes.h
@@ -196,6 +196,8 @@ namespace llvm {
/// This pass reads flow sensitive profile.
extern char &MIRProfileLoaderPassID;
+ extern char &InitUndefID;
+
/// FastRegisterAllocation Pass - This pass register allocates as fast as
/// possible. It is best suited for debug code where live ranges are short.
///
@@ -600,6 +602,8 @@ namespace llvm {
/// Lowers KCFI operand bundles for indirect calls.
FunctionPass *createKCFIPass();
+
+ FunctionPass *createInitUndefPass();
} // End llvm namespace
#endif
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index a113100f04e6211..80c7b79e0121b16 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -2223,6 +2223,24 @@ class TargetInstrInfo : public MCInstrInfo {
llvm_unreachable("unknown number of operands necessary");
}
+ virtual unsigned getUndefInitOpcode(unsigned RegClassID) const {
+ (void)RegClassID;
+
+ llvm_unreachable("Unexpected register class.");
+ }
+
+ virtual const TargetRegisterClass *getVRLargestSuperClass(const TargetRegisterClass *RC) const {
+ llvm_unreachable("Unexpected target register class.");
+ }
+
+ virtual bool isVectorRegClass(const TargetRegisterClass *RC) const {
+ llvm_unreachable("Unexpected Register or MachineRegisterInfo");
+}
+
+ virtual unsigned getNoRegisterValue() const {
+ llvm_unreachable("Unexpected target register class.");
+ }
+
private:
mutable std::unique_ptr<MIRFormatter> Formatter;
unsigned CallFrameSetupOpcode, CallFrameDestroyOpcode;
diff --git a/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h b/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
index a064dec7d8ab38c..ef5e5fb7b0d916d 100644
--- a/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
@@ -327,6 +327,15 @@ class TargetSubtargetInfo : public MCSubtargetInfo {
/// Get the list of MacroFusion predicates.
virtual std::vector<MacroFusionPredTy> getMacroFusions() const { return {}; };
+
+ // hasVectorInstructions is used to determine if an architecture supports
+ // vector instructions in relation to Vector CodeGen. By default, it is
+ // assumed that it will not support Vector Instructions, with architecture
+ // specific overrides providing the information where they are implemented.
+ // This was originally used in RISC-V's Init Undef pass but has been moved to
+ // be a virtual function when the pass was refactored to support multiple
+ // architectures.
+ virtual bool hasVectorInstructions() const { return false; }
};
} // end namespace llvm
diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h
index 3db639a68724077..929176998d05270 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -301,6 +301,7 @@ void initializeTLSVariableHoistLegacyPassPass(PassRegistry &);
void initializeTwoAddressInstructionPassPass(PassRegistry&);
void initializeTypeBasedAAWrapperPassPass(PassRegistry&);
void initializeTypePromotionLegacyPass(PassRegistry&);
+void initializeInitUndefPass(PassRegistry&);
void initializeUniformityInfoWrapperPassPass(PassRegistry &);
void initializeUnifyLoopExitsLegacyPassPass(PassRegistry &);
void initializeUnpackMachineBundlesPass(PassRegistry&);
diff --git a/llvm/lib/CodeGen/CMakeLists.txt b/llvm/lib/CodeGen/CMakeLists.txt
index df2d1831ee5fdbf..ca02c0749de88c6 100644
--- a/llvm/lib/CodeGen/CMakeLists.txt
+++ b/llvm/lib/CodeGen/CMakeLists.txt
@@ -88,6 +88,7 @@ add_llvm_component_library(LLVMCodeGen
IfConversion.cpp
ImplicitNullChecks.cpp
IndirectBrExpandPass.cpp
+ InitUndef.cpp
InlineSpiller.cpp
InterferenceCache.cpp
InterleavedAccessPass.cpp
diff --git a/llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp b/llvm/lib/CodeGen/InitUndef.cpp
similarity index 65%
rename from llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp
rename to llvm/lib/CodeGen/InitUndef.cpp
index 735fc1350c00915..c358ca49c4193cf 100644
--- a/llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp
+++ b/llvm/lib/CodeGen/InitUndef.cpp
@@ -1,4 +1,4 @@
-//===- RISCVRVVInitUndef.cpp - Initialize undef vector value to pseudo ----===//
+//===- InitUndef.cpp - Initialize undef vector value to pseudo ----===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
@@ -7,22 +7,21 @@
//===----------------------------------------------------------------------===//
//
// This file implements a function pass that initializes undef vector value to
-// temporary pseudo instruction and remove it in expandpseudo pass to prevent
-// register allocation resulting in a constraint violated result for vector
-// instruction. It also rewrites the NoReg tied operand back to an
-// IMPLICIT_DEF.
+// temporary pseudo instruction to prevent register allocation resulting in a
+// constraint violated result for vector instructions. It also rewrites the
+// NoReg tied operand back to an IMPLICIT_DEF.
//
-// RISC-V vector instruction has register overlapping constraint for certain
-// instructions, and will cause illegal instruction trap if violated, we use
-// early clobber to model this constraint, but it can't prevent register
-// allocator allocated same or overlapped if the input register is undef value,
-// so convert IMPLICIT_DEF to temporary pseudo instruction and remove it later
-// could prevent that happen, it's not best way to resolve this, and it might
+// Certain vector instructions have register overlapping constraints, and
+// will cause illegal instruction trap if violated, we use early clobber to
+// model this constraint, but it can't prevent register allocator allocating
+// same or overlapped if the input register is undef value, so convert
+// IMPLICIT_DEF to temporary pseudo instruction and remove it later could
+// prevent that happen, it's not best way to resolve this, and it might
// change the order of program or increase the register pressure, so ideally we
// should model the constraint right, but before we model the constraint right,
// it's the only way to prevent that happen.
//
-// When we enable the subregister liveness option, it will also trigger same
+// When we enable the subregister liveness option, it will also trigger the same
// issue due to the partial of register is undef. If we pseudoinit the whole
// register, then it will generate redundant COPY instruction. Currently, it
// will generate INSERT_SUBREG to make sure the whole register is occupied
@@ -39,23 +38,28 @@
//
//===----------------------------------------------------------------------===//
-#include "RISCV.h"
-#include "RISCVSubtarget.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/DetectDeadLanes.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
+#include "llvm/InitializePasses.h"
+#include "llvm/Pass.h"
+
using namespace llvm;
-#define DEBUG_TYPE "riscv-init-undef"
-#define RISCV_INIT_UNDEF_NAME "RISC-V init undef pass"
+#define DEBUG_TYPE "init-undef"
+#define INIT_UNDEF_NAME "init-undef-pass"
namespace {
-class RISCVInitUndef : public MachineFunctionPass {
+class InitUndef : public MachineFunctionPass {
const TargetInstrInfo *TII;
MachineRegisterInfo *MRI;
- const RISCVSubtarget *ST;
+ const TargetSubtargetInfo *ST;
const TargetRegisterInfo *TRI;
// Newly added vregs, assumed to be fully rewritten
@@ -65,7 +69,7 @@ class RISCVInitUndef : public MachineFunctionPass {
public:
static char ID;
- RISCVInitUndef() : MachineFunctionPass(ID) {}
+ InitUndef() : MachineFunctionPass(ID) {}
bool runOnMachineFunction(MachineFunction &MF) override;
void getAnalysisUsage(AnalysisUsage &AU) const override {
@@ -73,14 +77,11 @@ class RISCVInitUndef : public MachineFunctionPass {
MachineFunctionPass::getAnalysisUsage(AU);
}
- StringRef getPassName() const override { return RISCV_INIT_UNDEF_NAME; }
+ StringRef getPassName() const override { return INIT_UNDEF_NAME; }
private:
bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB,
const DeadLaneDetector &DLD);
- bool isVectorRegClass(const Register R);
- const TargetRegisterClass *
- getVRLargestSuperClass(const TargetRegisterClass *RC) const;
bool handleSubReg(MachineFunction &MF, MachineInstr &MI,
const DeadLaneDetector &DLD);
bool fixupIllOperand(MachineInstr *MI, MachineOperand &MO);
@@ -89,45 +90,9 @@ class RISCVInitUndef : public MachineFunctionPass {
} // end anonymous namespace
-char RISCVInitUndef::ID = 0;
-INITIALIZE_PASS(RISCVInitUndef, DEBUG_TYPE, RISCV_INIT_UNDEF_NAME, false, false)
-char &llvm::RISCVInitUndefID = RISCVInitUndef::ID;
-
-const TargetRegisterClass *
-RISCVInitUndef::getVRLargestSuperClass(const TargetRegisterClass *RC) const {
- if (RISCV::VRM8RegClass.hasSubClassEq(RC))
- return &RISCV::VRM8RegClass;
- if (RISCV::VRM4RegClass.hasSubClassEq(RC))
- return &RISCV::VRM4RegClass;
- if (RISCV::VRM2RegClass.hasSubClassEq(RC))
- return &RISCV::VRM2RegClass;
- if (RISCV::VRRegClass.hasSubClassEq(RC))
- return &RISCV::VRRegClass;
- return RC;
-}
-
-bool RISCVInitUndef::isVectorRegClass(const Register R) {
- const TargetRegisterClass *RC = MRI->getRegClass(R);
- return RISCV::VRRegClass.hasSubClassEq(RC) ||
- RISCV::VRM2RegClass.hasSubClassEq(RC) ||
- RISCV::VRM4RegClass.hasSubClassEq(RC) ||
- RISCV::VRM8RegClass.hasSubClassEq(RC);
-}
-
-static unsigned getUndefInitOpcode(unsigned RegClassID) {
- switch (RegClassID) {
- case RISCV::VRRegClassID:
- return RISCV::PseudoRVVInitUndefM1;
- case RISCV::VRM2RegClassID:
- return RISCV::PseudoRVVInitUndefM2;
- case RISCV::VRM4RegClassID:
- return RISCV::PseudoRVVInitUndefM4;
- case RISCV::VRM8RegClassID:
- return RISCV::PseudoRVVInitUndefM8;
- default:
- llvm_unreachable("Unexpected register class.");
- }
-}
+char InitUndef::ID = 0;
+INITIALIZE_PASS(InitUndef, DEBUG_TYPE, INIT_UNDEF_NAME, false, false)
+char &llvm::InitUndefID = InitUndef::ID;
static bool isEarlyClobberMI(MachineInstr &MI) {
return llvm::any_of(MI.defs(), [](const MachineOperand &DefMO) {
@@ -143,7 +108,7 @@ static bool findImplictDefMIFromReg(Register Reg, MachineRegisterInfo *MRI) {
return false;
}
-bool RISCVInitUndef::handleReg(MachineInstr *MI) {
+bool InitUndef::handleReg(MachineInstr *MI) {
bool Changed = false;
for (auto &UseMO : MI->uses()) {
if (!UseMO.isReg())
@@ -152,7 +117,7 @@ bool RISCVInitUndef::handleReg(MachineInstr *MI) {
continue;
if (!UseMO.getReg().isVirtual())
continue;
- if (!isVectorRegClass(UseMO.getReg()))
+ if (!TII->isVectorRegClass(MRI->getRegClass(UseMO.getReg())))
continue;
if (UseMO.isUndef() || findImplictDefMIFromReg(UseMO.getReg(), MRI))
@@ -161,7 +126,7 @@ bool RISCVInitUndef::handleReg(MachineInstr *MI) {
return Changed;
}
-bool RISCVInitUndef::handleSubReg(MachineFunction &MF, MachineInstr &MI,
+bool InitUndef::handleSubReg(MachineFunction &MF, MachineInstr &MI,
const DeadLaneDetector &DLD) {
bool Changed = false;
@@ -183,7 +148,7 @@ bool RISCVInitUndef::handleSubReg(MachineFunction &MF, MachineInstr &MI,
continue;
const TargetRegisterClass *TargetRegClass =
- getVRLargestSuperClass(MRI->getRegClass(Reg));
+ TII->getVRLargestSuperClass(MRI->getRegClass(Reg));
LaneBitmask NeedDef = Info.UsedLanes & ~Info.DefinedLanes;
@@ -202,11 +167,11 @@ bool RISCVInitUndef::handleSubReg(MachineFunction &MF, MachineInstr &MI,
Register LatestReg = Reg;
for (auto ind : SubRegIndexNeedInsert) {
Changed = true;
- const TargetRegisterClass *SubRegClass =
- getVRLargestSuperClass(TRI->getSubRegisterClass(TargetRegClass, ind));
+ const TargetRegisterClass *SubRegClass = TII->getVRLargestSuperClass(
+ TRI->getSubRegisterClass(TargetRegClass, ind));
Register TmpInitSubReg = MRI->createVirtualRegister(SubRegClass);
BuildMI(*MI.getParent(), &MI, MI.getDebugLoc(),
- TII->get(getUndefInitOpcode(SubRegClass->getID())),
+ TII->get(TII->getUndefInitOpcode(SubRegClass->getID())),
TmpInitSubReg);
Register NewReg = MRI->createVirtualRegister(TargetRegClass);
BuildMI(*MI.getParent(), &MI, MI.getDebugLoc(),
@@ -223,15 +188,15 @@ bool RISCVInitUndef::handleSubReg(MachineFunction &MF, MachineInstr &MI,
return Changed;
}
-bool RISCVInitUndef::fixupIllOperand(MachineInstr *MI, MachineOperand &MO) {
+bool InitUndef::fixupIllOperand(MachineInstr *MI, MachineOperand &MO) {
LLVM_DEBUG(
- dbgs() << "Emitting PseudoRVVInitUndef for implicit vector register "
+ dbgs() << "Emitting PseudoInitUndef Instruction for implicit vector register "
<< MO.getReg() << '\n');
const TargetRegisterClass *TargetRegClass =
- getVRLargestSuperClass(MRI->getRegClass(MO.getReg()));
- unsigned Opcode = getUndefInitOpcode(TargetRegClass->getID());
+ TII->getVRLargestSuperClass(MRI->getRegClass(MO.getReg()));
+ unsigned Opcode = TII->getUndefInitOpcode(TargetRegClass->getID());
Register NewReg = MRI->createVirtualRegister(TargetRegClass);
BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII->get(Opcode), NewReg);
MO.setReg(NewReg);
@@ -240,7 +205,7 @@ bool RISCVInitUndef::fixupIllOperand(MachineInstr *MI, MachineOperand &MO) {
return true;
}
-bool RISCVInitUndef::processBasicBlock(MachineFunction &MF,
+bool InitUndef::processBasicBlock(MachineFunction &MF,
MachineBasicBlock &MBB,
const DeadLaneDetector &DLD) {
bool Changed = false;
@@ -252,7 +217,7 @@ bool RISCVInitUndef::processBasicBlock(MachineFunction &MF,
unsigned UseOpIdx;
if (MI.getNumDefs() != 0 && MI.isRegTiedToUseOperand(0, &UseOpIdx)) {
MachineOperand &UseMO = MI.getOperand(UseOpIdx);
- if (UseMO.getReg() == RISCV::NoRegister) {
+ if (UseMO.getReg() == TII->getNoRegisterValue()) {
const TargetRegisterClass *RC =
TII->getRegClass(MI.getDesc(), UseOpIdx, TRI, MF);
Register NewDest = MRI->createVirtualRegister(RC);
@@ -275,9 +240,15 @@ bool RISCVInitUndef::processBasicBlock(MachineFunction &MF,
return Changed;
}
-bool RISCVInitUndef::runOnMachineFunction(MachineFunction &MF) {
- ST = &MF.getSubtarget<RISCVSubtarget>();
- if (!ST->hasVInstructions())
+bool InitUndef::runOnMachineFunction(MachineFunction &MF) {
+ ST = &MF.getSubtarget();
+
+ // This checks to ensure that the Subtarget being used has support for Vector
+ // Instructions. The pass will exit if this is not the case, and provides
+ // protection against unnecessary changing register definitions where this is
+ // not needed. By default hasVectorInstructions will return false, only in the
+ // Architecture specific subtarget override function can this return true.
+ if (!ST->hasVectorInstructions())
return false;
MRI = &MF.getRegInfo();
@@ -298,4 +269,4 @@ bool RISCVInitUndef::runOnMachineFunction(MachineFunction &MF) {
return Changed;
}
-FunctionPass *llvm::createRISCVInitUndefPass() { return new RISCVInitUndef(); }
+FunctionPass *llvm::createInitUndefPass() { return new InitUndef(); }
diff --git a/llvm/lib/CodeGen/TargetPassConfig.cpp b/llvm/lib/CodeGen/TargetPassConfig.cpp
index 46697480db52aa4..0fd8f73d65dd685 100644
--- a/llvm/lib/CodeGen/TargetPassConfig.cpp
+++ b/llvm/lib/CodeGen/TargetPassConfig.cpp
@@ -1424,6 +1424,8 @@ void TargetPassConfig::addFastRegAlloc() {
void TargetPassConfig::addOptimizedRegAlloc() {
addPass(&DetectDeadLanesID);
+ addPass(createInitUndefPass());
+
addPass(&ProcessImplicitDefsID);
// LiveVariables currently requires pure SSA form.
diff --git a/llvm/lib/Target/RISCV/CMakeLists.txt b/llvm/lib/Target/RISCV/CMakeLists.txt
index a0c3345ec1bbd7e..2c393101191a7d2 100644
--- a/llvm/lib/Target/RISCV/CMakeLists.txt
+++ b/llvm/lib/Target/RISCV/CMakeLists.txt
@@ -51,7 +51,6 @@ add_llvm_target(RISCVCodeGen
RISCVMoveMerger.cpp
RISCVPushPopOptimizer.cpp
RISCVRegisterInfo.cpp
- RISCVRVVInitUndef.cpp
RISCVSubtarget.cpp
RISCVTargetMachine.cpp
RISCVTargetObjectFile.cpp
diff --git a/llvm/lib/Target/RISCV/RISCV.h b/llvm/lib/Target/RISCV/RISCV.h
index 9eb18099894b217..7af543f018ccbd5 100644
--- a/llvm/lib/Target/RISCV/RISCV.h
+++ b/llvm/lib/Target/RISCV/RISCV.h
@@ -72,10 +72,6 @@ void initializeRISCVInsertWriteVXRMPass(PassRegistry &);
FunctionPass *createRISCVRedundantCopyEliminationPass();
void initializeRISCVRedundantCopyEliminationPass(PassRegistry &);
-FunctionPass *createRISCVInitUndefPass();
-void initializeRISCVInitUndefPass(PassRegistry &);
-extern char &RISCVInitUndefID;
-
FunctionPass *createRISCVMoveMergePass();
void initializeRISCVMoveMergePass(PassRegistry &);
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index 7e1d3f31180650d..43eee8b8c617e19 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -13,6 +13,7 @@
#ifndef LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H
#define LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H
+#include "RISCV.h"
#include "RISCVRegisterInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/DiagnosticInfo.h"
@@ -20,6 +21,7 @@
#define GET_INSTRINFO_HEADER
#define GET_INSTRINFO_OPERAND_ENUM
#include "RISCVGenInstrInfo.inc"
+#include "RISCVGenRegisterInfo.inc"
namespace llvm {
@@ -262,6 +264,44 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
ArrayRef<std::pair<MachineMemOperand::Flags, const char *>>
getSerializableMachineMemOperandTargetFlags() const override;
+ const TargetRegisterClass * getVRLargestSuperClass(const TargetRegisterClass *RC) const override{
+ if (RISCV::VRM8RegClass.hasSubClassEq(RC))
+ return &RISCV::VRM8RegClass;
+ if (RISCV::VRM4RegClass.hasSubClassEq(RC))
+ return &RISCV::VRM4RegClass;
+ if (RISCV::VRM2RegClass.hasSubClassEq(RC))
+ return &RISCV::VRM2RegClass;
+ if (RISCV::VRRegClass.hasSubClassEq(RC))
+ return &RISCV::VRRegClass;
+ return RC;
+ }
+
+ bool isVectorRegClass(const TargetRegisterClass *RC) const override {
+ return RISCV::VRRegClass.hasSubClassEq(RC) ||
+ RISCV::VRM2RegClass.hasSubClassEq(RC) ||
+ RISCV::VRM4RegClass.hasSubClassEq(RC) ||
+ RISCV::VRM8RegClass.hasSubClassEq(RC);
+ }
+
+ unsigned getUndefInitOpcode(unsigned RegClassID) const override {
+ switch (RegClassID) {
+ case RISCV::VRRegClassID:
+ return RISCV::PseudoRVVInitUndefM1;
+ case RISCV::VRM2RegClassID:
+ return RISCV::PseudoRVVInitUndefM2;
+ case RISCV::VRM4RegClassID:
+ return RISCV::PseudoRVVInitUndefM4;
+ case RISCV::VRM8RegClassID:
+ return RISCV::PseudoRVVInitUndefM8;
+ default:
+ llvm_unreachable("Unexpected register class.");
+ }
+ }
+
+ unsigned getNoRegisterValue() const override {
+ return RISCV::NoRegister;
+ }
+
protected:
const RISCVSubtarget &STI;
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index 2ba93764facd07d..8bc2646d6e77e21 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -202,7 +202,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
}
// Vector codegen related methods.
- bool hasVInstructions() const { return HasStdExtZve32x; }
+ bool hasVectorInstructions() const override { return HasStdExtZve32x; }
bool hasVInstructionsI64() const { return HasStdExtZve64x; }
bool hasVInstructionsF16Minimal() const { return HasStdExtZvfhmin; }
bool hasVInstructionsF16() const { return HasStdExtZvfh; }
@@ -213,7 +213,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
bool hasVInstructionsAnyF() const { return hasVInstructionsF32(); }
bool hasVInstructionsFullMultiply() const { return HasStdExtV; }
unsigned getMaxInterleaveFactor() const {
- return hasVInstructions() ? MaxInterleaveFactor : 1;
+ return hasVectorInstructions() ? MaxInterleaveFactor : 1;
}
// Returns VLEN divided by DLEN. Where DLEN is the datapath width of the
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index b4b81b545a54bbd..8b8d7ca859ddd25 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -123,7 +123,6 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
initializeRISCVInsertReadWriteCSRPass(*PR);
initializeRISCVInsertWriteVXRMPass(*PR);
initializeRISCVDAGToDAGISelPass(*PR);
- initializeRISCVInitUndefPass(*PR);
initializeRISCVMoveMergePass(*PR);
initializeRISCVPushPopOptPass(*PR);
}
@@ -397,7 +396,6 @@ class RISCVPassConfig : public TargetPassConfig {
bool addRegAssignAndRewriteOptimized() override;
void addPreRegAlloc() override;
void addPostRegAlloc() override;
- void addOptimizedRegAlloc() override;
void addFastRegAlloc() override;
};
} // namespace
@@ -572,14 +570,8 @@ void RISCVPassConfig::addPreRegAlloc() {
addPass(createRISCVInsertWriteVXRMPass());
}
-void RISCVPassConfig::addOptimizedRegAlloc() {
- insertPass(&DetectDeadLanesID, &RISCVInitUndefID);
-
- TargetPassConfig::addOptimizedRegAlloc();
-}
-
void RISCVPassConfig::addFastRegAlloc() {
- addPass(createRISCVInitUndefPass());
+ addPass(createInitUndefPass());
TargetPassConfig::addFastRegAlloc();
}
diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
index 45239649569b46d..6e1a3a9ef252cbf 100644
--- a/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
+++ b/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
@@ -123,7 +123,6 @@ static_library("LLVMRISCVCodeGen") {
"RISCVOptWInstrs.cpp",
"RISCVPostRAExpandPseudoInsts.cpp",
"RISCVPushPopOptimizer.cpp",
- "RISCVRVVInitUndef.cpp",
"RISCVRedundantCopyElimination.cpp",
"RISCVRegisterInfo.cpp",
"RISCVSubtarget.cpp",
>From 7148a248d4baf2c413a569038cad82c8fa6f813d Mon Sep 17 00:00:00 2001
From: Jack Styles <jack.styles at arm.com>
Date: Tue, 23 Jan 2024 14:55:46 +0000
Subject: [PATCH 2/2] [ARM] Add support for ARM Vector Instructions for Init
Undef Pass
For Vector Instructions within the ARM Architecture, certain
instructions have early-clobber restraints that are defined
for the instruction. However, when using the Greedy register
allocator this is ignored. To get around this, we can use
the Init Undef pass to assign a Pseudo instruction for the
registers that are early-clobber to ensure the restraint
is followed.
This adds in support for this using a new Pseudo instruction,
`PseudoARMInitUndef` which is used to ensure early-clobber
restrains are followed. The relevant overriding functions
have also been provided to ensure the architecture is
supported by the pass and the required information can be
passed to ensure that early-clobber restrains are respected.
---
llvm/lib/Target/ARM/ARMAsmPrinter.cpp | 4 ++++
llvm/lib/Target/ARM/ARMBaseInstrInfo.h | 24 +++++++++++++++++++
llvm/lib/Target/ARM/ARMInstrInfo.td | 9 +++++++
llvm/lib/Target/ARM/ARMSubtarget.h | 4 ++++
.../CodeGen/Thumb2/mve-intrinsics/vcaddq.ll | 11 +++++++++
5 files changed, 52 insertions(+)
diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
index 15cda9b9432d5f2..14bdf5db1871154 100644
--- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -2409,8 +2409,12 @@ void ARMAsmPrinter::emitInstruction(const MachineInstr *MI) {
case ARM::SEH_EpilogEnd:
ATS.emitARMWinCFIEpilogEnd();
return;
+
+ case ARM::PseudoARMInitUndef:
+ return;
}
+
MCInst TmpInst;
LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
index 6aebf3b64e8d43f..02e6b6a8a7ce2f5 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -13,13 +13,16 @@
#ifndef LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
#define LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
+#include "ARMBaseRegisterInfo.h"
#include "MCTargetDesc/ARMBaseInfo.h"
+#include "MCTargetDesc/ARMMCTargetDesc.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/IntrinsicInst.h"
#include "llvm/IR/IntrinsicsARM.h"
@@ -536,6 +539,27 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
std::optional<RegImmPair> isAddImmediate(const MachineInstr &MI,
Register Reg) const override;
+
+ unsigned getUndefInitOpcode(unsigned RegClassID) const override {
+ if(RegClassID == ARM::MQPRRegClass.getID()){
+ return ARM::PseudoARMInitUndef;
+ }
+ llvm_unreachable("Unexpected register class.");
+ }
+
+ const TargetRegisterClass *getVRLargestSuperClass(const TargetRegisterClass *RC) const override {
+ if (ARM::MQPRRegClass.hasSubClassEq(RC))
+ return &ARM::MQPRRegClass;
+ return RC;
+ }
+
+ bool isVectorRegClass(const TargetRegisterClass *RC) const override {
+ return ARM::MQPRRegClass.hasSubClassEq(RC);
+ }
+
+ unsigned getNoRegisterValue() const override{
+ return ARM::NoRegister;
+ }
};
/// Get the operands corresponding to the given \p Pred value. By default, the
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
index 812b5730875d5d4..538410699db0a9f 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -6532,3 +6532,12 @@ let isPseudo = 1 in {
let isTerminator = 1 in
def SEH_EpilogEnd : PseudoInst<(outs), (ins), NoItinerary, []>, Sched<[]>;
}
+
+
+//===----------------------------------------------------------------------===//
+// Pseudo Instructions for use when early-clobber is defined and Greedy Register
+// Allocation is used. This ensures the constraint is used properly.
+//===----------------------------------------------------------------------===//
+let isCodeGenOnly = 1, hasNoSchedulingInfo = 1 in {
+ def PseudoARMInitUndef : PseudoInst<(outs MQPR:$vd), (ins), NoItinerary, []>;
+}
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h
index 43b4123a1b55713..e089b1b5491aa18 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.h
+++ b/llvm/lib/Target/ARM/ARMSubtarget.h
@@ -277,6 +277,10 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
return &InstrInfo->getRegisterInfo();
}
+ bool hasVectorInstructions() const override {
+ return HasMVEIntegerOps || HasMVEFloatOps;
+ }
+
const CallLowering *getCallLowering() const override;
InstructionSelector *getInstructionSelector() const override;
const LegalizerInfo *getLegalizerInfo() const override;
diff --git a/llvm/test/CodeGen/Thumb2/mve-intrinsics/vcaddq.ll b/llvm/test/CodeGen/Thumb2/mve-intrinsics/vcaddq.ll
index 9bb24fc61ccef39..02234c63725360a 100644
--- a/llvm/test/CodeGen/Thumb2/mve-intrinsics/vcaddq.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-intrinsics/vcaddq.ll
@@ -699,6 +699,17 @@ entry:
ret <4 x i32> %0
}
+define arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot270_s32_undef() {
+; CHECK-LABEL: test_vhcaddq_rot270_s32_undef:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vhcadd.s32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}, #270
+; CHECK-NOT: vhcadd.s32 q[[REG:[0-9]+]], q{{[0-9]+}}, q[[REG]], #270
+; CHECK-NEXT: bx lr
+entry:
+ %0 = tail call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 0, i32 1, <4 x i32> undef, <4 x i32> undef)
+ ret <4 x i32> %0
+}
+
define arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot90_x_s8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vhcaddq_rot90_x_s8:
; CHECK: @ %bb.0: @ %entry
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