[llvm] [AMDGPU] Pick available high VGPR for CSR SGPR spilling (PR #78669)

[Christudasan Devadasan via llvm-commits]

================
@@ -312,6 +312,35 @@ bool SIMachineFunctionInfo::isCalleeSavedReg(const MCPhysReg *CSRegs,
   return false;
 }
 
+void SIMachineFunctionInfo::shiftSpillPhysVGPRsToLowestRange(
+    MachineFunction &MF) {
+  for (unsigned I = 0, E = SpillPhysVGPRs.size(); I < E; ++I) {
+    Register Reg = SpillPhysVGPRs[I];
+    const SIRegisterInfo *TRI =
+        MF.getSubtarget<GCNSubtarget>().getRegisterInfo();
+    MachineRegisterInfo &MRI = MF.getRegInfo();
+    Register NewReg =
+        TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF);
+    if (!NewReg || NewReg >= Reg)
+      continue;
+
+    MRI.replaceRegWith(Reg, NewReg);
+
+    // Update various tables with the new VGPR.
+    SpillPhysVGPRs[I] = NewReg;
+    WWMReservedRegs.remove(Reg);
+    WWMReservedRegs.insert(NewReg);
+    WWMSpills.insert(std::make_pair(NewReg, WWMSpills[Reg]));
+    WWMSpills.erase(Reg);
+
+    for (MachineBasicBlock &MBB : MF) {
+      MBB.removeLiveIn(Reg);
+      MBB.addLiveIn(NewReg);
+      MBB.sortUniqueLiveIns();
+    }
----------------
cdevadas wrote:

Adding the `NewReg` here can be avoided as all wwm-registers are already added into BB LiveIns during `SIFrameLowering::determineCalleeSaves`. But `Reg` has to be removed from the BBLiveIns which was added earlier in `SIMachineFunctionInfo::allocatePhysicalVGPRForSGPRSpills` while spilling CSR SGPR into VGPR.
Adding them into the BBLiveIns is required for their spill stores and restores later inserted at respective prolog and epilog blocks to avoid the MIR verifier error.

https://github.com/llvm/llvm-project/pull/78669